JPH04142094A - Board for placing electronic component - Google Patents
Board for placing electronic componentInfo
- Publication number
- JPH04142094A JPH04142094A JP26604290A JP26604290A JPH04142094A JP H04142094 A JPH04142094 A JP H04142094A JP 26604290 A JP26604290 A JP 26604290A JP 26604290 A JP26604290 A JP 26604290A JP H04142094 A JPH04142094 A JP H04142094A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- resin
- thermal expansion
- base material
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000463 material Substances 0.000 claims abstract description 41
- 239000000919 ceramic Substances 0.000 claims abstract description 40
- 239000002131 composite material Substances 0.000 claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 38
- 239000011347 resin Substances 0.000 claims abstract description 38
- 239000011148 porous material Substances 0.000 claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 13
- 239000000805 composite resin Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims description 33
- 229910052878 cordierite Inorganic materials 0.000 description 16
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 16
- 239000003822 epoxy resin Substances 0.000 description 10
- 229920000647 polyepoxide Polymers 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000004744 fabric Substances 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 5
- 239000002253 acid Substances 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 3
- 229910052863 mullite Inorganic materials 0.000 description 3
- 238000007750 plasma spraying Methods 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N Acrylic acid Chemical compound OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 2
- 229910000505 Al2TiO5 Inorganic materials 0.000 description 2
- CERQOIWHTDAKMF-UHFFFAOYSA-N Methacrylic acid Chemical compound CC(=C)C(O)=O CERQOIWHTDAKMF-UHFFFAOYSA-N 0.000 description 2
- 239000004962 Polyamide-imide Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910000174 eucryptite Inorganic materials 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000007849 furan resin Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920002312 polyamide-imide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- AABBHSMFGKYLKE-SNAWJCMRSA-N propan-2-yl (e)-but-2-enoate Chemical compound C\C=C\C(=O)OC(C)C AABBHSMFGKYLKE-SNAWJCMRSA-N 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 2
- 229910052845 zircon Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- CNLWCVNCHLKFHK-UHFFFAOYSA-N aluminum;lithium;dioxido(oxo)silane Chemical compound [Li+].[Al+3].[O-][Si]([O-])=O.[O-][Si]([O-])=O CNLWCVNCHLKFHK-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052642 spodumene Inorganic materials 0.000 description 1
- 239000002759 woven fabric Substances 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は電子部品搭載用基板に関し、特に表面実装用の
薄型フラットパッケージ集積回路が搭載される電子部品
搭載用基板に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a substrate for mounting electronic components, and more particularly to a substrate for mounting electronic components on which a thin flat package integrated circuit for surface mounting is mounted.
（従来の技術）
電子部品搭載用基板は、電子部品等を互いに電気的に接
続しながら支持するために、所定の剛性を有する絶縁基
材とこれに形成される導体回路とを有するものであるが
、その内の特に絶縁基材については、種々な材料のもの
か既に数多く提案されている。(Prior Art) An electronic component mounting board has an insulating base material having a predetermined rigidity and a conductive circuit formed thereon in order to support electronic components while electrically connecting them to each other. However, among these, many proposals have already been made regarding insulating base materials made of various materials.
この種の絶縁基材として一般に使用されているものは、
ガラスクロスにエポキシ樹脂を含浸して形成した所謂ガ
ラエポ基材であるが、このガラエボ基材は熱膨張率が大
きいことから、フラットパッケージ等の表面実装用の電
子部品が搭載される電子部品搭載用基板を構成する材料
としては好ましくないものである。すなわち、ガラエボ
基材を例にとってみると、その熱膨張率は約１５×１０
−６／℃であって、これに搭載されるフラットパッケー
ジ集積回路は最近小さく且つ薄くなりツツあり、特にＴ
Ｓ ＯＰ （Ｔｈｉｎ Ｓｍａｌｌ Ｏｕｔｌｉｎｅ
Ｐａｃｋａｇｅ ）と呼ばれるパッケージ厚みが１．２
ｍｍ以下の薄型のフラットパッケージ集積回路の熱膨張
率は約８ Ｘ １０−６／℃であり、絶縁基材側で１５
Ｘ １０−６／℃以上の熱膨張率を有していることは
次のような不都合な現象を生じさせるものである。Commonly used insulating base materials of this type are:
This is a so-called glass-epoxy base material made by impregnating glass cloth with epoxy resin.Since this glass-evo base material has a high coefficient of thermal expansion, it is suitable for mounting electronic components such as flat packages on which surface-mounted electronic components are mounted. It is not preferable as a material constituting the substrate. In other words, taking the Gala Evo base material as an example, its coefficient of thermal expansion is approximately 15 x 10
-6/℃, and the flat package integrated circuits mounted on these have recently become smaller and thinner, especially T
S OP (Thin Small Outline
Package thickness is 1.2
The coefficient of thermal expansion of a thin flat package integrated circuit of less than mm is approximately 8 x 10-6/°C, and the coefficient of thermal expansion on the insulating base material side is 15
Having a coefficient of thermal expansion of X 10-6/°C or more causes the following disadvantageous phenomena.
即ち、電子部品搭載用基板上の導体回路に対して前記薄
型のフラットパッケージ集積回路（以下単にフラットパ
ッケージと称す）を実装する際には熱が加えられるので
あるか、前述したようにフラットパッケージと絶縁基材
との間の熱膨張率に大きな差かあると、前記加熱により
絶縁基材とフラットパッケージの間に寸法差が生じ導体
回路とリードのピッチかすれて接続されなかったり、シ
ョート不良が生じることがある。このことは、近年その
高密度化及び高容量化のために、フラットパッケージ自
体の大きさかそれまでの８ｍｒ＋＋程度から１２〜１６
ｍｍ程度にまで大きくなっていること、及びフラットパ
ッケージ自体のビン数か格段に増加してその間隔か小さ
くなってきていること等によって、より一層顕著になっ
てきているのである。That is, is heat applied when the thin flat package integrated circuit (hereinafter simply referred to as a flat package) is mounted on a conductor circuit on a board for mounting electronic components? If there is a large difference in thermal expansion coefficient between the insulating base material and the insulating base material, the heating will cause a dimensional difference between the insulating base material and the flat package, causing the pitch of the conductor circuit and the lead to become blurred, resulting in poor connection or short-circuiting. Sometimes. This means that in recent years, due to the increase in density and capacity, the size of the flat package itself has changed from the previous 8 mr++ to 12 to 16 mr.
This problem has become even more noticeable due to the fact that the size of the bins has increased to about 1.0 mm, and the number of bins in the flat package itself has increased significantly and the spacing between them has become smaller.
また、フラットパッケージをこの電子部品搭載用基板に
実装した後には、膨張した絶縁基材が収縮するのである
が、フラットパッケージと絶縁基材との間に前述したよ
うな熱膨張率の差があると、収縮量の差により電子部品
のリードに歪が生じ、結果としてリードの接続不良を生
じてしまう。Furthermore, after the flat package is mounted on this electronic component mounting board, the expanded insulating base material contracts, but there is a difference in thermal expansion coefficient between the flat package and the insulating base material as mentioned above. The difference in the amount of shrinkage causes distortion in the leads of the electronic component, resulting in poor connection of the leads.
そこで、本発明者等は、絶縁基材と電子部品の熱膨張率
の差の課題を解決するにはどうしたらよいかについて種
々検討を重ねてきた結果、本発明を完成したのである。Therefore, the present inventors have completed the present invention as a result of various studies on how to solve the problem of the difference in coefficient of thermal expansion between the insulating base material and the electronic component.
（発明が解決しようとする課題）
本発明は、以上の経緯に基づいてなされたもので、その
解決しようとする課題は、従来の電子部品搭載用基板を
構成している絶縁基材とこれに実装されるフラットパッ
ケージとの熱膨張率の大きな差である。(Problems to be Solved by the Invention) The present invention has been made based on the above-mentioned circumstances, and the problems to be solved are the insulating base material constituting the conventional board for mounting electronic components, This is a large difference in thermal expansion coefficient from that of the flat package on which it is mounted.
そして、本発明の目的とするところは、絶縁基材とフラ
ットパッケージとの熱膨張率の差を極力小さくすること
ができて、その電気的接続の信頼性を高め、かつフラッ
トパッケージの破損を防止することのできる電子部品搭
載用基板を提供することにある。The purpose of the present invention is to minimize the difference in thermal expansion coefficient between the insulating base material and the flat package, improve the reliability of the electrical connection, and prevent damage to the flat package. An object of the present invention is to provide a board for mounting electronic components that can be used to mount electronic components.
（課題を解決するための手段及びその作用）以上のよう
な課題を解決するために請求項１の発明が採った手段は
図面に示した符号を付して説明すると、第１図において
［絶縁基材（１０）とこの絶縁基材（ｌＯ）上に形成さ
れた導体回路（４）とを有すると共にフラットパッケー
ジ集積回路（１）との熱膨張率を近似させた電子部品搭
載用基板（２０）であって、
前記絶縁基材（１０）を、セラミック複合体又はセラミ
ック複合体（２）の少なくとも前記導体回路（４）が形
成される面に樹脂層又は樹脂複合層（３）を形成したも
のより構成し、且つ、前記セラミック複合体（２）を、
熱膨張率が６ｘｌＯ−’／’Ｃ以下で気孔率が５〜５０
容量％のセラミック多孔質体の気孔の９５％以上に樹脂
を充填して構成すると共に、前記セラミック複合体（２
）の厚みが前記電子部品搭載用基板（２０）の厚みの９
５〜４０％を占めるように構成したことを特徴とする電
子部品搭載用基板（２０）Ｊをその要旨とするものであ
る。(Means for Solving the Problems and Their Effects) The means taken by the invention of claim 1 to solve the above-mentioned problems will be described with reference numerals shown in the drawings. An electronic component mounting substrate (20) having a base material (10) and a conductor circuit (4) formed on the insulating base material (10) and having a coefficient of thermal expansion similar to that of the flat package integrated circuit (1). ), wherein the insulating base material (10) is formed with a resin layer or a resin composite layer (3) on at least the surface of the ceramic composite or the ceramic composite (2) on which the conductor circuit (4) is formed. and the ceramic composite (2) comprises:
Thermal expansion coefficient is 6xlO-'/'C or less and the porosity is 5 to 50.
% by volume of the pores of the ceramic porous body are filled with resin, and the ceramic composite (2
) is 9 of the thickness of the electronic component mounting board (20).
The gist thereof is a substrate (20) J for mounting electronic components, characterized in that it is configured to occupy 5 to 40%.
つまり、絶縁基材（１０）とフラットパッケージ（１）
の熱膨張率を近似させたのである。そして、その近似さ
せる具体的手段として、絶縁基材（１０）をセラミック
複合体（２）又はセラミック複合体（２）と樹脂層又は
樹脂複合層（３）とから構成し、これらのセラミック複
合体（２）及び樹脂層又は樹脂複合層（３）を次のよう
なものとしたのである。In other words, the insulating base material (10) and the flat package (1)
The coefficient of thermal expansion was approximated. As a specific means for approximating this, the insulating base material (10) is composed of a ceramic composite (2) or a ceramic composite (2) and a resin layer or a resin composite layer (3), and these ceramic composites are (2) and the resin layer or resin composite layer (3) were made as follows.
すなわち、セラミック複合体（２）は、熱膨張率が６ｘ
ｌＯ−６／’Ｃ以下であって、その気孔率が５〜５０容
量％のセラミック多孔質体に樹脂を充填し、その充填の
割合がセラミック多孔質体の気孔の９５％以上を占める
ようにしたのである。ここで、セラミック多孔質体（２
）の熱膨張率を６×１０−”／’Ｃ以下としタノハ、仮
１：６Ｘ１０−＠／”Ｃより大きいと気孔の中に樹脂が
入った場合に熱膨張率が大きくなり、フラットパッケー
ジ（１）の熱膨張率に近い５〜ｌ０ＸＩＯ−”／”Ｃの
熱膨張率を維持することができないからである。また、
このセラミック多孔質体の気孔率を５〜ｂ
上としたのは、仮に、気孔率が５容量％より小さいと気
孔が微細化しすぎて、樹脂がこの気孔に入らなくなるか
らであり、気孔率が５０容量％より大きくなるとこの気
孔に充填される樹脂の割合が大きくなりすぎ、そうなる
と熱膨張率が大きくなってしまうからである。さらに、
気孔への樹脂の割合を９５％以上としたのは、気孔の９
５％以上に樹脂が充填されていないと、その気孔が外部
と連通ずる気孔となってしまい、この絶縁基材の耐湿性
が低下し、結果として電子部品搭載用基板（２０）とし
ての接続信頼性が低下してしまうからである。That is, the ceramic composite (2) has a coefficient of thermal expansion of 6x
A ceramic porous body having a porosity of 5 to 50% by volume and having a porosity of 1O-6/'C or less is filled with a resin so that the filling ratio accounts for 95% or more of the pores of the ceramic porous body. That's what I did. Here, the ceramic porous body (2
Tanoha tentatively assumes that the thermal expansion coefficient of 6 x 10-''/'C is below 1:6 x 10-''/'C, and if the thermal expansion coefficient is greater than 1:6 This is because it is not possible to maintain a thermal expansion coefficient of 5 to 10XIO-''/''C, which is close to the thermal expansion coefficient of 1). Also,
The reason why the porosity of this ceramic porous body is set to 5-b is because if the porosity was smaller than 5% by volume, the pores would become too fine and the resin would not be able to enter the pores. This is because if it exceeds 50% by volume, the proportion of the resin that fills the pores becomes too large, resulting in an increase in the coefficient of thermal expansion. moreover,
The proportion of resin in the pores was set to 95% or more because 9 of the pores
If the resin is not filled to 5% or more, the pores will become pores that communicate with the outside, reducing the moisture resistance of this insulating base material, resulting in poor connection reliability as a board for mounting electronic components (20). This is because the quality decreases.
なお、ここで使用されるセラミック多孔質体（２）の成
分及び充填される樹脂の種類は、本発明の場合特に限定
されるものではないが、例えば、セラミック多孔質体と
しては、コージェライト、ムライト、ユークリプタイト
、スポジュメン、チタン酸アルミニウム、ジルコン、石
英、炭化ケイ素、窒化ケイ素、窒化アルミニウムあるい
はこれらのいずれか少なくとも一種以上からなる複合初
等使用することができるが、なかでも電気絶縁性に優れ
たコージェライト、ムライト、窒化アルミニウムを使用
することが有効である。充填される樹脂としては、エポ
キシ樹脂、ポリイミド樹脂、トリアジン樹脂、ポリパラ
バン酸樹脂、ポリアミドイミド樹脂、シリコン樹脂、ア
クリル酸樹脂、メタクリル酸樹脂、アニリン酸樹脂、フ
ェノール樹脂、ウレタン樹脂、フラン樹脂、フッ素樹脂
、あるいはこれらの樹脂混合物が好適である。Note that the components of the ceramic porous body (2) used here and the type of resin to be filled are not particularly limited in the case of the present invention, but for example, as the ceramic porous body, cordierite, Mullite, eucryptite, spodumene, aluminum titanate, zircon, quartz, silicon carbide, silicon nitride, aluminum nitride, or composite materials consisting of at least one of these can be used, but among them, materials with excellent electrical insulation properties can be used. It is effective to use cordierite, mullite, and aluminum nitride. The resins to be filled include epoxy resin, polyimide resin, triazine resin, polyparabanic acid resin, polyamideimide resin, silicone resin, acrylic acid resin, methacrylic acid resin, anilic acid resin, phenol resin, urethane resin, furan resin, and fluororesin. or a mixture of these resins is suitable.
次に、本発明は上記のようなセラミック複合体（２）の
少なくともいずれか一面に、樹脂層又は樹脂複合層（３
）を設けたのである。少なくともいずれかの一面とは導
体回路（４）が形成される少なくとも一面であって、セ
ラミック複合体（２）の両面にこの樹脂層又は樹脂複合
層（３）を設けても良い。Next, the present invention provides a resin layer or a resin composite layer (3) on at least one surface of the ceramic composite (2) as described above.
) was established. At least one surface is at least one surface on which the conductor circuit (4) is formed, and this resin layer or resin composite layer (3) may be provided on both surfaces of the ceramic composite (2).
そして、このセラミック複合体（２）は、当該電子部品
搭載用基板（２０）の総厚みに対して９５〜４０％を占
めるように形成する必要がある。ここで、このセラミッ
ク複合体（２）の占める割合が基板の総厚みの９５〜４
０％としたのは、９５％より大きいと絶縁基材（１０）
の厚み方向の熱膨張率が１０ｘｌＯ−６／℃以下となっ
てしまいこのような基板に設けられるスルーホールを構
成する銅や銀−Ｐｄ等の熱膨張率（１０〜２０ Ｘ １
０−６／℃）より小さくなり、当該スルーホールにおけ
る接続信頼性が低下するからである。また、このセラミ
ック複合体（２）の占める割合が基板の総厚みに対して
４０％より小さいと逆にこの絶縁基材（１０）の厚み方
向の熱膨張率が４０ Ｘ １０−６／℃以上となって、
これもまた当該スルーホールにおける接続信頼性を低下
させるからである。This ceramic composite (2) needs to be formed so as to occupy 95 to 40% of the total thickness of the electronic component mounting substrate (20). Here, the proportion of this ceramic composite (2) is 95 to 4 of the total thickness of the substrate.
0% is used for insulation base material (10) when it is greater than 95%.
The coefficient of thermal expansion in the thickness direction of the substrate is less than 10xlO-6/°C.
0-6/°C), and the connection reliability in the through-hole decreases. In addition, if the proportion of this ceramic composite (2) is less than 40% of the total thickness of the substrate, conversely, the coefficient of thermal expansion in the thickness direction of this insulating base material (10) is 40 x 10-6/°C or more. So,
This is because this also reduces the connection reliability in the through hole.
なお、ここで使用される樹脂層又は樹脂複合層（３）の
材質については、本発明の場合、特に限定されるもので
はないが、樹脂層（３）としては、エポキシ樹脂、ポリ
イミド樹脂、トリアジン樹脂、ポリパラバン酸樹脂、ポ
リアミドイミド樹脂、シリコン樹脂、アクリル酸樹脂、
メタクリル酸樹脂、アニリン酸樹脂、フェノール樹脂、
ウレタン樹脂、フラン樹脂を、樹脂複合層（３）として
は、上記樹脂にアルミナ、石英、コージェライト、ムラ
イト、ユークリプタイト、スボジュメン、チタン酸アル
ミニウム、ジルコン、炭化ケイ素、窒化ケイ素、窒化ア
ルミニウムなどの粉末、あるいは単繊維、長繊維の不織
布、織物あるいはそれらの混合物が含まれて使用するの
が好適である。The material of the resin layer or resin composite layer (3) used here is not particularly limited in the case of the present invention, but the resin layer (3) may be made of epoxy resin, polyimide resin, triazine resin, etc. Resin, polyparabanic acid resin, polyamideimide resin, silicone resin, acrylic acid resin,
Methacrylic acid resin, anilic acid resin, phenolic resin,
The resin composite layer (3) is made of a urethane resin or a furan resin, and the resin is combined with alumina, quartz, cordierite, mullite, eucryptite, subodumene, aluminum titanate, zircon, silicon carbide, silicon nitride, aluminum nitride, etc. It is preferable to use a powder, a single fiber, a long fiber nonwoven fabric, a woven fabric, or a mixture thereof.
本発明によれば、フラットノ寸・ソケージ（１）か搭載
される部分を少なくともセラミ・ツク複合体（２）の占
める割合か基板（２０）の総厚みに対して９５〜４０％
を占めるように形成する必要がある。According to the present invention, the portion to be mounted on the flat cage (1) is at least 95 to 40% of the proportion of the ceramic composite (2) or the total thickness of the substrate (20).
It is necessary to form it so that it occupies .
また、本発明によれば、他の電子回路部品（１）の熱膨
張率に応じてセラミ・ツク複合体（２）の占める割合が
、基板（１）の総厚みに対して９５〜４０％の範囲内で
基板（１）の各部分で異なっていても良い。これにより
さらに接続信頼性に富んだ基板（２０）を得ることかで
きる。Further, according to the present invention, the proportion of the ceramic composite (2) in accordance with the coefficient of thermal expansion of the other electronic circuit components (1) is 95 to 40% of the total thickness of the substrate (1). It may be different for each part of the substrate (1) within the range of . This makes it possible to obtain a substrate (20) with even higher connection reliability.
以上のように構成することにより、本発明に係る電子部
品搭載用基板（２０）は、その表面方向の熱膨張率が３
〜ｌ０ＸＩＯ−６／℃となり、厚み方向の熱膨張率が１
０〜４０ Ｘ １０−６／℃となるため、フラットパッ
ケージ（１）の熱膨張率（３〜８×１０−６／℃）を、
スルーホールを構成する銅又は銀−Ｐｄ等の熱膨張率（
１０−２０Ｘ１０−６／℃）に近似させることができ、
よって、フラ・ソトノく・ソケージ（１）の実装時等に
おける熱歪による接続不良やチップ割れを回避すること
ができるのである。With the above configuration, the electronic component mounting substrate (20) according to the present invention has a thermal expansion coefficient of 3 in the surface direction.
~l0XIO-6/℃, and the coefficient of thermal expansion in the thickness direction is 1
0 to 40 x 10-6/℃, so the coefficient of thermal expansion of the flat package (1) (3 to 8 x 10-6/℃) is
Thermal expansion coefficient (
10-20X10-6/℃),
Therefore, it is possible to avoid connection failures and chip cracks due to thermal distortion during mounting of the frame, socket, and socket (1).
（実施例）
次に、本発明に係る電子部品搭載用基板（２０）の各実
施例を説明する。(Example) Next, each example of the electronic component mounting board (20) according to the present invention will be described.
塞」１例」２
第１図及び第２図は本発明の電子部品搭載用基板（２０
）を具体的に示した図である。この電子部品搭載用基板
（２０）には、フラットパッケージ（１）が実装されて
おり、前記基板（２０）は、セラミ・ツク複合体（２）
および樹脂あるいは樹脂複合層（３）の絶縁基材（１０
）と導体回路（４）とから形成されている。Figures 1 and 2 show an electronic component mounting board (20) of the present invention.
) is a diagram specifically showing. A flat package (1) is mounted on this electronic component mounting board (20), and a ceramic-tsuku composite (2) is mounted on the board (20).
and an insulating base material (10
) and a conductor circuit (4).
本実施例では、セラミック複合体（２）として気孔率２
７％のコージェライト焼結体（熱膨張率２ ｘ １０−
６／℃）の気孔部にエポキシ樹脂が約１００％含浸され
たものを使用した。第２図は総厚み１．８ｍｍに対し前
記セラミ・ツク複合体（２）の厚みを０．８ｍｍとし上
下に熱膨張率５．２×１０−’／’Ｃのガラスクロス直
径０．１ｍｍを含んだエポキシ樹脂複合層（３）と銅箔
とを熱圧着によって前記基板に積層して製作した基板（
２０）である。この基板（２０）の水平方向の熱膨張率
は５．８ｘ １０−’／’Ｃであり、また、基板（２０
）の厚み方向の熱膨張率は１７． ８ Ｘ １０−’／
”Ｃであった。In this example, the ceramic composite (2) has a porosity of 2
7% cordierite sintered body (thermal expansion coefficient 2 x 10-
6/°C) in which the pores were approximately 100% impregnated with epoxy resin. In Fig. 2, the thickness of the ceramic-tsuku composite (2) is 0.8 mm for a total thickness of 1.8 mm, and glass cloth with a thermal expansion coefficient of 5.2 x 10-'/'C is placed above and below with a diameter of 0.1 mm. A substrate (
20). The horizontal thermal expansion coefficient of this substrate (20) is 5.8x 10-'/'C, and the substrate (20)
) has a coefficient of thermal expansion in the thickness direction of 17. 8 x 10-'/
“It was C.
第３図は銅箔の片面にコージェライト粉末をプラズマ溶
射によってコージェライト多孔質層（２）を形成したも
のに熱膨張率５．２Ｘ１０−６／℃のガラスクロス０．
１ｍｍを含んだエポキシ樹脂複合層（３）と熱圧着によ
って張り合わせた基板から製作した基材（１０）である
。なお前記コージェライト多孔質層（２）の気孔率は１
３％であってエポキシ樹脂複合層（３）との熱圧着時に
９８％の気孔にエポキシ樹脂が充填されていた。この基
板（２０）の総厚みは０．３０ｍｍであり、前記コージ
ェライト複合層（２）の厚みは０．１５ｍｍであった。Figure 3 shows a cordierite porous layer (2) formed on one side of a copper foil by plasma spraying cordierite powder and a glass cloth with a thermal expansion coefficient of 5.2 x 10-6/°C.
This is a base material (10) manufactured from an epoxy resin composite layer (3) containing 1 mm thick and a substrate bonded together by thermocompression bonding. The porosity of the cordierite porous layer (2) is 1
3%, and 98% of the pores were filled with epoxy resin during thermocompression bonding with the epoxy resin composite layer (3). The total thickness of this substrate (20) was 0.30 mm, and the thickness of the cordierite composite layer (2) was 0.15 mm.
この基板（２０）の水平方向の熱膨張率は６，８×１０
−’／’Ｃであり、また、基板（２０）の厚み方向の熱
膨張率は２４．６×１０−’／’Ｃであった。The horizontal thermal expansion coefficient of this substrate (20) is 6.8×10
-'/'C, and the coefficient of thermal expansion in the thickness direction of the substrate (20) was 24.6 x 10-'/'C.
いずれの基板（２０）もフラットパッケージ（１）の熱
膨張率と近く、また、スルホール導体の銅の熱膨張率１
８ Ｘ １０−６／’Ｃと極めて近いものである。Both substrates (20) have a coefficient of thermal expansion close to that of the flat package (1), and the coefficient of thermal expansion of copper of the through-hole conductor is 1.
It is very close to 8 x 10-6/'C.
一方、第２図において、コージェライトの代わりにアル
ミナ多孔質層（熱膨張率７ Ｘ １０−６／℃）によっ
て同様の基板（２０）を形成したもの、コージェライト
の気孔率を５８％としたもの、樹脂の充填率を８８％と
したもの、コージェライト複合層の厚みを０．３ｍｍと
したもの、そしてすべての絶縁層を熱膨張率５．２Ｘ１
０−６／℃のガラスクロス０．１ｍｍを含んだエポキシ
樹脂複合層で構成した基板（２０）によって形成したも
のの各試験結果を表１にまとめた。On the other hand, in Figure 2, a similar substrate (20) was formed using an alumina porous layer (thermal expansion coefficient 7 x 10-6/℃) instead of cordierite, and the porosity of cordierite was set to 58%. one with a resin filling rate of 88%, one with a cordierite composite layer thickness of 0.3 mm, and all insulation layers with a thermal expansion coefficient of 5.2 x 1.
Table 1 summarizes the test results for the substrate (20) made of an epoxy resin composite layer containing 0.1 mm of 0-6/°C glass cloth.
一方、これらの基板（２０）にフラットパッケージ（１
）を実装した時の実装不良発生数と、−６５℃〜１２５
℃の熱衝撃試験および８５℃、８５％の恒温恒湿試験を
１０００時間評価した結果も同表にまとめた。この結果
本発明の基板はフラットパッケージ（１）の実装に極め
て有効であり、電気的にも優れた接続信頼性を有してい
ることが分かる。On the other hand, a flat package (1
) and the number of mounting defects when mounting -65℃ to 125℃
The results of a thermal shock test at 85° C. and a constant temperature and humidity test at 85° C. and 85% for 1000 hours are also summarized in the same table. As a result, it can be seen that the substrate of the present invention is extremely effective for mounting the flat package (1) and has excellent electrical connection reliability.
犬１１１１
実施例１で用いた０、８ｍｍのコージェライト複合層（
２）の表面に銅箔を直接熱圧着し、導体回路（４）を形
成した。ついでフラットパッケージ（１）の搭載部分に
相当する位置に前記銅箔の片面にコージェライト粉末を
プラズマ溶射によってコージェライト多孔質層を部分的
に形成したものに熱膨張率５．２Ｘ１０−’／’Ｃのガ
ラスクロス０． １ｍｍを含んだエポキシ樹脂複合層（
３）と熱圧着によって張り合わせた。この銅箔の片面に
コージェライト粉末をプラズマ溶射によってコージェラ
イト多孔質層を部分的に形成した銅箔およびガラスクロ
ス０．１ｍｍを含んだエポキシ樹脂複合層（３）の同位
置に、予めＩＣペアチップ（５）か直接基板に実装され
る部分か削除されている。こうして得られた基板は第４
図の如く形成された多層の基板（２０）である。Dog 1111 0.8 mm cordierite composite layer used in Example 1 (
A conductive circuit (4) was formed by directly thermocompressing copper foil onto the surface of 2). Next, a cordierite porous layer was partially formed on one side of the copper foil by plasma spraying cordierite powder at a position corresponding to the mounting part of the flat package (1), and a thermal expansion coefficient of 5.2X10-'/' was applied. C glass cloth 0. Epoxy resin composite layer containing 1 mm (
3) and pasted together by thermocompression bonding. An IC pair chip is placed in advance at the same position on an epoxy resin composite layer (3) containing a copper foil and glass cloth 0.1 mm thick, in which a cordierite porous layer is partially formed on one side of the copper foil by plasma spraying cordierite powder. (5) The part that is directly mounted on the board has been deleted. The thus obtained substrate is the fourth
This is a multilayer substrate (20) formed as shown in the figure.
この基板（２０）においてＩＣヘアチップ（５）か搭載
される部分、フラットパッケージ（１）の搭載部分、そ
して他の部品（６）が実装される部分の基板特性を表２
にまとめると共に接続信頼性等の評価結果もまとめた。Table 2 shows the board characteristics of the part of this board (20) where the IC hair chip (5) is mounted, the part where the flat package (1) is mounted, and the part where other components (6) are mounted.
In addition to summarizing the results, we also summarized the evaluation results of connection reliability, etc.
本発明によれば、電子部品の種類に応じて基板の層の構
成を可変することによって、より信頼性の高い実装が実
現できる。According to the present invention, more reliable mounting can be achieved by changing the configuration of the layers of the board depending on the type of electronic component.
（以下余白）
（発明の効果）
以上詳述したように、本発明に係る電子部品搭載用基板
は、「絶縁基材とこの絶縁基材上に形成された導体回路
とを有すると共にフラットパッケージ集積回路との熱膨
張率を近似させた電子部品搭載用基板であって、
前記絶縁基材を、セラミック複合体又はセラミック複合
体の少なくとも前記導体回路が形成される面に樹脂層又
は樹脂複合層を形成したものより構成し、且つ、前記セ
ラミック複合体を、熱膨張率が６Ｘ１０−’／”Ｃ以下
で気孔率が５〜５０容量％のセラミック多孔質体の気孔
の９５％以上に樹脂を充填して構成すると共に、
前記セラミック複合体の厚みが前記電子部品搭載用基板
の厚みの９５〜４０％を占めるように構成したこと」を
その構成上の特徴としている。(Left below) (Effects of the Invention) As detailed above, the electronic component mounting board according to the present invention "has an insulating base material and a conductor circuit formed on the insulating base material, and is also capable of flat package integration. A board for mounting electronic components having a thermal expansion coefficient similar to that of a circuit, wherein the insulating base material is a ceramic composite or a ceramic composite with a resin layer or a resin composite layer on at least the surface on which the conductor circuit is formed. 95% or more of the pores of the ceramic porous body having a thermal expansion coefficient of 6 x 10-'/''C or less and a porosity of 5 to 50% by volume are filled with a resin. The structure is characterized in that the thickness of the ceramic composite occupies 95 to 40% of the thickness of the electronic component mounting board.
従って、この電子部品搭載用基板によれば、その表面方
向の熱膨張率が３〜ｌ０ＸＩＯ−’／”Ｃとなり、その
厚み方向の熱膨張率も１０〜３０×１０−’／’Ｃとな
るため、フラットパッケージ及びスルーホールを構成す
る銅等の熱膨張率に近似させることができ、よって、両
者の熱膨張率の差を極力小さくすることができて、その
電気的接続の信頼性を高めることができると共に、電子
部品の破損をも防止することができる。Therefore, according to this board for mounting electronic components, the coefficient of thermal expansion in the surface direction is 3 to 10XIO-'/'C, and the coefficient of thermal expansion in the thickness direction is also 10 to 30x10-'/'C. Therefore, the coefficient of thermal expansion can be approximated to that of copper, etc. that constitutes the flat package and through-hole, and therefore, the difference in the coefficient of thermal expansion between the two can be minimized, increasing the reliability of the electrical connection. At the same time, it is possible to prevent damage to electronic components.
よって、この基板を使用することで今後増々高密度化さ
れる電子部品あるいは装置に対して極めて有効な手段と
なる。たとえば、メモリーモジュール、薄型のメモリー
カード、ＩＣカード、ハンディムービー用のモジュール
、カメラモジュール、ハンディパソコン、ブックパソコ
ン、電子手帳、ハンディワープロ、ブックワープロ等の
小型高性能製品に使用が可能である。Therefore, the use of this substrate becomes an extremely effective means for electronic components or devices that will become increasingly denser in the future. For example, it can be used in small, high-performance products such as memory modules, thin memory cards, IC cards, handy movie modules, camera modules, handy computers, book computers, electronic notebooks, handy word processors, and book word processors.
第１図は本発明に係る電子部品搭載用基板の第一実施例
を示す平面図、第２図は第１図におけるＡ−Ａ断面図、
第３図は第二実施例に係る電子部品搭載用基板の第２図
に対応する断面図、第４図は第三実施例に係る電子部品
搭載用基板の第２図に対応する断面図である。
符 号 の 説 明
１・・・フラットパッケージ集積回路、２・・・セラミ
ック複合体、３・・・樹脂層又は樹脂複合層、４・・導
体回路、５・・・ＩＣペアチップ、６・・・抵抗チップ
、１０・・・絶縁基材、２０・・・電子部品搭載用基板
。
以 上FIG. 1 is a plan view showing a first embodiment of the electronic component mounting board according to the present invention, FIG. 2 is a cross-sectional view taken along line A-A in FIG.
3 is a sectional view corresponding to FIG. 2 of the electronic component mounting board according to the second embodiment, and FIG. 4 is a sectional view corresponding to FIG. 2 of the electronic component mounting board according to the third embodiment. be. Explanation of symbols 1...Flat package integrated circuit, 2...Ceramic composite, 3...Resin layer or resin composite layer, 4...Conductor circuit, 5...IC pair chip, 6... Resistance chip, 10... Insulating base material, 20... Electronic component mounting board. that's all
Claims (1)
とを有すると共にフラットパッケージ集積回路との熱膨
張率を近似させた電子部品搭載用基板であって、 前記絶縁基材を、セラミック複合体又はセラミック複合
体の少なくとも前記導体回路が形成される面に樹脂層又
は樹脂複合層を形成したものより構成し、且つ、前記セ
ラミック複合体を、熱膨張率が６×１０＾−＾６／℃以
下で気孔率が５〜５０容量％のセラミック多孔質体の気
孔の９５％以上に樹脂を充填して構成すると共に、 前記セラミック複合体の厚みが前記電子部品搭載用基板
の厚みの９５〜４０％を占めるように構成したことを特
徴とする電子部品搭載用基板。 ２）．前記電子部品搭載用基板の少なくとも電子部品を
搭載する部分の前記セラミック複合体の厚みが、前記電
子部品搭載用基板の厚みに対して９５〜４０％を占める
ように構成したことを特徴とする請求項１記載の電子部
品搭載用基板。 ３）．前記電子部品搭載用基板の前記セラミック複合体
の厚みは、前記電子部品搭載用基板の厚みの９５〜４０
％の範囲内で部分的に可変であることを特徴とする請求
項１又は２記載の電子部品搭載用基板。[Claims] 1). A substrate for mounting electronic components, which has an insulating base material and a conductor circuit formed on the insulating base material, and has a coefficient of thermal expansion similar to that of a flat package integrated circuit, the insulating base material being a ceramic composite. or a ceramic composite in which a resin layer or a resin composite layer is formed on at least the surface on which the conductor circuit is formed, and the ceramic composite has a thermal expansion coefficient of 6 x 10^-^6/°C. 95% or more of the pores of a ceramic porous body having a porosity of 5 to 50% by volume are filled with resin, and the thickness of the ceramic composite is 95 to 40% of the thickness of the electronic component mounting substrate. % of the electronic component mounting board. 2). A claim characterized in that the thickness of the ceramic composite in at least a portion of the electronic component mounting substrate on which the electronic component is mounted is 95 to 40% of the thickness of the electronic component mounting substrate. Item 1. A substrate for mounting electronic components according to item 1. 3). The thickness of the ceramic composite of the electronic component mounting board is 95 to 40 times the thickness of the electronic component mounting board.
3. The electronic component mounting board according to claim 1, wherein the electronic component mounting board is partially variable within a range of %.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26604290A JP2750473B2 (en) | 1990-10-02 | 1990-10-02 | Substrate for mounting electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26604290A JP2750473B2 (en) | 1990-10-02 | 1990-10-02 | Substrate for mounting electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04142094A true JPH04142094A (en) | 1992-05-15 |
| JP2750473B2 JP2750473B2 (en) | 1998-05-13 |
Family
ID=17425588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26604290A Expired - Lifetime JP2750473B2 (en) | 1990-10-02 | 1990-10-02 | Substrate for mounting electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2750473B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015130426A (en) * | 2014-01-08 | 2015-07-16 | デクセリアルズ株式会社 | Connection method and conjugate |
-
1990
- 1990-10-02 JP JP26604290A patent/JP2750473B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015130426A (en) * | 2014-01-08 | 2015-07-16 | デクセリアルズ株式会社 | Connection method and conjugate |
| WO2015105098A1 (en) * | 2014-01-08 | 2015-07-16 | デクセリアルズ株式会社 | Connection method and assembly |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2750473B2 (en) | 1998-05-13 |
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