JPH04142053A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH04142053A
JPH04142053A JP2265475A JP26547590A JPH04142053A JP H04142053 A JPH04142053 A JP H04142053A JP 2265475 A JP2265475 A JP 2265475A JP 26547590 A JP26547590 A JP 26547590A JP H04142053 A JPH04142053 A JP H04142053A
Authority
JP
Japan
Prior art keywords
pads
integrated circuit
semiconductor integrated
probing
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2265475A
Other languages
Japanese (ja)
Inventor
Hidekatsu Nishimaki
秀克 西巻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2265475A priority Critical patent/JPH04142053A/en
Publication of JPH04142053A publication Critical patent/JPH04142053A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To ensure an interval between probes of a tester when a wafer test is executed by a method wherein, in addition to a bonding pad, a pad, for probing which is used to execute the wafer test is formed of a metal interconnection on an upper layer which is situated by another layer. CONSTITUTION:Metal interconnections 4 are formed in such a way that they connect pads 2 to pads 3 for probing use which are formed at the inside of a chip situated on an upper layer from a chip constitution and which are used to execute a wafer test. The bonding pads 2 are connected to an input, an output, a GND and a power supply of a semiconductor integrated circuit at the inside of a chip; the pads 3 for probing use are connected to them. When the pads 3 for probing and the bonding pads 3 are used jointly, an interval between the pads can be made large. Thereby, a probe for a tester can be brought into contact with all the pads 2, 3 in the same manner as in the case where all the bonding pads are probed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はウェハテストのための１０−ビング用のパッド
を形成した半導体集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device in which a 10-bing pad for wafer testing is formed.

〔従来の技術〕[Conventional technology]

従来の半導体集積回路装置は第４図のように形成されて
いた。図において、（１）は基板、（２）はボンディン
グパッドである。半導体集積回路はボンディングパッド
（２）で囲まれた領域の内部に形成されているが、この
図では省略しである。第４図の断面図を２層配線を用い
た場合について示し九のが第５図である。ボンディング
パッド（２）は１１（５１及び２Ａｊ（２）の２層によ
って形成されている。A conventional semiconductor integrated circuit device was formed as shown in FIG. In the figure, (1) is a substrate, and (2) is a bonding pad. Although the semiconductor integrated circuit is formed inside the region surrounded by the bonding pads (2), it is omitted in this figure. FIG. 5 shows the cross-sectional view of FIG. 4 in the case where two-layer wiring is used. The bonding pad (2) is formed of two layers: 11 (51) and 2Aj (2).

次に動作について説明する− ボン・ディングパッド（２）は基板（１）上に作られた
半導体集積回路の入力、出力、ＧＭＤ及び電源に接続さ
れており、ウェハテストを行う際にはこのボンディング
パッド（２）にテスタのプローブ（図示せず）を接触す
ることにより、半導体集積回路にバイアス及び、信号を
加えテストを行う。このテスタの７０−ブをボンディン
グパッド（２）に接触することをプロービングという。Next, we will explain the operation - The bonding pad (2) is connected to the input, output, GMD, and power supply of the semiconductor integrated circuit fabricated on the substrate (1). A test is performed by applying a bias and a signal to the semiconductor integrated circuit by contacting the pad (2) with a tester probe (not shown). Contacting the 70-b of the tester with the bonding pad (2) is called probing.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体集積回路装置はプロセスの微細化に伴い、
ボンディングパッドの間隔が小さくなって、ウェハテス
トを行う際にはテスタのプローブどうしが接触しないよ
うにプローブの間隔を取りつつ、間隔の小石＜表ったボ
ンディングパッド総てにプロービンブレなければならな
いので、テスタのプローブを細くする必要がある。しか
し、プローブの強度を考慮すると、プローブを細くする
ことに限界があり、この物理的限界によりボンディング
パッド間隔の小てい半導体集積回路装置では全ボンディ
ングパッドにプロービングすることが不可能となり、ウ
ェハテストが行えなくなるという問題点があった。Conventional semiconductor integrated circuit devices have become smaller due to process miniaturization.
As the spacing between bonding pads has become smaller, when performing a wafer test, it is necessary to keep the probes apart so that the tester probes do not touch each other, and to prevent the probe from shaking on all exposed bonding pads. The tester probe needs to be thinner. However, considering the strength of the probe, there is a limit to how thin the probe can be, and this physical limit makes it impossible to probe all bonding pads in semiconductor integrated circuit devices with small bonding pad spacing, making wafer testing difficult. There was a problem that it could not be done.

本発明は上記のような問題点を解決する念めになされた
もので、ウェハテストを行う際に、テスタのプローブの
間隔を十分とれるような半導体集積回路装置を得ること
を目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit device that allows a sufficient distance between probes of a tester when performing a wafer test.

〔課題を解決する念めの手段〕[A precautionary measure to solve the problem]

本発明に係る半導体集積回路装置は、従来のチップ構成
の更に一層上の金属配線を用いてボンディングパッドが
配列でれた領域の内側にウェハテストのためのプロービ
ング用のパッドを形成したものである。A semiconductor integrated circuit device according to the present invention has probing pads for wafer testing formed inside a region where bonding pads are arranged using metal wiring that is further above the conventional chip structure. .

〔作用〕[Effect]

本発明における半導体集積回路装置は、ウェハテストの
九めのプロービング用のパッドをボンディングパッドの
内側に形成することにより、全ボンディングパッドにプ
ロービングするのと同等となりウェハテストが可能とな
る。In the semiconductor integrated circuit device of the present invention, by forming the ninth probing pad for wafer testing inside the bonding pad, wafer testing becomes possible, which is equivalent to probing all bonding pads.

〔実施例〕〔Example〕

以下、本発明の一実施例を図について説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例である半導体集積回路装置の
平面図である。図中符号（１）及び（２）は前記従来の
ものと同一につき説明は省略する。図において、（８）
は従来のチップ構成の更に一層上の金属配線を用いてチ
ップ内部に形成されたウェハテストに用いるプロービン
グ用パッド、偽）はパッド（２）と（８）を接続する金
属配線である。第２図及び第３図は第１図のボンデイン
ギパッド（２）及びプロービング用パッド（８）の周辺
を２層配線によって構成された半導体集積回路装置の断
面図で、第２図は金属配線（４）として３Ａ／（７１を
、第３図は金属配線（４）としてＩＡＩ　（５！　、　
２Ａｌ　１６）、及び３Ａｌ＋７１を用いた一実施例で
ある。プロービング用パッド＋８）は３Ａ／（γ）を用
いて形成されており、ボンディングパッド（２）に比べ
面積を大きく、あるいは間隔を大きく配列しである。FIG. 1 is a plan view of a semiconductor integrated circuit device which is an embodiment of the present invention. Reference numerals (1) and (2) in the figure are the same as those of the conventional device, so explanations thereof will be omitted. In the figure, (8)
is a probing pad used for a wafer test formed inside the chip using a metal wiring layer further above the conventional chip structure, and false) is a metal wiring connecting pads (2) and (8). 2 and 3 are cross-sectional views of a semiconductor integrated circuit device configured with two-layer wiring around the bonding pad (2) and probing pad (8) shown in FIG. (4) is 3A/(71, and in Figure 3, metal wiring (4) is IAI (5!,
This is an example using 2Al 16) and 3Al+71. The probing pads +8) are formed using 3A/(γ), and have a larger area or are arranged at larger intervals than the bonding pads (2).

次に動作について説明する。Next, the operation will be explained.

ボンディングパッド（２）はチップ内部の半導体集積回
路の入力、出力、ＧＮＤ及び電源に接続されているので
、プロービング用パッド（８）もチップ内部の半導体集
積回路の入力、出力、ＧＮＤ及び電源に接続されている
。Since the bonding pad (2) is connected to the input, output, GND, and power supply of the semiconductor integrated circuit inside the chip, the probing pad (8) is also connected to the input, output, GND, and power supply of the semiconductor integrated circuit inside the chip. has been done.

このプロービング用のパッドを用い、あるいはこのプロ
ービング用パッド（８）とボンディングパッド（２）を
併用すればパッド間隔を大きくできるので、テスタのプ
ローブ（図示せず）を全パッド（２）　＜８１に接触石
せることが可能で、全ボンデイングバッドヘプロービン
グしたのと同等となる。従って、半導体集積回路の全入
力、出力、ＧＮＤ及び電源にプローブを接続することが
できる。By using this probing pad, or by using this probing pad (8) and bonding pad (2) together, the pad spacing can be increased, so the tester probes (not shown) can be set to all pads (2) <81. It is possible to apply a contact stone, and it is equivalent to probing the entire bonding pad. Therefore, probes can be connected to all inputs, outputs, GND, and power sources of the semiconductor integrated circuit.

〔発明の効果〕〔Effect of the invention〕

以上のように本発明によれば、ボンディングパッドの他
にウェハテストを行うためのプロービング用パッドを従
来のチップ構成の更に一層上の金属配線を用いて形成す
るようにしたので、ボンディングパッドの間隔が小さく
、ウェハテストを行う際に全ボンディングパッドにプロ
ービングができずウェハテストが不可能な半導体集積回
路装置において、プロービング用パッドを用い、あるい
は、ボンディングパッドとプロービング用のパッドを併
用すれば全パッドへプロービングが可能で従って半導体
集積回路装置において、全ボンディングパッドへプロー
ビングしたのと同等となりウェハテストが可能となると
いう効果がある。As described above, according to the present invention, in addition to the bonding pads, probing pads for performing wafer testing are formed using metal wiring that is further above the conventional chip configuration, so that the bonding pads are spaced apart from each other. In semiconductor integrated circuit devices where wafer testing is impossible due to the small size of the bonding pads, all bonding pads cannot be probed during wafer testing. Therefore, in a semiconductor integrated circuit device, it is equivalent to probing all the bonding pads, and a wafer test is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例である半導体集積回路装置の
平面図、第２図及び第３図は第１図の半導体集積回路装
置を２層配線を用いて構成したチップの一実施例を示す
断面図、第４図は従来の半導体集積回路装置の平面図、
第５図は第４図の半導体集積回路装置を２層配線を用い
て構成したチップの断面図である。 図において、（１）は基板、（２）はボンディングパッ
ド、（８）はプロービング用パッド、＋４）は金属配線
、（６）はＩＡＩ　、　（６）は２Ａ／、（テ）は３Ａ
／　、　＋８＞及び（９）は層間膜、嶽はガラスコート
を示ｆ。 なお、 図中、 同一符号は同− 又は相当部分を 示す。 代 理 人 大 岩 増 雄 第１図 第４図 第２図 第３図 第５図FIG. 1 is a plan view of a semiconductor integrated circuit device which is an embodiment of the present invention, and FIGS. 2 and 3 are examples of a chip constructed by using the semiconductor integrated circuit device of FIG. 1 using two-layer wiring. FIG. 4 is a plan view of a conventional semiconductor integrated circuit device.
FIG. 5 is a cross-sectional view of a chip constructed using the semiconductor integrated circuit device of FIG. 4 using two-layer wiring. In the figure, (1) is the board, (2) is the bonding pad, (8) is the probing pad, +4) is the metal wiring, (6) is IAI, (6) is 2A/, (Te) is 3A
/ , +8> and (9) are interlayer films, and d is a glass coat f. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo OiwaFigure 1Figure 4Figure 2Figure 3Figure 5

Claims (1)

【特許請求の範囲】[Claims] 　チップ構成の更に一層上の金属配線を用いてウェハテ
ストを行うためのプロービング用のパッドをボンディン
グパッドが配列された領域の内側、つまり、半導体集積
回路が形成された領域の上に形成したことを特徴とする
半導体集積回路装置。Probing pads for wafer testing using the metal wiring layer further above the chip structure are formed inside the area where the bonding pads are arranged, that is, on the area where the semiconductor integrated circuit is formed. Features of semiconductor integrated circuit devices.
JP2265475A 1990-10-02 1990-10-02 Semiconductor integrated circuit device Pending JPH04142053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2265475A JPH04142053A (en) 1990-10-02 1990-10-02 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2265475A JPH04142053A (en) 1990-10-02 1990-10-02 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04142053A true JPH04142053A (en) 1992-05-15

Family

ID=17417691

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2265475A Pending JPH04142053A (en) 1990-10-02 1990-10-02 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04142053A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990018725A (en) * 1997-08-28 1999-03-15 윤종용 Semiconductor wafer and its electrical property inspection method
WO2004047171A1 (en) * 2002-11-20 2004-06-03 Intel Corporation Forming a cap above a metal layer

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990018725A (en) * 1997-08-28 1999-03-15 윤종용 Semiconductor wafer and its electrical property inspection method
WO2004047171A1 (en) * 2002-11-20 2004-06-03 Intel Corporation Forming a cap above a metal layer
US7056817B2 (en) 2002-11-20 2006-06-06 Intel Corporation Forming a cap above a metal layer

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