JPH04140873A - Microprocessor system - Google Patents

Abstract

PURPOSE:To shorten a read/access time by providing an arbitration circuit which arbitrates the operations of both a surrounding circuit and a microprocessor, and switching circuit which connects and disconnects buses, and plural memories connected with the buses with the above mentioned switching circuit in between. CONSTITUTION:When the write/access of a microprocessor 1 and the write/ access of a surrounding circuit 2 are simultaneously generated, an arbitration circuit 4 turns the access of the processor 1 into a waiting state through an access controlling signal S2. At the same time, a switching circuit 6 is closed by a bus connection and disconnection controlling signal S3, and the access of the surrounding circuit 2 is executed by an access controlling signal S1. A bus 7 at that time is turned into one bus state connecting the processor 1 with a main memory 3, a submemory 5, and the circuit 2 by the switching circuit 6. After that, the circuit 4 closes the circuit 6 by the signal S3, and executes the access of the processor 1 through the signal S2. The bus 7 at that time is turned into one bus state connecting the processor 1 with the memory 3, memory 5, and circuit by the circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor system, and more particularly to a microprocessor system that controls access contention.

[Conventional technology]

Conventionally, in microprocessor systems that have a microprocessor and peripheral circuits that directly access memory, when the microprocessor access and the peripheral circuit access occur at the same time, the system configuration makes it impossible to execute both accesses at the same time. Since this is not possible, one of the accesses is made to wait and the other access is executed.

Thereafter, when the execution of the access is completed, the access that was kept on standby is executed.

FIG. 7 shows an example of such a conventional microprocessor.
As shown in FIG. 7, which is a block diagram of the system, a conventional microprocessor system includes one microprocessor 1 connected to a bus 7.
and peripheral circuits 2 and 2 /< Memory 3A connected to the memory block and accessed from microprocessor 1 and peripheral circuit 2, and access control signals S1 and S for access from microprocessor 1 and peripheral circuit 2, respectively.
2, and an arbitration circuit 4A that performs control based on 2.

There are four types of operations when the microprocessor 1 and the peripheral circuit 2 access the memory 3 at the same time, and these operations will be explained below.

8 to 11 are operational state diagrams for explaining an example of the operation of the system shown in FIG. 7, respectively.

As shown in FIG. 8, this operating state is a case where a write access of the microprocessor 1 and a read access of the peripheral circuit 2 occur simultaneously.

In this case, the arbitration circuit 4A first receives the access control signal S2.
It sends out an access control signal S1 to make the microprocessor 1 wait for a write access, while sending out an access control signal S1 to make the peripheral circuit 2 execute a read access. Thereafter, when the memory access of the peripheral circuit 2 is completed, the arbitration circuit 4A executes the access of the microprocessor-1 using the access control signal S1. Note that at this time, the peripheral circuit 2 is in a standby state.

Next, as shown in FIG. 9, this operating state is a case where a write access by the microprocessor 1 and a write access by the peripheral circuit 2 occur simultaneously. In this case, the arbitration circuit 4A first puts the access of the microprocessor 1 in a standby state via the access control signal S2, and causes the access of the peripheral circuit 2 to be executed via the access control signal S1. Thereafter, the arbitration circuit 4 executes the access of the microprocessor 1 through the control signal S2.

Next, as shown in FIG. 10, this operating state is a case where a read access of the microprocessor 1 and a write access of the peripheral circuit 2 occur simultaneously. In this case, first, the arbitration circuit 4A puts the access of the microprocessor-1 into a standby state through the access control signal S2, while
The access of the peripheral circuit 2 is executed through the access control signal Sl. Thereafter, the arbitration circuit 4A executes the access of the microprocessor-1 through the access control signal S2.

Furthermore, as shown in FIG. 11, this operating state is an S case in which read access to the microprocessor 1 and read access to the peripheral circuit 2 occur simultaneously. In this case, the arbitration circuit 4A first puts the access of the microprocessor 1 into a standby state through the access control signal S2, and causes the access of the peripheral circuit 2 to be executed through the access control signal S1. Thereafter, the arbitration circuit 4A executes the access of the microprocessor-1 through the access control signal S2.

In short, in the conventional microprocessor system, when accesses to the memory 3 by the microprocessor 1 and the peripheral circuit 2 occur simultaneously, the access by the microprocessor 1 must wait until the access by the peripheral circuit 2 is completed. Therefore, the execution speed of the microprocessor 1 decreases.

[Problem to be solved by the invention]

In the above-described conventional microprocessor system having a peripheral circuit, when accesses of the microprocessor and the peripheral circuit occur simultaneously, one access is made to wait until the other access is completed. Therefore, there is a drawback that the overall read access time becomes longer and the performance of the side that is placed on standby deteriorates.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor system that does not increase read access time or degrade performance even when read accesses from the microprocessor and peripheral circuits occur simultaneously.

[Means to solve the problem]

The microprocessor system of the present invention includes microprocessor systems connected to first and second buses, respectively.
and a peripheral circuit, a main memory and a sub memory respectively connected to the first and second buses and arranged in the same address space, and a switching circuit for separately connecting the first and second buses; a microprocessor and an arbitration circuit that receives an access request from the peripheral circuit and controls access, and when the access request is for writing to the main memory or the sub memory, the switching circuit The first and second buses are connected to each other, and the first and second buses are separated when reading from the main memory or the sub memory.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a microprocessor illustrating an embodiment of the present invention.
FIG. 2 is a block diagram of the system.

As shown in FIG. 1, this embodiment has a bus 7 divided into two, a microprocessor 1 and a peripheral circuit 2 connected to each bus 7, and a main memory connected to each bus 7. 3 and secondary memory 5; and an arbitration circuit 4 which separates the bus 7 and controls access between the microprocessor 1 and the peripheral circuit 2 upon receiving an access request from the microprocessor 1 and the peripheral circuit 2; It has a switching circuit 6 for separating and connecting 7.

Signal Sl is a signal that controls access to peripheral circuit 2, signal S2 is a signal that controls access to microprocessor 1, and signal S3 is a signal that controls separate connection of bus 7. Moreover, the sub memory 5 is arranged in the same address space as the main memory 3 and always has the same data as the main memory 3. Furthermore, when the bus 7 is connected by the switching circuit 6, it becomes one bus connecting the microprocessor 1, the main memory 3, the sub memory 5, and the peripheral circuit 2.
Conversely, when the bus 7 is separated by the switching circuit 6, it is separated into two buses: one connecting the microprocessor 1 and the main memory 3, and the other bus connecting the peripheral circuit 2 and the sub memory 5.

In this embodiment, write access by the microprocessor 1 and the peripheral circuit 2 is performed simultaneously on the main memory 3 and the sub memory 5. Also, Microflosser-1
Read access is performed only to main memory 3,
Read access by the peripheral circuit 2 is performed only to the sub memory 5.

There are four types of operations when the microprocessor 1 and the peripheral circuit 2 access the main memory 3 at the same time, and these operations will be explained below.

2 to 5 are operational state diagrams for explaining an example of the operation of the system shown in FIG. 1, respectively.

As shown in FIG. 2, this operating state is a case where a write access by the microprocessor 1 and a read access by the peripheral circuit 2 occur simultaneously.

In this case, first, the arbitration circuit 4 sends the access control signal S2 to put the microprocessor 1 in a standby state, opens the switching circuit 6 using the bus separation connection control signal S3, and sends the access control signal S1 to the peripheral circuit 1. access. That is, the bus 7 is separated by the switching circuit 6 into a bus connecting the peripheral circuit 2 and the sub memory 5 and a bus connecting the microprocessor 1 and the main memory 3. Thereafter, the arbitration circuit 4 closes the switching circuit 6 using the bus separation/connection control signal S3, and accesses the microprocessor 1 via the access control signal S2.

At this time, the bus 7 is in the state of one bus connecting the microprocessor 1, the main memory 3, the sub memory 5, and the arbitration circuit 2 by the switching circuit 6.

Next, as shown in FIG. 3, this operating state is a case where a write access by the microprocessor 1 and a write access by the peripheral circuit 2 occur simultaneously. In this case, the arbitration circuit 4 first puts the access of the microprocessor-1 into a standby state via the access control signal S2, and
The switching circuit 6 is closed by the bus separation connection control signal S3, and the peripheral circuit 2 is accessed by the access control signal S1. At this time, the bus 7 is connected to the microprocessor 1, the main memory 3, the sub memory 5, and the peripheral circuit 2 by the switching circuit 6.
There is now a single bus connecting the two. Thereafter, the arbitration circuit 4 switches the switching circuit 6 to the bus separation connection control signal S3.
is closed, and the microprocessor 1 is accessed through the access control signal S2. At this time, the bus 7 is in the state of one bus connecting the microprocessor 1, main memory 3, sub memory 5, and peripheral circuit 2 by the switching circuit 6.

Next, as shown in FIG. 4, this operating state is a case where a read access by the microprocessor 1 and a write access by the peripheral circuit 2 occur simultaneously. In this case, the arbitration circuit 4 first puts the access of the microprocessor 1 in a standby state through the access control signal S2, closes the switching circuit 6 with the bus separation connection control signal S3, and stops the access of the peripheral circuit 2 with the access control signal Sl. Let it run. At this time, the bus 7 is in the state of one bus connecting the microprocessor 1, the main memory 3, the sub memory 5, and the peripheral circuit 2 by the switching circuit 6. After that,
The arbitration circuit 4 opens the switching circuit 6 and the microprocessor
1 access is executed. At this time, the bus 7 is separated by the switching circuit 6.

Finally, 1. As shown in Figure 5, this operating state is
This is a case where read access to microprocessor 1 and read access to peripheral circuit 2 occur simultaneously. In this case, the arbitration circuit 4 opens the switching circuit 6 and uses the access control signals Sl and S2 to set -r, o-j, and
It is now possible to execute the accesses of the peripheral circuit 2 and the peripheral circuit 2 simultaneously. At this time, the bus 7 is separated by the switching circuit 6. Therefore, the number of accesses is one.

As described above, in the microprocessor system of this embodiment, when read access to the microprocessor 1 and the peripheral circuit 2 occurs simultaneously, the access can be made without making either of them wait.

FIG. 6 is a specific configuration diagram of the arbitration circuit shown in FIG. 1.

As shown in FIG. 6, this arbitration circuit is an AND circuit (AN
D gate) A1 to A6 and AND output inverting circuit (NAN
D gate) Nl-N3 and logic inversion circuit (inverter)
Il, I2, and OR circuit (0'R gate) 01 to o3
and D-type 7 jJ block flop circuits FFI to FF3.

This arbitration circuit consists of a PREQ signal that becomes active (active GH) when the peripheral circuit 2 makes an access request of 1-, a PRE A D signal that becomes active when the peripheral circuit 2 makes a read access request, and the peripheral circuit. PWRI that becomes active when 2 makes a write access request.
An access control signal S1 that includes a TE signal and a PAK signal that becomes active when the arbitration circuit 4 permits access from the peripheral circuit 2; and an MREQ that becomes active when the microprocessor 1 makes an access request. The MRITE signal, which becomes active when microprocessor 1 requests read access, and the MREAD signal, which becomes active when microprocessor 1 requests write access, and the arbitration circuit 4 permit access to microprocessor 1. If MA becomes active
The access control signal S2 containing the K signal and the bus separation connection control signal s3 containing the CLO8E signal, which becomes active when either the microprocessor 1 or the peripheral circuit 2 executes a write access, are input/output. .

First, the levels of the PREQ signal and PREAD signal are high.
When IGH, that is, when peripheral circuit 2 requests read access, AND gate AI outputs EII.
Make it GH. In addition, in the NAND gate N1, the levels of the PREQ signal and the PWRITE signal are HIGH and the M
When the level of the AR signal is LOW, that is, when the peripheral circuit 2 requests write access and the microprocessor 1 is not accessing, the output signal is set to LOW. Also, A
(ND game) A2 sets the output to HIGH when the MREQ signal and MWRITE signal levels are HIGH, that is, when microprocessor 1 requests write access.
Make it GH. NAND game) N3 is the MAK signal and A
ND game) When the output level of A2 is 1: (IGFH,
In other words, microphone o 7'.

When processor l is executing write access, the output level is set to LOW. AND game) A4 sets the output level to HIGH when the outputs of AND gate A1 and NAND gate N3 are HIGH, that is, when the peripheral circuit 2 requests a read access and the microprocessor 1 is not executing a write access. Make it. Also, OR gate A4 or inverter E2 output level is HIGH, that is, when peripheral circuit 2 requests read access and microprocessor 1 is not executing write access, or Peripheral circuit 2 requests write access and microprocessor-1
When access is not in progress, the output level is set to HIGH. The output of this OR game 1-01 is input to the D-type flip-flop FFI, and the signal cut by the CLOCK signal becomes the PAK signal.

Then, AND gate A3 connects the MREQ signal and MREA
When the level of the D signal is HIGH, that is, the microprocessor-1 requests read access, the output level is set to HIGH.
N2 is set when the PREQ signal and inverter 1 level is H.
At IGH, that is, when the peripheral circuit 2 requests access and the microprocessor 1 is not executing the access, the pressure level is set to LOW. AND game) A5 is N
When the output level of AND gate N1 and AND gate A3 is HIGH, that is, either the peripheral circuit 2 does not request a write access or the microprocessor 1 is executing an access, and the microprocessor 1 requests read access, sets the output level to HIGH. Furthermore, when the output level of the AND gate A2 and the NAND gate N2 is HIGH, the ANDy gate A6 indicates whether the peripheral circuit 2 is not issuing an access request or the microprocessor 1 is executing an access. In either case, and if the microprocessor-1 is requesting a write access, the output level is set to HIGH. Furthermore, OR gate 03 is A
(ND game) When the output level of A5 or A6 is HIGH, that is, microprocessor-1 is executing an access and requests access, or peripheral circuit 2 does not issue an access request and the microprocessor-1 When the processor 1 is requesting a write access, or when the peripheral circuit 2 does not request a right access and the microprocessor 1 is requesting a read access, the output level is set to HIGH. Make it. 1[J of this OR gate 03 is input to the D-flip-flop FF3, and the one cut by the clock signal is MAK
It becomes a signal.

Furthermore, the OR gate 02 outputs the PWRITE signal or the MW
When the level of the RITE signal is HIGH, and t') If either the microprocessor 1 or the peripheral circuit 2 performs a write access, the output level is set to HIGH. The output of this OR gate 02 is input to FF2, and the output cut by the clock signal becomes the CLO8E signal.

In short, the arbitration circuit 4 performs PREQ, PREAD.

Access control signal S1 composed of PAK signal
is exchanged with peripheral circuit 2, and MREQ, MR
By transmitting and receiving an access control signal S2 composed of EAD and MAK signals to and from the microprocessor 1, the peripheral circuit 2 requests a read access, and the microprocessor 1 executes the write access. If the peripheral circuit 2 is not in use, or if the peripheral circuit 2 requests a write access and the microprocessor 1 is not executing the access, the peripheral circuit 2 is permitted to access. Furthermore,
When the microprocessor 1 is executing an access and the microprocessor l is requesting an access, or when there is no access request from the peripheral circuit 2 and the microprocessor 1 is requesting a write access,
Alternatively, when there is no write access request from the peripheral circuit 2 and the microprocessor-1 is requesting a read access, the microprocessor-1 is executing the access. Furthermore, when either the microprocessor 1 or the peripheral circuit 2 performs write access, the switching circuit 6 can be closed.

〔Effect of the invention〕

As explained above, the microprocessor of the present invention
The system has an arbitration circuit that arbitrates the operations of peripheral circuits and a microprocessor, a switching circuit that separates and connects the bus, and a plurality of memories that are connected to the bus across the switching circuit. Since read accesses from the microprocessor and peripheral circuits can be performed separately and simultaneously, the overall read access time can be shortened and the overall performance can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprocessor system showing an embodiment of the present invention, FIGS. 2 to 5 are operation state diagrams each explaining an example of the operation of the system shown in FIG. 1, and FIG. 7 is a block diagram of a microprocessor system showing a conventional example, and FIGS. 8 to 11 are for explaining an example of the operation of the system shown in FIG. 7. FIG. 1...Microprocessor 2...
Peripheral circuit, 3... Main memory, 4... Arbitration circuit, 5... Sub memory, 6... Switching circuit, 7... Bus, SL, S2...access control signal, s3...bus separation connection control signal, A
l~A6......Logic product circuit (AND), N1~N3
......Logic product pressure inversion circuit (NAND), II,
I2...Logic inversion circuit (inverter), 01~0
3...Logical clever path (OR), FFl-FF3・
...D-flip-flop circuit. Agent Patent Attorney Shinmi Uchihara? zuzuseizumuizuzuryokuzumizumizu

Claims (1)

[Claims] a microprocessor and peripheral circuits connected to the first and second buses, respectively; a main memory and a secondary memory connected to the first and second buses, respectively, and located in the same address space; a switching circuit that separates and connects a second bus; and an arbitration circuit that receives access requests from the microprocessor and the peripheral circuits and controls access; In this case, the first and second buses are brought into a connected state by the switching circuit, and when reading from the main memory or the sub memory, the first and second buses are brought into a separated state. microprocessor system.