JPH04140866A - Detachment system for input/output device - Google Patents

Abstract

PURPOSE:To remarkably improve the operation efficiency by detaching the connection of an input/output device and a central processor, and also, reporting the generation of unauthorized interruption, when a detection by a counter is generated, and also, a detection by a timer is generated. CONSTITUTION:When a unauthorized interruption is generated from an IOE 2, the number of times thereof is counted, and a unauthorized interruption counter WIC 21 for detecting a fact that its number of times becomes a prescribed number of times, and an elapsed time after the unauthorized interruption is generated first are monitored. When this time becomes a prescribed time, a unauthorized state continuation timer WRT 22 for detecting it is provided. In accordance with generation of the unauthorized interruption, the WRT 22 monitors the elapsed time therefrom, and when this time reaches a prescribed time, its detection output is sent out, and on the other hand, in accordance with generation of the unauthorized interruption, the WIC 21 executes metering. When the detection output is overlapped, an IOC 3 executes detachment of the IOE 2, and its report to a CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to a data processing device consisting of a central processing unit and a plurality of input/output devices, in which unauthorized interrupts are repeatedly received from any of the input/output devices. [Prior art] In general, in such a data processing device, each input/output device (hereinafter referred to as 10E) is separated from each other, and each 10E and the central processing A five-person output control device (hereinafter referred to as 10C) is interposed between the equipment (hereinafter referred to as CPtJ).

Through this, each IOE issues an interrupt request to the CPU, and after the CPU responds to this, data is exchanged between the two.
If an illegal interrupt occurs, the CPU software determines this, counts the number of times this occurs, and when this count reaches a predetermined number of times, excludes the IOE from being subject to data exchange. It is intended to be used for separation.

[Problem to be solved by the invention]

However, in the case of CPU software, the said 1
Until a decision is made to disconnect 0E, invalid interrupts continue to occur and the CPU is occupied processing them, which limits the time to run the original application software and reduces overall operating efficiency. is occurring.

[Means to solve the problem]

The present invention is constructed by the following means.

That is, in the data processing device described above, there is a timer that detects when a certain period of time has elapsed since the occurrence of an unauthorized interrupt from an input/output device, and a counter that detects when the number of unauthorized interrupts from the input/output device reaches a predetermined number. and an input/output control device that disconnects the input/output device from the central processing unit when detection by the counter occurs and detection by the timer occurs, and notifies the central processing unit of the occurrence of an unauthorized interrupt. It is something.

[Function] Therefore, the IOC uses its own counter and timer to monitor the number of occurrences of unauthorized interrupts and the elapsed time since the first occurrence, and depending on the number of occurrences and the elapsed time, disconnects the IOE and This will be reported to the CPU.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 1 is a block diagram of the entire configuration, in which a CPU 1 and a plurality of l0E2 are provided, and an l0C3 is provided for each of these and interposed between each l0E2 and the CPUI. When the 10E2 becomes necessary, it requests an interrupt to the CPU1 via the l0C3, and if the CPU1 responds to this, the l0E2 and the CPU
Data is exchanged with 1.

FIG. 2 is a block diagram showing the contents of l0C3. When an illegal interrupt occurs from the corresponding l0E2, it counts the number of times this occurs and detects when this number reaches a predetermined number. , WIC) 2L and an illegal state duration timer (hereinafter referred to as WRT) 22 that monitors the elapsed time since the first occurrence of an illegal interrupt and detects this when this time reaches a certain period of time. Yes, WRT 22 depending on the occurrence of illegal interrupt
monitors the elapsed time, and when this time reaches a certain time, it sends out a detection output, while the WIC 21 performs registration in response to the occurrence of an illegal interrupt, and when this count value reaches a predetermined number of times. , and send out the detection outputs of this, and when these detection outputs overlap, l0C3 disconnects l0E2 and sends its CPU.
1 is to be notified.

FIG. 3 is a flowchart showing the status of interrupt processing by the l0C3, which is executed by a microprocessor or the like in the l0C3.

First, in response to the occurrence of an interrupt from rIOE
Check the state of lOE" 102 to determine whether it is an illegal interrupt? J103, and if it is Y (YES) [Is this the first interrupt? Check J11.1 as well, and issue an interrupt to rCPU according to this Y" 112, reset rWRT, and restart.''113
starts the timing operation of WRT22, and then rwr
"Add 1 to c" 114 to register the WIC21.

Then, did rWRT exceed a certain time? ”121 to W
Judging by the check of RT22, this is N (No)
During this time, steps 101 and subsequent steps are repeated, whereas if step 121 is Y, the WRT 22 has performed the detection, and the WIC 21 checks whether rWIC has exceeded the predetermined number of times. ”122, and depending on the N of this, rw
"Reset IC" 123 and repeat steps 101 and subsequent steps.

On the other hand, if step 122 is Y, WIC21
detects that the rIOE2 has detected an abnormal interrupt a predetermined number of times within a certain period of time, determines that its own l0E2 has become abnormal, and disconnects the rIOE.
"Issuing an interrupt to notify rCPU of IOE disconnection" I32 is performed.

On the other hand, if step 103 is N, after performing "reset rWIc" 141, "normal interrupt processing" 1
42.

Therefore, when the WIC 21 and the WRT 22 each detect a minor overload for a predetermined number of times and for a certain period of time, the fOE2 is disconnected and the CPU 1 is notified from the l0C3, and the CPU 1 is required to process the unauthorized interrupt. Therefore, the operating load of the CPU 1 is reduced, and only the original application software needs to be executed, thereby greatly improving the operating efficiency of the CPU 1.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, there is provided a timer that detects that a certain period of time has passed since the occurrence of an unauthorized interrupt from an input/output device, and a timer that detects when the number of unauthorized interrupts from the input/output device reaches a predetermined number. The input/output control device is equipped with a counter that detects an interrupt, and when a detection by this counter occurs and a detection by a timer occurs, the connection between the input/output device and the central processing unit is disconnected, and the occurrence of an unauthorized interrupt is sent to the central processing unit. By making the notification from the input/output control device, the central processing unit does not need to process unauthorized interrupts, and the operating efficiency of the central processing unit is greatly improved, so that a remarkable effect can be obtained in various data processing devices.

[Brief explanation of drawings]

The figures show an embodiment of the present invention, with Fig. 1 being a block diagram of the entire configuration, Fig. 2 being a block diagram showing the contents of the input/output control device, and Fig. 3 being a block diagram showing the contents of the input/output control device.
The figure is a flowchart showing the status of interrupt processing. 1... central processing unit, 2... input/output device, 3...
... Input/output control device, 21 ... Illegal interrupt counter, 22 ... Illegal state continuation timer

Claims (1)

[Claims] In a data processing device comprising a central processing unit, a plurality of input/output devices, and an input/output control device interposed for each of these input/output devices and between each input/output device and the central processing unit, the input/output The apparatus includes a timer that detects when a certain period of time has elapsed since the occurrence of an unauthorized interrupt from the device, and a counter that detects when the number of unauthorized interrupts from the input/output device reaches a predetermined number. and an input/output control device that disconnects the input/output device from the central processing unit when detected by the timer and notifies the central processing unit of the occurrence of an unauthorized interrupt. Device disconnection method.