CN109298961A - Fault handling method, device and the network equipment of multi-core processor - Google Patents
Fault handling method, device and the network equipment of multi-core processor Download PDFInfo
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- CN109298961A CN109298961A CN201810986628.1A CN201810986628A CN109298961A CN 109298961 A CN109298961 A CN 109298961A CN 201810986628 A CN201810986628 A CN 201810986628A CN 109298961 A CN109298961 A CN 109298961A
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- chip microcontroller
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
Abstract
The invention discloses a kind of fault handling method of multi-core processor and devices, it is related to field of computer technology, the operating status that this method passes through each core in real time monitoring multi-core processor, interruption can be triggered when core is abnormal, and the status information of fault keranel is collected by interrupt processing function and start correcting strategy.The present invention positions the fault keranel in multi-core processor in which can help developer's fast accurate, and developer is helped to carry out fault restoration.Meanwhile the present invention can also monitoring period to core each in multi-core processor and correcting strategy carry out flexible configuration, there is better recovery mechanism.
Description
Technical field
The present invention relates to field of computer technology more particularly to a kind of fault handling method of multi-core processor, device and
The network equipment.
Background technique
With the continuous promotion of single core processor performance, excessive heat can be generated, is restricted so as to cause its performance.And
In order to promote the overall performance of processor, multi-core processor also just comes into being.Multi-core processor refers in one piece of processor
Integrate two or more cores.Multi-core processor can be executed more by dividing task between multiple cores within the specific time
Task, so as to improve the processing capacity of entire processor.Therefore, multi-core processor is more and more applied to place
It manages in the more demanding network communication equipment of device processing capacity.In order to guarantee the normal operation of client traffic, to multi-core processor
It is effectively monitored and is repaired and just seemed very necessary.
The monitoring and restorative procedure that the network communication equipment of usual multi-core processor uses are as follows: when monitoring multi-core processor
When breaking down, repaired by the way of resetting entire multi-core processor.This method have the disadvantage in that can not monitor it is more
The operating status of each core in core processor can not fast accurate ground positioning failure core when some core is operating abnormally；In addition,
When some core breaks down, directly restarts entire multi-core processor also and will affect the normal implementation of business.
Summary of the invention
The present invention provides the fault handling method, device and the network equipment of a kind of multi-core processor, solves multicore processing
Device can not monitor the operating status of each core, when some core breaks down, because can not precise positioning fault keranel, lead to not needle
The problem of fault keranel is repaired.
To achieve the goals above, the first aspect of the present invention provides a kind of fault handling method of multi-core processor, packet
Include following steps:
Multi-core processor registers interrupt processing function, and the interrupt processing function can on each core of multi-core processor
With processing；Each core sends monitoring request to single-chip microcontroller respectively in multi-core processor, after single-chip microcontroller receives monitoring request, starting pair
The monitoring of the core；Each core reports keep-alive message to single-chip microcontroller according to the preset monitoring period respectively；When single-chip microcontroller time-out
Triggering is interrupted when not receiving the keep-alive message of some core, collects the status information of some core simultaneously by the interrupt processing function
Start correcting strategy.
Wherein, the monitoring request includes: core ID and the preset monitoring period.The keep-alive message includes: core ID.
The multi-core processor center can carry out the double of information by I2C bus, UART bus or spi bus and the single-chip microcontroller
To interaction.
The status information includes: core ID；The starting correcting strategy, comprising: the core of some core according to collection
Some described core is restarted or disabled to ID.
Further, the status information includes: core ID and register information；The starting correcting strategy includes: basis
The core ID and register information for some core collected, position the failure cause of some core, and restart or described in disabling
Some core.
Further, the method also includes triggerings when the keep-alive message for not receiving some core when single-chip microcontroller time-out
It interrupts, if the interrupt processing function, without response, the single-chip microcontroller resets the multi-core processor according to reset timing.
The second aspect of the present invention provides a kind of fault treating apparatus of multi-core processor, specifically includes:
Registration module registers interrupt processing function, the interrupt processing letter to interruption processing module for multi-core processor
Number can be handled on each core of multi-core processor；
Reporting module sends monitoring request to single-chip microcontroller respectively for each core in multi-core processor；And for described
Each core reports keep-alive message to single-chip microcontroller according to the preset monitoring period respectively；
Monitoring module receives the monitoring request that each core is sent for single-chip microcontroller, starts the monitoring to the core；For
Single-chip microcontroller receives each core according to the keep-alive message of preset monitoring periodic report, when time-out does not receive the keep-alive of some core
It triggers and interrupts when message；
Interruption processing module, for collecting some described core by the interrupt processing function when single-chip microcontroller is triggered and interrupted
Status information and start correcting strategy.
The third aspect of the present invention provides a kind of network equipment, specifically includes:
Multi-core processor, for registering interrupt processing function, the interrupt processing function is in the every of the multi-core processor
The status information of some core can be collected on a core and starts correcting strategy；Each core is also used to send out to single-chip microcontroller respectively
It send monitoring to request, and reports keep-alive message to the single-chip microcontroller according to the preset monitoring period；
The monitoring of each core is requested and started to single-chip microcontroller for receiving the monitoring, when time-out does not receive the guarantor of some core
Triggering is interrupted when message living, is collected the status information of some core by the interrupt processing function and is started correcting strategy.
Wherein, the status information includes: core ID；The starting correcting strategy, comprising: some core according to collection
Core ID, restart or disable some described core.
Further, the status information includes: core ID and register information；The starting correcting strategy, comprising: according to
The core ID and register information for some core collected, position the failure cause of some core, and restart or described in disabling
Some core.
Further, the single-chip microcontroller is also used to, and when time-out does not receive the keep-alive message of some core, triggering is interrupted, if institute
Interrupt processing function is stated without response, resets the multi-core processor according to reset timing.
The monitoring request includes: core ID and the preset monitoring period；The keep-alive message includes: core ID.Wherein,
The multi-core processor center can carry out the double of information by I2C bus, UART bus or spi bus and the single-chip microcontroller
To interaction.
In conclusion multi-core processor failure monitoring method, device and the network equipment of the invention, more by monitoring in real time
The operating status of each core in core processor positions in which can help developer's fast accurate when some core is abnormal
Fault keranel, the present invention can also carry out flexible configuration to core each in multi-core processor preset monitoring period and correcting strategy,
With better recovery mechanism.
Detailed description of the invention
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only certain embodiments of the present invention, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain other relevant attached drawings.
Fig. 1 shows a kind of structural schematic diagram of network equipment provided in an embodiment of the present invention；
Fig. 2 shows the structural schematic diagrams of another network equipment provided in an embodiment of the present invention；
Fig. 3 shows the structural schematic diagram of another network equipment provided in an embodiment of the present invention；
Fig. 4 shows a kind of flow chart of multi-core processor fault handling method provided in an embodiment of the present invention；
Fig. 5 shows a kind of structural schematic diagram of multi-core processor fault treating apparatus provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with attached drawing in the embodiment of the present invention, technical solution in the embodiment of the present invention carries out clear, complete
Ground description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is right below
The detailed description of the embodiment of the present invention provided in the accompanying drawings is not intended to limit the range of claimed invention, but
It is merely representative of selected embodiment of the invention.Based on the embodiment of the present invention, those skilled in the art are not making creativeness
Every other embodiment obtained, shall fall within the protection scope of the present invention under the premise of labour.
Below by specific embodiment, it is described in detail respectively.
Embodiment one
The embodiment of the invention provides a kind of network equipment 100, structural schematic diagram is as shown in Figure 1, the network equipment 100 wraps
It includes: a multi-core processor 101 and a single-chip microcontroller 102.Multi-core processor 101 includes Core1、Core2……CoreNDeng total N
A core, wherein N is the positive integer more than or equal to 2.
Multi-core processor 101, for registering interrupt processing function, the interrupt processing function is in the multi-core processor
The status information of some core can be collected on 101 each core and starts correcting strategy；Be also used to each core respectively to
Single-chip microcontroller 102 sends monitoring request, and reports keep-alive message to single-chip microcontroller 102 according to the preset monitoring period；
Wherein, the status information includes: core ID；The starting correcting strategy includes: some core according to collection
Core ID, restart or disable some described core.
Further, the status information includes: core ID and register information；The starting correcting strategy includes: basis
The core ID and register information for some core collected, position the failure cause of some core, and restart or described in disabling
Some core.
The monitoring request includes: core ID and the preset monitoring period；The keep-alive message includes: core ID.
The monitoring of each core is requested and started to single-chip microcontroller 102 for receiving the monitoring, when time-out does not receive some core
It triggers and interrupts when keep-alive message.
The single-chip microcontroller 102 is also used to, and when time-out does not receive the keep-alive message of some core, triggering is interrupted, if the interruption
Function is handled without response, resets the multi-core processor 101 according to reset timing.
Further, the single-chip microcontroller 102 is also used to, and when time-out does not receive the keep-alive message of some core, triggering is interrupted,
If the interrupt processing function resets the multi-core processor 101 without response, according to reset timing.
Embodiment two
The embodiment of the invention provides a kind of network equipment 200, structural schematic diagram is as shown in Fig. 2, the network equipment 200 wraps
It includes: a multi-core processor 201 and a single-chip microcontroller 202.Multi-core processor 201 includes Core1、Core2……CoreNDeng total N
A core, wherein N is the positive integer more than or equal to 2.Wherein, single-chip microcontroller 202 is connected to multi-core processor 201 by GPIO pin,
And it can trigger GPIO and interrupt；Single-chip microcontroller 202 can reset multi-core processor 201 according to reset timing by RESET pin；Monolithic
The two-way interactive of information can be carried out between machine 202 and multi-core processor 201 by I2C bus, UART bus or spi bus.
After the starting operation of multi-core processor 201, multi-core processor 201 registers GPIO interrupt processing function, at the interruption
Reason function can collect the status information of some core on each core of the multi-core processor 201 and start correcting strategy；
Each core in multi-core processor 201 pass through respectively I2C bus to single-chip microcontroller 202 send monitoring request, and by I2C bus with
The preset monitoring period reports keep-alive message to single-chip microcontroller 202.
Wherein, the status information includes: core ID；The starting correcting strategy includes: some core according to collection
Core ID, restart or disable some described core.
Further, the status information includes: core ID and register information；The starting correcting strategy includes: basis
The core ID and register information for some core collected, position the failure cause of some core, and restart or described in disabling
Some core.
The monitoring request includes: core ID and the preset monitoring period；The keep-alive message includes: core ID.
Single-chip microcontroller 202 is used to receive the monitoring that monitoring requests and starts each core, when time-out does not receive the keep-alive of some core
It triggers and interrupts when message, the status information of some core is collected by the interrupt processing function and start correcting strategy.
Further, the single-chip microcontroller 102 is also used to, and when time-out does not receive the keep-alive message of some core, triggering is interrupted,
If interrupt processing function resets multi-core processor 201 according to reset timing by RESET pin without response, single-chip microcontroller 202.
The network equipment of the embodiment of the present invention monitors the operation shape of each core in multi-core processor in real time by single-chip microcontroller
State, when some core is abnormal, with can helping developer's fast accurate positioning failure core, the embodiment of the present invention can be with
Flexible configuration is carried out to core each in multi-core processor preset monitoring period and correcting strategy, there is better fault recovery machine
System.
Embodiment three
The network equipment of the embodiment of the present invention may include multiple multi-core processors.The present embodiment is with two multi-core processors
For provide the network equipment 300, structural schematic diagram is as shown in Figure 3.The network equipment 300 includes: two multi-core processors
301,302 and a single-chip microcontroller 303.Multi-core processor 301 includes Core11、Core12……Core1NDeng N number of core altogether.At multicore
Managing device 302 includes Core21、Core22……Core2MDeng total M core, N and M are the positive integer more than or equal to 2.In the present invention
In embodiment, single-chip microcontroller 303 is connected to multi-core processor 301,302 by GPIO pin respectively, and can trigger GPIO and interrupt；It is single
Piece machine 303 can reset multi-core processor 301,302 according to reset timing by RESET pin respectively；Single-chip microcontroller 303 and multicore
The two-way interactive of information can be carried out between processor 301,302 by I2C bus, UART bus or spi bus.Network is set
Standby 300 specific implementation is identical as embodiment two, and details are not described herein.
Example IV
The embodiment of the invention provides a kind of multi-core processor fault handling method, flow chart is as shown in figure 4, can answer
In the network equipment in embodiment one, embodiment two, embodiment three, include the following steps:
S401, multi-core processor register interrupt processing function, each core of the interrupt processing function in multi-core processor
On can handle.
S402, each core sends monitoring request to single-chip microcontroller respectively in multi-core processor, after single-chip microcontroller receives monitoring request,
Start the monitoring to the core.
Wherein, the monitoring request includes: core ID and preset monitoring period.
S403, each core report keep-alive message to single-chip microcontroller according to the preset monitoring period respectively.
Wherein, the preset monitoring period is the preset monitoring period in monitoring request；The keep-alive message
It includes: core ID.
S404 is triggered when single-chip microcontroller time-out does not receive the keep-alive message of some core and is interrupted, by the interrupt processing function
It collects the status information of some core and starts correcting strategy.
Wherein, the status information includes: core ID；The starting correcting strategy includes: some core according to collection
Core ID, restart or disable some described core；
Further, the status information includes: core ID and register information；The starting correcting strategy includes: basis
The core ID and register information for some core collected, position the failure cause of some core, and restart or described in disabling
Some core.
In step S404, interruption can be triggered when single-chip microcontroller time-out does not receive the keep-alive message of some core, if interrupt processing
Function resets the multi-core processor according to reset timing without response, the single-chip microcontroller.
The multi-core processor fault handling method of the embodiment of the present invention is monitored in real time every in multi-core processor by single-chip microcontroller
The operating status of a core, when some core is abnormal, positioning failure core, of the invention with capable of helping developer's fast accurate
Embodiment can also carry out flexible configuration to core each in multi-core processor preset monitoring period and correcting strategy, have more preferable
Recovery mechanism.
Embodiment five
The embodiment of the invention provides a kind of multi-core processor fault treating apparatus 500, structural schematic diagram such as Fig. 5 institutes
Show, can apply in the network equipment in embodiment one, embodiment two, embodiment three, comprising:
Registration module 501 registers interrupt processing function, the interruption to interruption processing module 503 for multi-core processor
Processing function can be handled on each core of multi-core processor；
Reporting module 502 sends monitoring request to single-chip microcontroller respectively for each core in multi-core processor；And for institute
It states each core and reports keep-alive message to single-chip microcontroller according to the preset monitoring period respectively；
Monitoring module 504 receives the monitoring request that each core is sent for single-chip microcontroller, starts the monitoring to the core；
It is also used to single-chip microcontroller and receives each core according to the keep-alive message of preset monitoring periodic report, when time-out does not receive some core
Keep-alive message when triggering interrupt；
Interruption processing module 503, for when single-chip microcontroller is triggered and is interrupted, by the interrupt processing function collect it is described some
The status information of core simultaneously starts correcting strategy；If the interrupt processing function, without response, the single-chip microcontroller is multiple according to reset timing
The position multi-core processor.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the protection scope in claims.
Claims (10)
1. the fault handling method of multi-core processor, which is characterized in that the described method includes:
Multi-core processor registers interrupt processing function, and the interrupt processing function can be located on each core of multi-core processor
Reason；Each core sends monitoring request after single-chip microcontroller receives monitoring request to single-chip microcontroller respectively and starts to the core in multi-core processor
Monitoring；Each core reports keep-alive message to single-chip microcontroller according to the preset monitoring period respectively；When single-chip microcontroller time-out is not received
To some core keep-alive message when triggering interrupt, status information and the starting of some core are collected by the interrupt processing function
Correcting strategy.
2. the method as described in claim 1, which is characterized in that the monitoring request includes: core ID and the preset monitoring
Period.
3. method according to claim 2, which is characterized in that the keep-alive message includes: core ID.
4. the method as described in claim 1, which is characterized in that the status information includes: core ID；Plan is repaired in the starting
Slightly, comprising: some described core is restarted or disabled to the core ID of some core according to collection.
5. method according to any of claims 1-4, which is characterized in that the method also includes: it is described when single-chip microcontroller is super
Triggering is interrupted when Shi Wei receives the keep-alive message of some core, if the interrupt processing function is without response, the single-chip microcontroller is according to multiple
Bit timing resets the multi-core processor.
6. the fault treating apparatus of multi-core processor, which is characterized in that described device includes:
Registration module registers interrupt processing function to interruption processing module for multi-core processor, and the interrupt processing function exists
It can be handled on each core of multi-core processor；
Reporting module sends monitoring request to single-chip microcontroller respectively for each core in multi-core processor；And for described each
Core reports keep-alive message to single-chip microcontroller according to the preset monitoring period respectively；
Monitoring module receives the monitoring request that each core is sent for single-chip microcontroller, starts the monitoring to the core；For monolithic
Machine receives each core according to the keep-alive message of preset monitoring periodic report, when time-out does not receive the keep-alive message of some core
When triggering interrupt；
Interruption processing module, for collecting the shape of some core by the interrupt processing function when single-chip microcontroller is triggered and interrupted
State information simultaneously starts correcting strategy.
7. a kind of network equipment characterized by comprising
Multi-core processor, for registering interrupt processing function, each core of the interrupt processing function in the multi-core processor
On can collect the status information of some core and start correcting strategy；It is also used to each core and sends prison to single-chip microcontroller respectively
Control request, and keep-alive message is reported to the single-chip microcontroller according to the preset monitoring period；
The monitoring of each core is requested and started to single-chip microcontroller for receiving the monitoring, when the keep-alive that time-out does not receive some core disappears
It triggers and interrupts when breath, the status information of some core is collected by the interrupt processing function and start correcting strategy.
8. the network equipment as claimed in claim 7, which is characterized in that the status information includes: core ID；The starting is repaired
Strategy, comprising: some described core is restarted or disabled to the core ID of some core according to collection.
9. the network equipment as claimed in claim 7, which is characterized in that monitoring request includes: core ID and described preset
Monitor the period；The keep-alive message includes: core ID.
10. such as the described in any item network equipments of claim 7-9, which is characterized in that the single-chip microcontroller is also used to, when time-out not
Triggering is interrupted when receiving the keep-alive message of some core, if described in the interrupt processing function resets without response, according to reset timing
Multi-core processor.
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