CN111813207B - Chip resetting device and relay protection device - Google Patents
Chip resetting device and relay protection device Download PDFInfo
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- CN111813207B CN111813207B CN202010731938.6A CN202010731938A CN111813207B CN 111813207 B CN111813207 B CN 111813207B CN 202010731938 A CN202010731938 A CN 202010731938A CN 111813207 B CN111813207 B CN 111813207B
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- protection device
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The application discloses chip resetting means and relay protection device, wherein chip resetting means includes: a safety monitoring processor and a plurality of monitoring registers; the number of the monitoring registers is the same as that of the functional cores of the relay protection device; the input ends of the monitoring registers are used for being connected with the functional cores in a one-to-one correspondence manner; the monitoring register is used for periodically acquiring the running signals sent by the correspondingly connected functional cores; the safety monitoring processor is used for periodically acquiring the operation signal sent by the monitoring register; the relay protection device is also used for judging the running state of the functional core corresponding to the running signal based on preset judging conditions, and when the running state of the functional core is judged to be abnormal, a reset command is sent to the monitoring register to reset the functional core, so that the technical problem that when the relay protection device of the multifunctional core is faced, the functional cores which run normally and run abnormally are reset at the same time, and unnecessary waste and trouble are caused is solved.
Description
Technical Field
The application relay protection device technical field especially relates to a chip resetting means and relay protection device.
Background
With the development of digital power technology, the digital relay protection device is popularized and applied in a power system. Meanwhile, the reliability and stability of the digital relay protection device are also increasingly required by the power system.
When the relay protection device is abnormal, the relay protection device can normally work by resetting, however, the reset of the conventional relay protection device is controlled by the main control chip, and when the relay protection device is reset, the whole relay protection device is restarted, so that when the relay protection device faces a multifunctional core, the functional core which normally operates and operates abnormally resets simultaneously, and unnecessary waste and trouble are caused.
Disclosure of Invention
In view of this, the application provides a chip reset device and a relay protection device, which solves the technical problems that the reset of the existing relay protection device is controlled by a main control chip, and the whole relay protection device is restarted during reset, so that when the relay protection device faces a multifunctional core, functional cores which normally operate and abnormally operate reset simultaneously, and unnecessary waste and trouble are caused.
The application provides a chip resetting means in a first aspect, is applied to relay protection device, includes: a safety monitoring processor and a plurality of monitoring registers;
the number of the monitoring registers is the same as that of the functional cores of the relay protection device;
the input ends of the monitoring registers are used for being connected with the functional cores in a one-to-one correspondence mode;
the monitoring register is used for periodically acquiring the running signal sent by the correspondingly connected functional core;
the safety monitoring processor is used for periodically acquiring the operation signal sent by the monitoring register; and the monitoring device is also used for judging the running state of the functional core corresponding to the running signal based on a preset judgment condition, and sending a reset command to the monitoring register to reset the functional core when the running state of the functional core is judged to be abnormal.
Optionally, the operation signal is: a one-way cumulative value;
the preset judgment condition is as follows: and if the one-way accumulated value is not changed, the function core corresponding to the one-way accumulated value is abnormal in operation, and if the one-way accumulated value is not changed, the function core is normal in operation.
Optionally, the operation signal is: presetting a fixed value;
the preset judgment condition is as follows: and if the preset fixed value is not changed, the function core corresponding to the preset fixed value operates normally, and if not, the operation is abnormal.
Optionally, the method further comprises:
and the watchdog logic circuit is connected with the safety monitoring processor and used for judging the running state of the safety monitoring processor.
Optionally, the safety monitoring processor is: CK803 type processors.
Optionally, the storage module of the safety monitoring processor is a primary cache and/or a secondary cache of the relay protection device.
The present application provides in a second aspect a relay protection device, including: a plurality of functional cores and a chipized reset means as described in the second aspect;
and the plurality of functional cores are connected with the plurality of monitoring registers of the chip resetting device in a one-to-one correspondence manner.
Optionally, the functional core is further configured to trigger a reset signal of the relay protection device when it is determined that the reset command sent by the monitoring register is not obtained.
Optionally, a plurality of the functional cores are functional cores that execute the same function.
Optionally, the plurality of functional cores are functional cores that each perform a different function.
According to the technical scheme, the embodiment of the application has the following advantages:
the application provides a be applied to relay protection device's chip resetting means includes: a safety monitoring processor and a plurality of monitoring registers; the number of the monitoring registers is the same as that of the functional cores of the relay protection device; the input ends of the monitoring registers are used for being connected with the functional cores in a one-to-one correspondence manner; the monitoring register is used for periodically acquiring the running signals sent by the correspondingly connected functional cores; the safety monitoring processor is used for periodically acquiring the operation signal sent by the monitoring register; and the monitoring device is also used for judging the running state of the functional core corresponding to the running signal based on a preset judgment condition, and sending a reset command to the monitoring register to reset the functional core when judging that the running state of the functional core is abnormal.
The chip reset device in the application comprises a plurality of monitoring registers, the number of the monitoring registers is the same as that of the functional cores of the relay protection device, and the two are connected in one-to-one correspondence, so that the monitoring register can acquire the operation signal of the functional core connected to the monitoring register, the safety detection processor can then judge the operating state of the corresponding functional core according to the operating signal, so as to reset the subsequent corresponding functional cores, and thus, each functional core is independently judged and independently reset without mutual influence, thereby solving the problem that the reset of the prior relay protection device is controlled by a main control chip, when the relay protection device is reset, the whole relay protection device is restarted, so that the functional cores which normally operate and abnormally operate are reset at the same time when the relay protection device faces the multifunctional cores, and the technical problems of unnecessary waste and trouble are caused.
Drawings
Fig. 1 is a schematic structural diagram of an embodiment of a resetting device for a chip in an embodiment of the present application;
fig. 2 is a schematic structural diagram of an embodiment of a relay protection device in an embodiment of the present application;
fig. 3 is a schematic diagram of an implementation structure of a relay protection device in an embodiment of the present application.
Detailed Description
The embodiment of the application provides a chip resetting device and a relay protection device, and solves the technical problems that the resetting of the existing relay protection device is controlled by a main control chip, the whole relay protection device is restarted when the resetting is carried out, and thus when the relay protection device faces a multifunctional core, the functional core which operates normally and abnormally resets simultaneously, and unnecessary waste and trouble are caused.
In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, a first structure of a chip-based reset device according to an embodiment of the present application is schematically illustrated.
The chip reset device in this embodiment is applied to a relay protection device, and includes: a safety monitoring processor 1 and a plurality of monitoring registers 2; the number of the monitoring registers 2 is the same as that of the functional cores of the relay protection device; the input end of the monitoring register 2 is used for connecting the functional cores in a one-to-one correspondence manner; the monitoring register 2 is used for periodically acquiring an operation signal sent by a correspondingly connected functional core; the safety monitoring processor 1 is used for periodically acquiring the running signal sent by the monitoring register 2; and the monitoring device is also used for judging the running state of the functional core corresponding to the running signal based on a preset judgment condition, and sending a reset command to the monitoring register 2 to reset the functional core when judging that the running state of the functional core is abnormal.
The chip reset device in this embodiment includes a plurality of monitoring registers 2, the number of the monitoring registers 2 is the same as the number of the functional cores of the relay protection device, and the two are connected in one-to-one correspondence, so that the monitoring register 2 can acquire the operation signal of the functional core connected thereto, the safety detection processor can then judge the operating state of the corresponding functional core according to the operating signal, so as to reset the subsequent corresponding functional cores, and thus, each functional core is independently judged and reset independently without mutual influence, thereby solving the problem that the reset of the prior relay protection device is controlled by a main control chip, when the relay protection device is reset, the whole relay protection device is restarted, so that the functional cores which normally operate and abnormally operate are reset at the same time when the relay protection device faces the multifunctional cores, and the technical problems of unnecessary waste and trouble are caused.
The above is a first embodiment of a resetting device for a chip provided in the embodiments of the present application, and the following is a second embodiment of a resetting device for a chip provided in the embodiments of the present application.
Referring to fig. 1, a schematic structural diagram of a second embodiment of a chip-based reset device in an embodiment of the present application is shown.
The chip reset device in this embodiment is applied to a relay protection device, and includes: a safety monitoring processor 1 and a plurality of monitoring registers 2; the number of the monitoring register 2 is the same as that of the functional cores of the relay protection device; the input end of the monitoring register 2 is used for connecting the functional cores in a one-to-one correspondence manner; the monitoring register 2 is used for periodically acquiring an operation signal sent by a correspondingly connected functional core; the safety monitoring processor 1 is used for periodically acquiring the running signal sent by the monitoring register 2; and the monitoring device is also used for judging the running state of the functional core corresponding to the running signal based on a preset judgment condition, and sending a reset command to the monitoring register 2 to reset the functional core when judging that the running state of the functional core is abnormal.
The operation signal in this embodiment may be, for example: the operating signals are: a one-way cumulative value; the preset judgment conditions are as follows: and if the one-way accumulated value is not changed, the function core corresponding to the one-way accumulated value is abnormal in operation, and if the one-way accumulated value is not changed, the function core is normal in operation. It will be appreciated that the operating signal may also be: presetting a fixed value; the preset judgment conditions are as follows: and if the preset fixed value is not changed, the function core corresponding to the preset fixed value operates normally, and if not, the operation is abnormal.
It should be noted that the description of the operation signal is only an exemplary schematic description, and those skilled in the art may perform specific setting according to needs, and details are not described herein.
It can be understood that, in this embodiment, the operation state of the safety monitoring processor 1 is also monitored to ensure the monitoring performance of the safety monitoring processor 1, and specifically, the on-chip reset device in this embodiment further includes: and the watchdog logic circuit 3 is connected with the safety monitoring processor 1 and is used for judging the running state of the safety monitoring processor 1.
It can be understood that, in the working process, the watchdog logic circuit 3 may periodically receive the data sent by the safety monitoring processor 1, and when the safety monitoring processor 1 is abnormal, the sent data may also be abnormal, and at this time, the watchdog logic circuit 3 resets the safety monitoring processor 1.
The safety monitoring processor 1 in this embodiment is a CK803 type processor, which belongs to a non-main processor in the relay protection device, and therefore, the setting of the function does not affect the performance of the entire relay protection device.
It is understood that the safety monitoring processor 1 may also have other types of structures, and those skilled in the art can perform the setting according to the needs, and the details are not described herein.
In the embodiment, the storage module of the relay protection device directly uses the primary cache and/or the secondary cache of the relay protection device, so that the access efficiency can be improved, the condition that the external RAM is interfered when the external RAM is used can be avoided, and the reliability is improved.
In the present embodiment, in order to reduce the size of the on-chip reset device, a plurality of monitor registers 2 are integrated into one multi-core monitor register 2.
The chip reset device in the embodiment comprises a plurality of monitoring registers 2, the number of the monitoring registers 2 is the same as that of the functional cores of the relay protection device, and the two are connected in one-to-one correspondence, so that the monitoring register 2 can acquire the operation signal of the functional core connected thereto, the security detection processor may then determine the operating state of the corresponding functional core from the operating signal, so as to reset the subsequent corresponding functional cores, and thus, each functional core is independently judged and independently reset without mutual influence, thereby solving the problem that the reset of the prior relay protection device is controlled by a main control chip, when the relay protection device is reset, the whole relay protection device is restarted, so that the functional cores which normally operate and abnormally operate are reset at the same time when the relay protection device faces the multifunctional cores, and the technical problems of unnecessary waste and trouble are caused.
The second embodiment of the resetting device in chip form provided in the embodiment of the present application is as follows, please refer to fig. 2.
The relay protection device provided in the embodiment of the present application includes: a plurality of functional cores 4 and a chip reset device in the first embodiment or the second embodiment; the plurality of functional cores 4 are connected with the plurality of monitoring registers 2 of the chip reset device in a one-to-one correspondence manner.
It should be noted that the monitoring registers 2 connected to the functional cores 4 one by one may acquire the operation signals corresponding to the functional cores 4, and further determine the operation state of the functional cores 4 by using the operation signals, so as to determine whether to perform reset processing on the functional cores 4.
In this embodiment, not only the safety monitoring processor 1 may monitor the functional core 4, but also the functional core 4 monitors the safety monitoring processor 1, so as to ensure stable performance of the relay protection device, and specifically, the functional core 4 is further configured to trigger a reset signal of the relay protection device when it is determined that the reset command sent by the monitoring register 2 is not obtained.
It can be understood that the relay protection device is provided with a reset signal for triggering the reset of the whole relay protection device, and the functional core 4 triggers the reset signal when judging that the safety monitoring processor 1 operates abnormally.
Generally, when the safety monitoring processor 1 is abnormally operated, the whole relay protection device is usually unrecoverable, so that the signal for resetting the safety monitoring processor 1 in the watchdog logic circuit 3 is also a reset signal of the relay protection device.
It can be understood that, in this embodiment, the plurality of function cores 4 may be function cores 4 that execute the same function, so that when a single function core 4 operates abnormally, a seamless switching may be performed to a function core 4 that operates normally, a blank period may not occur, and the operation performance of the relay protection device is improved.
It is understood that the plurality of functional cores 4 may also be functional cores 4 that each execute a different function, so that the respective reset processes of the respective functional cores 4 do not affect each other when executing the respective corresponding functions.
For example, as shown in fig. 3, in this embodiment, the safety detection processor 1, the monitoring register 2, and the plurality of functional cores 4 are all disposed in an SOC chip of the relay protection device, and the functional cores are respectively: the data processing function core 4, the protection lockout function core 4, the protection logic function core 4, and the management function core 4, it should be understood that the above description of the different function cores 4 is only an exemplary illustration, and those skilled in the art may specifically set the functions as needed, and details are not described here.
It can be understood that different functional cores are designed on the SOC chip, the functional cores are respectively a data processing functional core 4, a protection blocking functional core 4, a protection logic functional core 4, and a management functional core 4, and a security monitoring processor 1 for monitoring the functional cores and a watchdog logic circuit 3 are arranged in the SOC chip.
Compared with the prior art, the relay protection device in the embodiment has the following advantages:
1) the small processor in the relay protection device is used for playing a role of safety monitoring, so that more resources are not distributed to safety monitoring by the main kernel with the functions of protection, locking and the like, and other kernels are concentrated in functional application of the kernel, so that the reliability and the stability of the digital relay protection device are improved;
2) the watchdog supervision and reset operation can be reasonably carried out on each functional core 4;
3) memory operation in the chip improves the processing efficiency;
4) and the logic detection of the external hardware watchdog improves the overall safety and reliability.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (10)
1. The utility model provides a chip resetting means, is applied to relay protection device which characterized in that includes: the system comprises a safety monitoring processor and a plurality of monitoring registers;
the number of the monitoring registers is the same as that of the functional cores of the relay protection device;
the input ends of the monitoring registers are used for being connected with the functional cores in a one-to-one correspondence mode;
the monitoring register is used for periodically acquiring the running signal sent by the correspondingly connected functional core;
the safety monitoring processor is used for periodically acquiring the operation signal sent by the monitoring register; and the monitoring device is also used for judging the running state of the functional core corresponding to the running signal based on a preset judgment condition, and sending a reset command to the monitoring register to reset the functional core when the running state of the functional core is judged to be abnormal.
2. The on-chip reset device of claim 1, wherein the operation signal is: a one-way cumulative value;
the preset judgment condition is as follows: and if the one-way accumulated value is not changed, the function core corresponding to the one-way accumulated value is abnormal in operation, and if the one-way accumulated value is not changed, the function core is normal in operation.
3. The on-chip reset device of claim 1, wherein the operation signal is: presetting a fixed value;
the preset judgment condition is as follows: and if the preset fixed value is not changed, the function core corresponding to the preset fixed value operates normally, and if not, the operation is abnormal.
4. The on-chip reset device of claim 1, further comprising:
and the watchdog logic circuit is connected with the safety monitoring processor and used for judging the running state of the safety monitoring processor.
5. The on-chip reset device of claim 1, wherein the safety monitoring processor is: a CK803 type processor.
6. The on-chip reset device of claim 1, wherein the storage module of the safety monitoring processor is a primary cache and/or a secondary cache of a relay protection device.
7. A relay protection device, comprising: a plurality of functional cores and a chiped reset device as claimed in any one of claims 1 to 6;
and the plurality of functional cores are connected with the plurality of monitoring registers of the chip resetting device in a one-to-one correspondence manner.
8. The relay protection device according to claim 7, wherein the functional core is further configured to trigger a reset signal of the relay protection device when it is determined that the reset command sent by the monitoring register is not obtained.
9. The relay protection device according to claim 7, wherein the plurality of functional cores are functional cores that perform the same function.
10. The relay protection device according to claim 7, wherein the plurality of functional cores are functional cores each performing a different function.
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| CN202010731938.6A CN111813207B (en) | 2020-07-27 | 2020-07-27 | Chip resetting device and relay protection device |
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| CN202010731938.6A CN111813207B (en) | 2020-07-27 | 2020-07-27 | Chip resetting device and relay protection device |
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| CN113258547B (en) * | 2021-07-01 | 2021-09-24 | 南方电网数字电网研究院有限公司 | Chip-level relay protection device and system |
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