CN101615031A - The failure detection circuit of embedded dual processor system - Google Patents
The failure detection circuit of embedded dual processor system Download PDFInfo
- Publication number
- CN101615031A CN101615031A CN200910050757A CN200910050757A CN101615031A CN 101615031 A CN101615031 A CN 101615031A CN 200910050757 A CN200910050757 A CN 200910050757A CN 200910050757 A CN200910050757 A CN 200910050757A CN 101615031 A CN101615031 A CN 101615031A
- Authority
- CN
- China
- Prior art keywords
- microprocessor
- circuit
- master
- failure detection
- master microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Debugging And Monitoring (AREA)
- Hardware Redundancy (AREA)
- Power Sources (AREA)
Abstract
The present invention proposes a kind of failure detection circuit of embedded dual processor system, comprises master microprocessor, from microprocessor, watchdog circuit and power circuit.Wherein, watchdog circuit links to each other with master microprocessor, is used to monitor the running status of master microprocessor, and occurs it being resetted when unusual at master microprocessor.Master microprocessor by communicating circuit with link to each other from microprocessor, its with carry out real-time communication from microprocessor, and send an enable signal to this power circuit according to running status from microprocessor.Power circuit respectively with master microprocessor and linking to each other from microprocessor, be used for the enable signal that sends according to master microprocessor, provide or interrupt operating voltage from microprocessor.The present invention can effectively prevent the abnormality of master and slave microprocessor in the control system, and guarantees that the work schedule of master and slave microprocessor is identical, and it has advantage simple in structure, that circuit cost is low, reliability is high.
Description
Technical field
The present invention relates to a kind of testing circuit, particularly a kind of failure detection circuit of embedded dual processor system.
Background technology
As everyone knows, single chip microcomputer is small and exquisite flexibly, extendability is strong, can constitute some powerful control system (for example the microcomputer excitation installment of generator etc.).Conventional single-chip computer control system often all uses a CPU (processor), expands a series of peripheral auxiliary circuits again, to reach the purpose of corresponding control.But progressively perfect along with the single-chip computer control system function makes its hardware also complicated all the more, especially in the IO interface system with more, uses single cpu must carry out loaded down with trivial details decoding, logical conversion, and debugging is difficulty very.And, also, the travelling speed of system is restricted because increasing of hardware capability makes the processing power of single cpu be difficult to satisfy the requirement of system.
Thus, the control system of two CPU is arisen at the historic moment, and two CPU can improve the operational efficiency of system, accelerates the response speed of system.In addition, owing to such as reasons such as work under bad environment, electromagnetic interference (EMI), even use single-chip microcomputer by industrial measurement and control environmental requirement design also to be difficult to guarantee the operation that CPU can be reliably and with long-term, and the Redundancy Design of two CPU is very effective a kind of solution, when a CPU can't work, another CPU can share the former work to a certain extent, can prevent systemic breakdown effectively.
For the reliability of further raising system, in the control system of two CPU, need to take enough fool proofs, anti-measure of crashing, guarantee the continuous firing of CPU.Scheme commonly used now is for each CPU a watchdog circuit (watchdog timer) to be set.As shown in Figure 1, include a master microprocessor 101 and one in this schematic diagram from microprocessor 103, master microprocessor 101 with watchdog circuit 105,107 is equipped with respectively from microprocessor 103.
Watchdog circuit is a timer circuit, watchdog circuit 105,107 just begins counting when system moves, master microprocessor 101 can be exported a feeding-dog signal at set intervals to watchdog circuit 105, also can export a feeding-dog signal at set intervals to watchdog circuit 107 from microprocessor 103, and with watchdog circuit 105,107 zero clearings.If master microprocessor 101 or do not send feeding-dog signal when program fleet (generally be) within a certain period of time from microprocessor 103, so Dui Ying watchdog circuit counter will overflow, and send a reset signal to unusual microprocessor, it is resetted.Therefore the effect of watchdog circuit 105,107 is exactly to prevent program generation endless loop, prevents master microprocessor 101 and crashes from microprocessor 103.
But the control system of this couple of present CPU still exists some defectives, now is summarized as follows:
1, present two system control cpus all add a watchdog circuit at each microprocessor, because watchdog circuit works alone, therefore on electrifying timing sequence, be difficult to control, in the course of the work, in case some microprocessors reset, another microprocessor is operate as normal still then, so just may cause the work schedule difference of two processors, can't co-ordination.For example aspect reseting logic, fault handling, when two CPU control programs are started working, need be to relevant interface, storage space, parameter and initialization of variable, in case program " race flies " phenomenon appears in wherein some CPU, its watchdog circuit can move immediately, reset and it is restarted, then initialized CPU may produce with the normal process program of another CPU and conflict if another CPU still normally moves according to original program this moment.
2, in a system two cover watchdog circuits are set, will certainly cause the increase of equipment cost, and produce the system of selling in batches for some, a little cost increase also can be cut down its market competitiveness.
Summary of the invention
The failure detection circuit that the purpose of this invention is to provide a kind of embedded dual processor system is to solve the shortcoming that is easy to generate conflict between existing pair of system control cpu circuit cost height, the CPU.
The present invention proposes a kind of failure detection circuit of embedded dual processor system, comprises master microprocessor, from microprocessor, watchdog circuit and power circuit.Wherein, watchdog circuit links to each other with master microprocessor, is used to monitor the running status of master microprocessor, and occurs it being resetted when unusual at master microprocessor.Master microprocessor by communicating circuit with link to each other from microprocessor, its with carry out real-time communication from microprocessor, and send an enable signal to this power circuit according to running status from microprocessor.Power circuit respectively with master microprocessor and linking to each other from microprocessor, be used for the enable signal that sends according to master microprocessor, provide or interrupt operating voltage from microprocessor.
According to the failure detection circuit of the described embedded dual processor system of preferred embodiment of the present invention, power circuit is the DC-DC insulating power supply.
According to the failure detection circuit of the described embedded dual processor system of preferred embodiment of the present invention, the DC-DC insulating power supply comprises recommends switching power circuit and voltage stabilizer.Recommend switching power circuit and link to each other, be used to export a voltage, and control the duty of itself by the enable signal that master microprocessor sends with master microprocessor.Voltage stabilizer respectively with recommend switching power circuit and linking to each other from microprocessor, be used for that the voltage of recommending switching power circuit output is carried out voltage stabilizing and handle, and export operating voltage from microprocessor.
According to the failure detection circuit of the described embedded dual processor system of preferred embodiment of the present invention, communicating circuit is that photoelectricity is isolated the RS232 communicating circuit.
The invention has the beneficial effects as follows:
1, the present invention is when master microprocessor is restarted, make from microprocessor and also restart simultaneously, therefore make master and slave microprocessor on work schedule, remain unanimity, when the routine processes that reseting logic, fault handling etc. are had relatively high expectations to sequential, also can not produce conflict.
2, master microprocessor of the present invention remains the monitoring from microprocessor, in case abnormality occurs from microprocessor, then automatically cutting off immediately forces it is resetted from the microprocessor work power supply restarts, so the present invention can guarantee the long operate as normal of system.
3, the present invention has only adopted single watchdog circuit in the system of two CPU, has reduced the circuit cost of system, produces the system of selling in batches for some, effectively reduces its production cost, has increased its market competitiveness.
Description of drawings
Fig. 1 is the theory diagram of existing a kind of pair of system control cpu;
Fig. 2 is the failure detection circuit Organization Chart of a kind of embedded dual processor system of the embodiment of the invention;
Fig. 3 is a kind of watchdog circuit of the embodiment of the invention;
Fig. 4 is a kind of main processor circuit figure of the embodiment of the invention;
Fig. 5 is a kind of from microcontroller circuit figure of the embodiment of the invention;
Fig. 6 is a kind of communicating circuit figure of the embodiment of the invention;
Fig. 7 is a kind of power circuit diagram of the embodiment of the invention.
Embodiment
Principle of the present invention is only to be provided with a watchdog circuit in the control system of dual micro processor, omitted watchdog circuit from microprocessor, and detect running status from microprocessor by the communication between principal and subordinate's microprocessor, and utilize master microprocessor to control, thereby reach the purpose of system's fool proof from the powering on and power down of microprocessor.
Below in conjunction with accompanying drawing, specify the present invention.
See also Fig. 2, it is the failure detection circuit Organization Chart of a kind of embedded dual processor system of the embodiment of the invention.It comprises master microprocessor 201, from microprocessor 203, watchdog circuit 205 and power circuit 207.Watchdog circuit 205 links to each other with master microprocessor 201, and master microprocessor 201 links to each other respectively with from microprocessor 203 and power circuit 207, power circuit 207 with link to each other from microprocessor 203.
During operate as normal, voltage VCC provides operating voltage for master microprocessor 201, and the voltage VCC1 of power circuit 207 outputs is for providing operating voltage from microprocessor 203.Wherein, can provide by various types of power circuits,, anyly can be from microprocessor 203 power supplies and can all be applicable to the present invention by controlled power circuit in master microprocessor 201 as the DC-DC insulating power supply etc. from the power supply of microprocessor 203.
The effect of watchdog circuit 205 is running statuses of monitoring master microprocessor 201, and when master microprocessor 201 appearance are unusual it is resetted.In the time of master microprocessor 201 normal operations, can make the counter O reset of watchdog circuit 205 to feeding-dog signal of watchdog circuit 205 outputs at set intervals.Do not send feeding-dog signal if exceed schedule time, illustrate that unusual condition may appear in master microprocessor 201, be i.e. deadlock, program endless loop etc.At this moment watchdog circuit 205 will send reset signal to master microprocessor 201, and it is restarted.
When master microprocessor 201 resetted, the enable signal of reset power circuit 207 quit work it, thereby made voltage VCC1 power down, made from microprocessor 203 voltage of losing the job to force it is resetted.After master microprocessor 201 is restarted, restart work, make voltage VCC1 re-power, make from microprocessor 203 and restart by enable signal control power circuit 207.Therefore, master microprocessor 201 reset restart in, also can reset from microprocessor 203 and to restart, sequential is consistent.
In addition, when operate as normal, master microprocessor 201 is understood and is carried out real-time communication from microprocessor 203, within a certain period of time can be to master microprocessor 201 return state information from microprocessor 203.If do not have return state information at the appointed time from microprocessor 203, the status information of perhaps returning occurs unusual, and master microprocessor 201 can quit work by control power circuit 207 so, cuts off the power supply from microprocessor 203.And then recover power circuit 207 and work on, making powers on from microprocessor 203 restarts, thereby reaches the function of master-slave mode failure detection.
With a physical circuit the present invention is described below.See also Fig. 3, U3 is a kind of watchdog circuit of the embodiment of the invention, and this watchdog circuit realizes that by chip X5045S81-4.5A its WDI pin links to each other with master microprocessor 201 with the RST pin.The WDI signal is the feeding-dog signal that master microprocessor 201 sends, if primary processor 201 does not send the WDI signal in the certain hour section, just then can export the RESET1 signal from the RST pin.
See also Fig. 4, U1 is a kind of main processor circuit figure of the embodiment of the invention, and the VCC pin provides operating voltage for master microprocessor 201.RST pin and P3.7 pin link to each other with watchdog circuit 205, and the RESET1 signal is the reset signals that watchdog circuit 205 transmission comes, and it can be controlled primary processor 201 and reset and restart.RXD pin and TXD pin are used for and carry out communication from microprocessor 203, and the RXD1 signal is the received signal of master microprocessor 201, and the TXD1 signal is the transmission signal of master microprocessor 201.The P1.0 pin is connected to power circuit, and the DCDC-EN signal is the enable signal of master microprocessor 201 to the power circuit transmission.
See also Fig. 5, U2 is a kind of from microcontroller circuit figure of the embodiment of the invention.Its VCC pin is connected to power circuit, and signal VCC1 is the operating voltage from microprocessor 203.Its RXD pin and TXD pin are used for carrying out communication with master microprocessor 201, and the RXD2 signal is the received signal from microprocessor 203, and the TXD2 signal is the transmission signal from microprocessor 203.Can self status information be sent to master microprocessor 201 by the TXD2 signal every a time period from microprocessor 203, so master microprocessor 201 can be judged running status from microprocessor 203 according to the TXD2 signal.If within a certain period of time, do not export the TXD2 signal from microprocessor 203, then show from microprocessor 203 and lost efficacy or abnormality occurs.
See also Fig. 6, it is a kind of communicating circuit figure of the embodiment of the invention.This circuit OPT1 and circuit OPT2 have formed one and have isolated optocoupler RS232 communicating circuit, it is connected master microprocessor 201 and between the communication interface of microprocessor 203, its effect is to be that coal Jie transmits signal with light, can isolate the input and output circuit.Thereby can suppress system noise effectively, and eliminate the interference of ground loop, have that response speed is very fast, a little benefit such as shock-resistant of long service life, volume.The RS232 communicating circuit is a kind of serial communication circuit, and wherein TXD1, RXD1 signal are respectively the transmission signal and the received signal of master microprocessor 201, and TXD2, RXD2 signal are respectively transmission signal and the received signal from microprocessor 203.
See also Fig. 7, it is a kind of power circuit diagram of the embodiment of the invention.Circuit U 4 has been formed one with circuit B1 and has been recommended switching power circuit, circuit U 5 is mu balanced circuits, the output of recommending switching power circuit links to each other with mu balanced circuit, therefore after recommending the voltage process mu balanced circuit voltage stabilizing of switching power circuit generation, its output voltage V CC1 is as the power supply voltage from microprocessor 203.The SD pin is connected to master microprocessor 201, is used to receive the enable signal DCDC-EN that master microprocessor 201 sends.In the present embodiment, when master microprocessor 201 was restarted, perhaps from microprocessor 203 running statuses when unusual, master microprocessor 201 can be drawn high the DCDC-EN signal, make and recommend switching power circuit and quit work, thereby make power supply VCC1 power down from microprocessor 203.Master microprocessor 201 drags down the DCDC-EN signal more then, make and recommend switching power circuit and rework, make from the power supply VCC1 of microprocessor 203 to re-power, and by realizing restarting from resetting of microprocessor 203 from microprocessor 203 built-in electrification reset functions.Certainly, according to the different designs of power circuit, the height of DCDC-EN signal control also can change accordingly, as drags down the DCDC-EN signal and can make power supply VCC1 power down, draws high the DCDC-EN signal power supply VCC1 is powered on.
Than prior art, the present invention has the following advantages:
1, the present invention is when master microprocessor is restarted, make from microprocessor and also restart simultaneously, therefore make master and slave microprocessor on work schedule, remain unanimity, when the routine processes that reseting logic, fault handling etc. are had relatively high expectations to sequential, also can not produce conflict.
2, master microprocessor of the present invention remains the monitoring from microprocessor, in case abnormality occurs from microprocessor, then automatically cutting off immediately forces it is resetted from the microprocessor work power supply restarts, so the present invention can guarantee the long operate as normal of system.
3, the present invention has only adopted single watchdog circuit in the system of two CPU, has reduced the circuit cost of system, produces the system of selling in batches for some, effectively reduces its production cost, has increased its market competitiveness.
More than disclosed only be several specific embodiment of the present invention, but the present invention is not limited thereto, any those skilled in the art can think variation, all should drop in protection scope of the present invention.
Claims (8)
1, a kind of failure detection circuit of embedded dual processor system is characterized in that, comprises a master microprocessor, from microprocessor, a watchdog circuit and a power circuit, wherein,
Watchdog circuit, it links to each other with this master microprocessor, is used to monitor the running status of this master microprocessor, and occurs it being resetted when unusual at this master microprocessor;
Master microprocessor links to each other from microprocessor with this by a communicating circuit, and it carry out real-time communication with this from microprocessor, and sent an enable signal according to this running status from microprocessor to this power circuit;
Power circuit, its respectively with this master microprocessor and should link to each other from microprocessor, this enable signal that is used for sending according to this master microprocessor provides or interrupts this operating voltage from microprocessor.
2, the failure detection circuit of embedded dual processor system as claimed in claim 1 is characterized in that, this power circuit is the DC-isolation power supply that always circulates.
3, the failure detection circuit of embedded dual processor system as claimed in claim 2 is characterized in that, this DC-DC insulating power supply comprises:
One recommends switching power circuit, and it links to each other with this master microprocessor, is used to export a voltage, and controls the duty of itself by this enable signal that this master microprocessor sends;
One voltage stabilizer is recommended switching power circuit with this respectively and is reached and should link to each other from microprocessor, is used for that this this voltage of recommending switching power circuit output is carried out voltage stabilizing and handles, and export this operating voltage from microprocessor.
4, the failure detection circuit of embedded dual processor system as claimed in claim 1 is characterized in that, this communicating circuit is that a photoelectricity is isolated the RS232 communicating circuit.
5, the failure detection circuit of embedded dual processor system as claimed in claim 4 is characterized in that, this photoelectricity is isolated the RS232 communicating circuit and comprised:
One first light emitting diode, its negative pole links to each other with the signal sending end of this master microprocessor;
One first phototriode, its base stage is relative with this first light emitting diode, and its collector is connected to this signal receiving end from microprocessor;
One second light emitting diode, its negative pole links to each other with this signal sending end from microprocessor;
One second phototriode, its base stage is relative with this second light emitting diode, and its collector is connected to the signal receiving end of this master microprocessor.
6, the failure detection circuit of embedded dual processor system as claimed in claim 1 is characterized in that, this watchdog circuit is an X5045S81-4.5A chip.
7, the failure detection circuit of embedded dual processor system as claimed in claim 1 is characterized in that, this master microprocessor is an AT89C2051 chip.
8, the failure detection circuit of embedded dual processor system as claimed in claim 1 is characterized in that, should be an AT89C2051 chip from microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100507570A CN101615031B (en) | 2009-05-07 | 2009-05-07 | Failure detection circuit of embedded dual processor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100507570A CN101615031B (en) | 2009-05-07 | 2009-05-07 | Failure detection circuit of embedded dual processor system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101615031A true CN101615031A (en) | 2009-12-30 |
| CN101615031B CN101615031B (en) | 2011-05-04 |
Family
ID=41494710
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100507570A Active CN101615031B (en) | 2009-05-07 | 2009-05-07 | Failure detection circuit of embedded dual processor system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101615031B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102163071A (en) * | 2011-01-20 | 2011-08-24 | 海能达通信股份有限公司 | Control circuit and power control method during reset thereof |
| CN102541044A (en) * | 2010-12-31 | 2012-07-04 | 深圳迈瑞生物医疗电子股份有限公司 | Fault monitoring circuit and medical equipment |
| CN102591237A (en) * | 2012-02-29 | 2012-07-18 | 四川航天系统工程研究所 | Electrical dual-core control system of underground risk-avoiding apparatus and control method thereof |
| CN102722171A (en) * | 2012-06-08 | 2012-10-10 | 广东好帮手电子科技股份有限公司 | Method and system for detecting anomaly of automobile instrument |
| CN104021014A (en) * | 2014-05-23 | 2014-09-03 | 江苏兆伏新能源有限公司 | Firmware upgrading method based on double-CPU system |
| CN104731667A (en) * | 2013-12-19 | 2015-06-24 | 现代自动车株式会社 | Apparatus and method for monitoring multiple micro-cores |
| CN105243708A (en) * | 2015-09-22 | 2016-01-13 | 中国船舶重工集团公司第七一八研究所 | Intelligent lock internal hierarchical program and redundancy control framework |
| CN105527914A (en) * | 2016-01-19 | 2016-04-27 | 杭州义益钛迪信息技术有限公司 | Double-CPU reliably-designed base station power environment monitoring device and method |
| CN106896764A (en) * | 2017-02-17 | 2017-06-27 | 上海格尼特控制技术有限公司 | The double mcu closed loop control method of remote control receiver |
| CN107943259A (en) * | 2016-10-13 | 2018-04-20 | 普天信息技术有限公司 | Power-off reset method and apparatus based on VxWorks system |
| CN109412468A (en) * | 2018-09-10 | 2019-03-01 | 上海辛格林纳新时达电机有限公司 | System and control method based on safe torque shutdown |
| CN110198065A (en) * | 2019-06-21 | 2019-09-03 | 深圳市小兔充充科技有限公司 | The detection circuit of charging station and the detection device of charging station |
| CN111679929A (en) * | 2020-06-03 | 2020-09-18 | 北京经纬恒润科技有限公司 | Control method applied to multi-core heterogeneous system |
| CN111813207A (en) * | 2020-07-27 | 2020-10-23 | 南方电网数字电网研究院有限公司 | Chip resetting device and relay protection device |
| CN113535447A (en) * | 2021-06-30 | 2021-10-22 | 浙江中控技术股份有限公司 | Safety control device with dual-processor structure and implementation method |
| CN116027759A (en) * | 2021-10-26 | 2023-04-28 | 中车株洲电力机车研究所有限公司 | Processor board monitoring and diagnosing circuit and electronic equipment |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103500135A (en) * | 2013-10-15 | 2014-01-08 | 深圳市汇川技术股份有限公司 | Circuit for monitoring embedded device main program |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2100328U (en) * | 1991-07-17 | 1992-04-01 | 中国矿业大学北京研究生部 | Vehicle headlight lightening means |
| US7423919B2 (en) * | 2005-05-26 | 2008-09-09 | Micron Technology, Inc. | Method and system for improved efficiency of synchronous mirror delays and delay locked loops |
| CN1805425A (en) * | 2005-12-19 | 2006-07-19 | 大连海事大学 | Embedded intelligent signal processing system |
| CN101188828A (en) * | 2006-11-16 | 2008-05-28 | 中兴通讯股份有限公司 | Method for dual-processor mobile terminal to work status of process slave processor |
| CN201017275Y (en) * | 2007-02-09 | 2008-02-06 | 深圳市泽森通信有限公司 | Built-in CPU chip reset control circuit |
| CN101373128B (en) * | 2008-09-26 | 2011-09-07 | 丹阳弘业福天渔具有限公司 | Intelligent control circuit with cipher timing detonator |
-
2009
- 2009-05-07 CN CN2009100507570A patent/CN101615031B/en active Active
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102541044A (en) * | 2010-12-31 | 2012-07-04 | 深圳迈瑞生物医疗电子股份有限公司 | Fault monitoring circuit and medical equipment |
| CN102541044B (en) * | 2010-12-31 | 2016-09-14 | 深圳迈瑞生物医疗电子股份有限公司 | Fault monitoring circuit and armarium |
| CN102163071A (en) * | 2011-01-20 | 2011-08-24 | 海能达通信股份有限公司 | Control circuit and power control method during reset thereof |
| CN102163071B (en) * | 2011-01-20 | 2013-09-11 | 海能达通信股份有限公司 | Control circuit and power control method during reset thereof |
| CN102591237A (en) * | 2012-02-29 | 2012-07-18 | 四川航天系统工程研究所 | Electrical dual-core control system of underground risk-avoiding apparatus and control method thereof |
| CN102722171B (en) * | 2012-06-08 | 2014-07-30 | 广东好帮手电子科技股份有限公司 | Method and system for detecting anomaly of automobile instrument |
| CN102722171A (en) * | 2012-06-08 | 2012-10-10 | 广东好帮手电子科技股份有限公司 | Method and system for detecting anomaly of automobile instrument |
| CN104731667A (en) * | 2013-12-19 | 2015-06-24 | 现代自动车株式会社 | Apparatus and method for monitoring multiple micro-cores |
| CN104731667B (en) * | 2013-12-19 | 2019-04-05 | 现代自动车株式会社 | Monitor the device and method of multiple micro cores |
| CN104021014A (en) * | 2014-05-23 | 2014-09-03 | 江苏兆伏新能源有限公司 | Firmware upgrading method based on double-CPU system |
| CN105243708A (en) * | 2015-09-22 | 2016-01-13 | 中国船舶重工集团公司第七一八研究所 | Intelligent lock internal hierarchical program and redundancy control framework |
| CN105527914A (en) * | 2016-01-19 | 2016-04-27 | 杭州义益钛迪信息技术有限公司 | Double-CPU reliably-designed base station power environment monitoring device and method |
| CN107943259A (en) * | 2016-10-13 | 2018-04-20 | 普天信息技术有限公司 | Power-off reset method and apparatus based on VxWorks system |
| CN106896764A (en) * | 2017-02-17 | 2017-06-27 | 上海格尼特控制技术有限公司 | The double mcu closed loop control method of remote control receiver |
| CN109412468A (en) * | 2018-09-10 | 2019-03-01 | 上海辛格林纳新时达电机有限公司 | System and control method based on safe torque shutdown |
| CN110198065A (en) * | 2019-06-21 | 2019-09-03 | 深圳市小兔充充科技有限公司 | The detection circuit of charging station and the detection device of charging station |
| CN111679929A (en) * | 2020-06-03 | 2020-09-18 | 北京经纬恒润科技有限公司 | Control method applied to multi-core heterogeneous system |
| CN111813207A (en) * | 2020-07-27 | 2020-10-23 | 南方电网数字电网研究院有限公司 | Chip resetting device and relay protection device |
| CN111813207B (en) * | 2020-07-27 | 2022-05-17 | 南方电网数字电网研究院有限公司 | Chip resetting device and relay protection device |
| CN113535447A (en) * | 2021-06-30 | 2021-10-22 | 浙江中控技术股份有限公司 | Safety control device with dual-processor structure and implementation method |
| CN116027759A (en) * | 2021-10-26 | 2023-04-28 | 中车株洲电力机车研究所有限公司 | Processor board monitoring and diagnosing circuit and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101615031B (en) | 2011-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101615031B (en) | Failure detection circuit of embedded dual processor system | |
| CN107122321B (en) | Hardware repair method, hardware repair system, and computer-readable storage device | |
| CN104050061B (en) | A kind of Based PC Ie bus many master control board redundancies standby system | |
| CN203786723U (en) | Dual redundant system based on X86 PC/104 embedded CPU modules | |
| CN102163071B (en) | Control circuit and power control method during reset thereof | |
| CN111831488B (en) | TCMS-MPU control unit with safety level design | |
| CN103853622A (en) | Control method of dual redundancies capable of being backed up mutually | |
| CN102724083A (en) | Degradable triple-modular redundancy computer system based on software synchronization | |
| US20150019671A1 (en) | Information processing system, trouble detecting method, and information processing apparatus | |
| TWI529624B (en) | Method and system of fault tolerance for multiple servers | |
| CN105242608B (en) | Vehicle control unit and control method thereof | |
| JP6130520B2 (en) | MULTISYSTEM SYSTEM AND MULTISYSTEM SYSTEM MANAGEMENT METHOD | |
| CN103645678A (en) | Real-time response type network control system | |
| EP1882219A2 (en) | Sleep watchdog circuit for asynchronous digital circuits | |
| US20120131371A1 (en) | Method for obtaining power states of a computer | |
| US20190052355A1 (en) | Network switching system | |
| CN104035536A (en) | Monitoring and reset control method of embedded system | |
| CN101009684B (en) | Monitoring device and method for single-board operation state in the distributed system | |
| CN102495767A (en) | Double-watchdog system for battery monitor | |
| WO2016068993A1 (en) | Load discovery | |
| CN101557307A (en) | Dispatch automation system application state management method | |
| CN203552244U (en) | Hardware watchdog device for computer and software system | |
| CN116257342A (en) | Configurable fault-tolerant star software task scheduling system based on multi-core processor | |
| US20200026682A1 (en) | Techniques of accessing serial console of bmc using host serial port | |
| US20080140890A1 (en) | Electronic Circuit Arrangement For Detecting a Failing Clock |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190711 Address after: 310052 D302-D309 Area, 309 Liuhe Road, Puyan Street, Binjiang District, Hangzhou City, Zhejiang Province Patentee after: Zhejiang Zhongkong Automation Instrument Co., Ltd. Address before: 310053 Three Floors (High-tech Zone) of District 309 D, Liuhe Road, Binjiang District, Hangzhou City, Zhejiang Province Co-patentee before: Zhejiang Supcon Research Co., Ltd. Patentee before: Zhejiang Zhongkong Automation Instrument Co., Ltd. |