JPH04139866A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH04139866A
JPH04139866A JP26412790A JP26412790A JPH04139866A JP H04139866 A JPH04139866 A JP H04139866A JP 26412790 A JP26412790 A JP 26412790A JP 26412790 A JP26412790 A JP 26412790A JP H04139866 A JPH04139866 A JP H04139866A
Authority
JP
Japan
Prior art keywords
lead
integrated circuit
semiconductor chip
semiconductor integrated
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26412790A
Other languages
Japanese (ja)
Inventor
Isamu Kaminaga
神永 勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26412790A priority Critical patent/JPH04139866A/en
Publication of JPH04139866A publication Critical patent/JPH04139866A/en
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To shorten the delivery time, reduce the cost, and stabilize rear potential of a semiconductor chip through common use of inner leads by previously manufacturing inner leads in a reticulated shape and removing unnecessary parts from the leads. CONSTITUTION:A required inner lead shape is obtained by removing unnecessary parts from previously formed reticulated inner leads 1 and a semiconductor chip 2 is connected with outer lead pins 3 with the inner leads thus formed. The inner leads 1 thus formed are connected to rear leads 5 for stabilizing rear potential with the pins 3 in between. Therefore, the cost of semiconductor integrated circuit devices can be reduced and the rear potential of semiconductor chips can be stabilized, because the reticulated inner leads 1 can be used commonly to various kinds of semiconductor integrated circuit devices and the manufacture of a specific inner lead to each semiconductor integrated circuit device becomes unnecessary.

Description

【発明の詳細な説明】 〔産業上の利用分野] この発明は半導体集積回路装置の組立に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the assembly of semiconductor integrated circuit devices.

〔従来の技術] 第6図は従来のインナーリードを使用して組立1こ半導
体集積回路装置で2図昏こおいて、(1)はインナーリ
ード、(2)は半導体チップ、(3)は外部リードピン
、(4)は密封樹脂である0第7図はインナーリード(
t)を拡大しfこ部分拡大図である。
[Prior Art] Figure 6 shows a semiconductor integrated circuit device assembled using conventional inner leads, where (1) is an inner lead, (2) is a semiconductor chip, and (3) is an assembled semiconductor integrated circuit device. The external lead pin (4) is a sealing resin.0 Figure 7 shows the inner lead (
t) is an enlarged partial enlarged view of f.

次に動作について説明する。第6図において。Next, the operation will be explained. In FIG.

インナーリードfl)に半導体チップ(2)を接続し、
半導体チップ(2)を固定する。インナーリード(11
は外部リードビン(3)に接続され、密封樹脂(4)に
より密封される。
Connect the semiconductor chip (2) to the inner lead fl),
Fix the semiconductor chip (2). Inner lead (11)
is connected to an external lead bin (3) and sealed with a sealing resin (4).

半導体チップ(2)はインナーリード(1)、外部り−
ドビン(3)により外部回路C図示せず)と接合し、信
号の処理を行う。半導体チップ(2)は信号を処理する
回路によりその大きさが決まり、信号取出しPADの位
置もいろいろ変化し、外部リードピン(3)も信号処理
数により変わる1こめ半導体チップ(2)と外部リード
ピン(3)により、インナーリード(1)をそれぞれ専
用に製作する必要がある。
The semiconductor chip (2) has an inner lead (1) and an outer lead.
It is connected to an external circuit C (not shown) by a dobbin (3) and processes signals. The size of the semiconductor chip (2) is determined by the circuit that processes the signal, the position of the signal extraction PAD changes variously, and the external lead pin (3) also changes depending on the number of signals processed. Due to 3), it is necessary to manufacture each inner lead (1) exclusively.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体集積回路装置は以上のように溝成されてい
1こので、半導体チップと外部リードピンをこあわせて
、専用にインナーリードを製作しなければならず、製作
するの(二時間がかかり、ま1こ短納期を要求される半
導体集積回路装置には使用するのに難しく、まfこ、製
作費用もそれぞれ専用に製作するため高くなり、少量生
産の半導体集積回路装置では無駄が多くなるため、納期
、コストを考えてインナーリードでの共用化を考える必
%があり、まfこ、半導体チップの裏面がどこにも接続
されていないTこめ裏面電位を安定化させる必要がある
などの問題点かあつfこ。
Conventional semiconductor integrated circuit devices have grooves as described above.1 Therefore, it is necessary to combine the semiconductor chip and external lead pins and create a special inner lead, which takes two hours and takes two hours to manufacture. However, it is difficult to use in semiconductor integrated circuit devices that require short delivery times, and manufacturing costs are high because each device is manufactured specifically for each device, and there is a lot of waste in semiconductor integrated circuit devices that are produced in small quantities. It is necessary to consider sharing the inner lead in consideration of delivery time and cost, and there are problems such as the need to stabilize the backside potential of the T-hole where the backside of the semiconductor chip is not connected to anything. Kaatsu fko.

この発明は上記のような問題点を解消するTこめ昏こな
されTこもので、インナーリードの共用化により短納期
、コスト削減できるとともに、半導体チップの裏面電位
を安定化することができる半導体集積回路装置を得るこ
とを目的とする。
This invention has been painstakingly accomplished to solve the above-mentioned problems, and provides a semiconductor integrated circuit that can shorten delivery time and reduce costs by sharing inner leads, as well as stabilizing the backside potential of a semiconductor chip. The purpose is to obtain equipment.

〔課題を解決する1こめの手段] この発明に係る半導体集積回路装置は、あらかじめ網目
状のインナーリードを製作して置き、その不要部分を除
去することにより、インナーリードを形成し、まTこ、
このインナーリードとチップ裏面と導通する裏面リード
で、半導体チップを挾んで接続すること(こより、イン
ナーリードの共用化、半導体チップの裏面電位を取り安
冗化するようをこしγこものである。
[First Means for Solving the Problems] The semiconductor integrated circuit device according to the present invention has a mesh-like inner lead manufactured in advance and an unnecessary portion thereof removed to form the inner lead. ,
The semiconductor chip is connected by sandwiching the inner lead to the back surface lead that is electrically connected to the back surface of the chip (this makes it possible to share the inner lead and to secure the back surface potential of the semiconductor chip and make it redundant).

〔作用〕[Effect]

この発明における半導体集積回路装置は、あらかじめ網
目状にしであるインナーリードを不要部分の除去により
所望のインナーリード形状を形成し、半導体チップと外
部リードピンを接続する。
In the semiconductor integrated circuit device of the present invention, a desired shape of the inner lead is formed by removing unnecessary portions of the inner lead, which is previously formed into a mesh shape, and the semiconductor chip and external lead pins are connected to each other.

まTこ、この形成しfこインナーリードとチップ裏面電
位を安定化させる裏面リードで挾んで接続することによ
り、チップ裏面電位を取り安定させる。
By sandwiching and connecting this formed inner lead with a back surface lead that stabilizes the potential on the back surface of the chip, the potential on the back surface of the chip is taken and stabilized.

まTこ、裏面リードは形成しfこインナーリードの強度
補強も兼ねる。
The back leads are formed and also serve to strengthen the inner leads.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図はこの発明の一実施例である半導体集積回路装置の組
立状態を示す断面図で、図において、(1)はインナー
リード、(2)は半導体チップ、(3)は外部リードピ
ン、(4)は密封樹脂、(5)は裏面電位用の裏面リー
ドである。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view showing the assembled state of a semiconductor integrated circuit device that is an embodiment of the present invention. In the figure, (1) is an inner lead, (2) is a semiconductor chip, (3) is an external lead pin, and (4) is an inner lead. is a sealing resin, and (5) is a back surface lead for back surface potential.

第2図は第1図のインナーリードC1lの部分拡大図で
2図(こおいて、(1)はインナーリード、(2)は半
導体チップである。
FIG. 2 is a partially enlarged view of the inner lead C1l in FIG. 1 (here, (1) is the inner lead and (2) is the semiconductor chip.

第3図はインナーリードの不要部分を削除し1こ状態を
示す説明図で、図において、11)はインナーリード、
(2)は半導体チップ、(3)は外部リードピン。
Figure 3 is an explanatory diagram showing a state in which unnecessary parts of the inner lead have been removed. In the figure, 11) is the inner lead,
(2) is a semiconductor chip, and (3) is an external lead pin.

c211は大きさの異なる半導体チップである。c211 are semiconductor chips of different sizes.

第4図は裏面電位を取る裏面リード(5)の平面図であ
る。
FIG. 4 is a plan view of the back surface lead (5) that takes the back surface potential.

次に動作(こついて説明する。第1図において、インナ
ーリード(1)&こ半導体チップ(2)を接続し、半導
体チップ(2)を固定するユ、インナーリードf11は
外部リードピン(3)に接続され、また、裏面電位用リ
ド(5)を半導体チップ(2)の裏面に接続し、裏面電
位と同電位の外部リードピン(3)&こ接続する。最後
(こ密封樹脂(4)で密封する。インナーリード(1)
は、はじめは第2図のように網目状になっている。この
インナーリード【1)を半導体チップ(2)上の接続点
の位置、半導体チップ(2)の大きさ、半導体チップ(
2)上の接続点と外部リードピン(3)との接続の仕方
により、所望するリード形状を決め、不要部分を切り取
りインナーリードの形状を決める。インナーリード(1
)の形状が決まり接続しγこものが第3図であり、半導
体チップ(2)の大きさはある範囲で自由になり、ま1
こ、外部リードピン(3)と半導体チップ(2)の接続
も自由にできて、インナーリードfllの共用化ができ
る。
Next, the operation (I will explain the details. In Fig. 1, the inner lead (1) & semiconductor chip (2) are connected and the semiconductor chip (2) is fixed. The inner lead f11 is connected to the external lead pin (3). Also, connect the back surface potential lead (5) to the back surface of the semiconductor chip (2), and connect the external lead pin (3) with the same potential as the back surface potential.Finally, seal this with sealing resin (4). Inner lead (1)
Initially, it has a mesh shape as shown in Figure 2. This inner lead [1] is determined by the location of the connection point on the semiconductor chip (2), the size of the semiconductor chip (2), and the size of the semiconductor chip (2).
2) Determine the desired lead shape based on the connection between the upper connection point and the external lead pin (3), and then cut off unnecessary parts to determine the shape of the inner lead. Inner lead (1
) is decided and connected, and the γ component is shown in Figure 3, and the size of the semiconductor chip (2) can be set freely within a certain range, and
In addition, the external lead pins (3) and the semiconductor chip (2) can be freely connected, and the inner leads Fll can be shared.

裏面電位用裏面lノード(5)は半導体チップ(2)の
裏面電位を安定化することができ、まTこ、インナリー
ド+11の補強も兼ねている。
The back surface potential node (5) can stabilize the back surface potential of the semiconductor chip (2), and also serves to reinforce the inner leads +11.

以上?こよりインナーリードの共用化が図れ、コストが
低減でき、ま1こ、裏面電位を安定化することができる
that's all? This makes it possible to share the inner lead, reduce costs, and further stabilize the back surface potential.

なお、上記実施例ではインナーリード+i)が半導体チ
ップ(2)の上側、裏面リート責5)が下側になってい
るが逆になってもかまわない。
In the above embodiment, the inner lead +i) is on the upper side of the semiconductor chip (2), and the back lead +i) is on the lower side, but the reverse may be used.

まTこ、裏面リード(5)は第5図の如く密封樹脂の外
をこでていてもかまわない。まに、裏面リードがなくて
もよい。
However, the back leads (5) may extend outside the sealing resin as shown in FIG. However, there is no need for back leads.

ま1こ、上記実施例では裏面リード(5)は半導体チッ
プ(2)の裏面電位安定の1こめに使用したが、誤動作
の原因)ニなりうるリードインダクタンス低減のfこめ
に、TことえばP基板を使用し1こ半導体は裏面電位は
GND電位(こなるが、裏面リードを外部リードピンの
GNDビン(こすべて接続してGNDピンの面ffを犬
きくして、リードインダクタンスを低減させるのに使用
してもよい。
In the above embodiment, the back surface lead (5) was used to stabilize the potential on the back surface of the semiconductor chip (2), but in order to reduce the lead inductance, which may cause malfunction, T, in other words, P was used. When using a board, the back side potential of this semiconductor is GND potential (this is the case, but the back side lead is connected to the GND pin of the external lead pin (all these are connected to make the surface ff of the GND pin sharper, and this is used to reduce lead inductance. You may.

〔発明の効果〕〔Effect of the invention〕

以上のよう(ここの発明によれば、インナーリードの共
用化が図れ、半導体集積回路装置ごとに専用につくる必
要がなく、まTこコストが削減できるととも(こ、半導
体チップの裏面電位を安定化させることができるなどの
効果がある。
As described above (according to the present invention, the inner leads can be shared, there is no need to create a dedicated one for each semiconductor integrated circuit device, and the cost can be reduced (the backside potential of the semiconductor chip can be reduced). It has effects such as stabilization.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例である半導体集積回路装置
の組立断面図、第2図は第1図のインナー IJ−ドの
使用前の網目状の部分拡大図、第3図は第2図のインナ
ーリードの不要部分を切り取つTこ状態を示す部分拡大
図、第4図は第1図の裏面リード(5)の拡大平面図、
第5図はこの発明の他の実施例を示す半導体集積回路装
置の組立断面図、第6図は従来の半導体集積回路装置の
組立断面図。 第7図は第6図のインナーリードの部分拡大図である。 図(こおいて、(1)はインナーリード、(2)は半導
体チップ、(3)は外部リードピン、(4)は密封樹脂
、(5)は裏面電位をとる裏面リードを示す。 なお1図中、同一符号は同一、ま1こは相当部分を示す
FIG. 1 is an assembled cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. FIG. 4 is an enlarged plan view of the rear lead (5) shown in FIG. 1;
FIG. 5 is an assembled sectional view of a semiconductor integrated circuit device showing another embodiment of the present invention, and FIG. 6 is an assembled sectional view of a conventional semiconductor integrated circuit device. FIG. 7 is a partially enlarged view of the inner lead in FIG. 6. (In this figure, (1) shows the inner lead, (2) shows the semiconductor chip, (3) shows the external lead pin, (4) shows the sealing resin, and (5) shows the back side lead that takes the back side potential. Inside, the same reference numerals indicate the same parts, and squares indicate corresponding parts.

Claims (1)

【特許請求の範囲】[Claims]  あらかじめインナーリードの形状を網目状にして置き
、接続する半導体チップの仕様、外部リードピンの仕様
に合せて不要部分を除去して、形状を決めたインナーリ
ードと、半導体チップの裏面と導通する裏面リードで半
導体チップを挾みこんで接続、組立てることを特徴とす
る半導体集積回路装置。
The shape of the inner lead is made into a mesh shape in advance, and unnecessary parts are removed according to the specifications of the semiconductor chip to be connected and the specifications of the external lead pins.The shape of the inner lead is determined, and the back side lead conducts with the back side of the semiconductor chip. A semiconductor integrated circuit device characterized by sandwiching, connecting and assembling semiconductor chips.
JP26412790A 1990-10-01 1990-10-01 Semiconductor integrated circuit device Pending JPH04139866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26412790A JPH04139866A (en) 1990-10-01 1990-10-01 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26412790A JPH04139866A (en) 1990-10-01 1990-10-01 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04139866A true JPH04139866A (en) 1992-05-13

Family

ID=17398848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26412790A Pending JPH04139866A (en) 1990-10-01 1990-10-01 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04139866A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5606199A (en) * 1994-10-06 1997-02-25 Nec Corporation Resin-molded type semiconductor device with tape carrier connection between chip electrodes and inner leads of lead frame
US5696029A (en) * 1993-08-31 1997-12-09 Texas Instruments Incorporated Process for manufacturing a lead frame
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5696029A (en) * 1993-08-31 1997-12-09 Texas Instruments Incorporated Process for manufacturing a lead frame
US5606199A (en) * 1994-10-06 1997-02-25 Nec Corporation Resin-molded type semiconductor device with tape carrier connection between chip electrodes and inner leads of lead frame
US6303985B1 (en) * 1998-11-12 2001-10-16 Micron Technology, Inc. Semiconductor lead frame and package with stiffened mounting paddle

Similar Documents

Publication Publication Date Title
JPS61117858A (en) Semiconductor device
GB2422485A (en) IC die with rows of staggered I/O pads with each row having a different pad shape
JP2560805B2 (en) Semiconductor device
JPH04139866A (en) Semiconductor integrated circuit device
JPS62261144A (en) Semiconductor integrated circuit
JPH01144664A (en) Integrated circuit device for semiconductor memory
US5126828A (en) Wafer scale integration device
JPH05243472A (en) Semiconductor integrated circuit
JPS5948949A (en) Parts for hybrid integrated circuit
US5869884A (en) Semiconductor device having lead terminal on only one side of a package
JPS6089955A (en) Semiconductor device
JPH02215143A (en) Tab ic
JP2002353325A (en) Semiconductor device
JPH0119400Y2 (en)
JPS58182841A (en) Monolithic integrated circuit
JPH0138913Y2 (en)
JPH11340272A (en) Semiconductor integrated circuit and semiconductor integrated circuit device
JPS6278848A (en) Large scale semiconductor integrated circuit
JPH0297049A (en) Package device for integrated circuit use
JPS63137459A (en) Semiconductor device
JPS63237535A (en) Hybrid integrated circuit
JPS6127646A (en) Integrated circuit
JPS6286750A (en) Manufacture of semiconductor device
JPH02189956A (en) Package for semiconductor device
JPH05129472A (en) Surface-mounting semiconductor device