JPH0413799B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a Josephson storage circuit, and more particularly to a non-destructive read random access memory using the Josephson effect.

(Prior art and its problems) Gate circuits using Josephson junctions can be applied to high-speed logic circuits and high-speed memory circuits because of their high-speed switching characteristics and low power consumption characteristics. In a Josephson storage circuit, one or several magnetic flux quanta φ ₀ stored in a superconducting loop including Josephson elements serve as a storage medium. The stored information is stored by superconducting current and has the advantage that no energy is required for information retention.In order to speed up the storage circuit, the number of magnetic flux quanta stored in the storage loop is minimized. things are necessary. Furthermore, it is desirable to downsize the circuit in order to reduce wiring inductance. Miniaturization of circuits is also important from the viewpoint of improving process yield.

FIG. 10 is a diagram for explaining a conventional example of a Josephson memory circuit using a Josephson gate circuit. In the figure, reference numerals 71 and 72 denote Josephson gate circuits consisting of three and two Josephson junctions and inductances, respectively, and are called a three-junction interferometer gate and a two-junction interferometer gate, respectively. 73 and 74 are superconducting lines, 75 is a word line, 76 is a bit line, 77 is an auxiliary word line, 78 is a sense line, and 79 is a damping resistor for preventing oscillation. FIG. 11 is a diagram for explaining a two-junction interferometer gate, in which a is a circuit diagram and b is its threshold characteristic. FIG. 12 is a diagram for explaining a three-junction interferometer gate, where a is a circuit diagram and b is its threshold characteristic. In Figure 11a, 81,8
2 is Josephson junction, 83 is inductance,
84 is a gate current path, and 85 is an input line that is electromagnetically coupled to the inductance. In the two-junction interferometer gate of FIG. 11, the critical current values of Josephson junctions 81 and 82 are the same value I ₀
is set to In Figure 12 a, 91, 92,
Josephson junctions 94 and 95 have critical current values I ₀ , 2I ₀ , and I _{0 ,} respectively, and 93 have the same inductance value L.
96 is the gate current path, 9
7 and 98 are input lines that are electromagnetically coupled to the inductance. In the threshold characteristics shown in FIGS. 11b and 12b, the horizontal axis represents the input current, the vertical axis represents the gate current, and the shaded area indicates that the gate circuit is in a voltage state.

Write binary numbers “0” and “1” to this memory circuit,
For details on the read operation, please refer to the document IEEE Journal of Solid State Circuits.
State Circuits) Vol.SC-14(5) pp.794-796, so I will only describe the outline here.

To write a binary number “1”, use the word line 75,
A current is applied to the auxiliary word line 77 and bit line 76 in the direction of the arrow in FIG. Make it smooth and flow. After this, when the current in the bit line 76 and the auxiliary word line 77 is cut first, and then the current in the word line 75 is cut off, a clockwise circulating current will flow in the memory circuit. To write a binary 0, current is applied to the bit line 76 and auxiliary word line 77, and the three-junction interferometer gate 71 is switched to a voltage state.
The circulating current is extinguished. As described above, the presence or absence of a circulating current in the memory circuit is made to correspond to the binary numbers "0" and "1".

For reading, word line 75, sense line 7
Apply current to 8. In the memory circuit in which the "1" state is written, the current injected from the word line 75 is superimposed on the circulating current, so the two-junction interferometer gate 72 switches to a voltage state,
“1” state can be read. Since no circulating current is flowing in the memory circuit to which the "0" state is written, the interferometer gate 72 does not switch and the "0" state can be read.

This Josephson memory circuit uses an interferometer gate with high-speed switching characteristics, so it has advantages such as high-speed operation, no power required to retain written contents, and non-destructive readout. Motsu. However, since the present memory circuit is arranged such that the superconducting line 74 is electromagnetically coupled to the two-junction interferometer gate 72, it is difficult to reduce the inductance value of the superconducting line 74, and the storage information and It is difficult to reduce the number of magnetic flux quanta. This hinders speeding up. Also, in the junction interferometer gate 71 used for writing, the first
The product of the inductance value L of the inductances 94 and 95 shown in Figure 2a and Josephson junction I ₀ must be set to about the magnetic flux quantum φ ₀ (〓2.07 mA・PH),
Attempting to lower the critical current value I ₀ by increasing speed and reducing power consumption has the disadvantage that L increases and a large area is required on the integrated circuit chip. Furthermore, when the memory circuits are arranged in an array, there are memory circuits in a half-selected state. That is, during writing, there is a state in which a current flows through either the bit line 76 or the auxiliary word line 77, and during reading, there is a state in which either the current in the word line 75 or a circulating current flows. This means that the interferometer gates 71 and 72 operate as two-input AND gates, and the entire original operating margin of each interferometer gate cannot be used, resulting in a reduction in operating margin. is inviting. For example, in a 3-junction interferometer gate, L = 2.07PH, I ₀ =
Select 0.1mA, word line 75, bit line 76,
Assuming that the operating margins of the currents flowing through each of the auxiliary word lines 77 are equal, the operating margin for writing is approximately ±27%. (However, variations in each parameter during manufacturing were ignored.) Furthermore, as described above, when writing "1", the current flowing through the bit line 76 and the auxiliary word line 77 is set earlier than the current flowing through the word line 75. The need to ensure timing safety is a limitation on high-speed operation.

(Objective of the Invention) An object of the present invention is to eliminate such drawbacks and provide a non-destructive read/storage circuit that can achieve high speed and high integration.

(Structure of the Invention) According to the present invention, one end of the first superconducting line;
One end of the second superconducting line including the second Josephson junction is connected, the other ends of the first and second superconducting lines are connected to each other to form a loop B, and the first superconducting line of the loop B A connection point between the line and the second superconducting line is connected to one end of the third superconducting line, and the other end of the third superconducting line and one end of the fourth superconducting line including the first Josephson junction are connected. the other end of the fourth superconducting line and the other end of the first superconducting line are connected, and the first,
A loop A is formed of the third and fourth superconducting lines and the first Josephson junction, and a word line current inflow terminal is provided at the connection point of the third and fourth superconducting lines of loop A. A word line current outflow terminal is provided at the connection point between the fourth superconducting line and the first superconducting line, and a bit line is provided so as to cause electromagnetic coupling with the third and fourth superconducting lines. and a sense line including a gate circuit using a Josephson junction arranged to form an electromagnetic coupling with both the first and second superconducting lines or with the first superconducting line. A Josephson memory circuit, which connects one end of the first superconducting line and one end of a second superconducting line including a second Josephson junction, and Connect the other ends of the lines to form loop B, loop B
A connection point between the first superconducting line and the second superconducting line is connected to one end of the third superconducting line, and a fourth line including the other end of the third superconducting line and the first Josephson junction is connected. One end of the superconducting line is connected, and the other end of the fourth superconducting line and the other end of the first superconducting line are connected to form the first, third, and fourth superconducting lines and the first Josephson junction. Loop A consisting of and without, the third of loop A
A word line current inflow terminal is provided at the connection point between the superconducting line and the fourth superconducting line, and a word line current inflow terminal is provided at the connection point between the fourth superconducting line and the first superconducting line. Further, a word line current outflow terminal is provided at the second connection point, a bit line and a fifth superconducting line are arranged so as to cause electromagnetic coupling with the third and fourth superconducting lines, and The method is characterized by providing a sense line including a gate circuit using a Josephson junction arranged so as to cause electromagnetic coupling with both the first and second superconducting lines or with the first superconducting line. A Josephson memory circuit connects one end of the first superconducting line and one end of a second superconducting line including a second Josephson junction, and connects the other ends of the first and second superconducting lines to each other. to form loop B, connect the connection point of the first superconducting line and second superconducting line of loop B to one end of the third superconducting line, and connect the other end of the third superconducting line. and the first
One end of a fourth superconducting line including a Josephson junction of A loop A consisting of a conductive line and a first Josephson junction, a third superconducting line of loop A and a fourth
A word line current inflow terminal is provided at the connection point of the fourth superconducting line and the first superconducting line, and a word line current inflow terminal is provided at the connection point of the fourth superconducting line and the first superconducting line.
A word line current outflow terminal is provided at the connection point of the bit line, and a bit line is arranged so as to cause electromagnetic coupling with the third and fourth superconducting lines, and both of the first and second superconducting lines are connected to each other. or a gate circuit using a Josephson junction arranged to cause electromagnetic coupling with the first superconducting line and arranged to produce electromagnetic coupling with the fifth superconducting line,
A Josephson memory circuit characterized by providing a sense line connects one end of the first superconducting line and one end of a second superconducting line including a second Josephson junction, and The other ends of the two superconducting lines are connected to form loop B, and the first
The connection point between the superconducting line and the second superconducting line and the third
The other end of the third superconducting line and one end of the fourth superconducting line including the first Josephson junction are connected, and the other end of the fourth superconducting line and the fourth superconducting line including the first Josephson junction are connected. The other end of the first superconducting line is connected to form a loop A consisting of the first, third, and fourth superconducting lines and the first Josephson junction, and the third superconducting line of loop A and the fourth superconducting line are connected. A word line current inflow terminal is provided at the connection point of the superconducting line, and the fourth superconducting line and the first
A word line current outflow terminal is provided at the connection point of the superconducting line, and the bit line and the seventh superconducting line are arranged so as to cause electromagnetic coupling with the third and fourth superconducting lines, arranged so as to cause electromagnetic coupling with both the first and second superconducting lines or with the first superconducting line, and arranged so as to produce electromagnetic coupling with the eighth superconducting line; A Josephson memory circuit includes a gate circuit using a Josephson junction and is characterized in that it is provided with a sense line, and includes one end of a first superconducting line and a second superconducting line including a second Josephson junction. one end of the superconducting line, and the other ends of the first and second superconducting lines are connected to form a loop B, and the connecting point of the first superconducting line and the second superconducting line of loop B is connected to the third superconducting line. The other end of the third superconducting line and one end of the fourth superconducting line including the first Josephson junction are connected, and the other end of the fourth superconducting line and the fourth superconducting line including the first Josephson junction are connected. The other end of the first superconducting line is connected to form a loop A consisting of the first, third, and fourth superconducting lines and the first Josephson junction, and the third superconducting line of loop A and the fourth superconducting line are connected. A word line current inflow terminal is provided at the connection point of the superconducting line, a word line current inflow terminal is provided at the connection point of the fourth superconducting line and the first superconducting line, and the third and fourth The bit wire is arranged so as to cause electromagnetic coupling with the superconducting line, and the bit line is arranged so as to produce electromagnetic coupling with both the first and second superconducting lines or with the first superconducting line. ,
A Josephson memory circuit characterized in that a sense line is provided, including a gate circuit using a Josephson junction arranged to generate electromagnetic coupling with the bit line, and one end of the first superconducting line. , connect one end of the second superconducting line including the second Josephson junction, connect the other ends of the first and second superconducting lines to form loop B, and form loop B.
A connection point between the first superconducting line and the second superconducting line is connected to one end of the third superconducting line, and a fourth line including the other end of the third superconducting line and the first Josephson junction is connected. One end of the superconducting line is connected, and the other end of the fourth superconducting line and the other end of the first superconducting line are connected to form the first, third, and fourth superconducting lines and the first Josephson junction. Loop A consisting of and without, the third of loop A
An inflow terminal for the word line current is provided at the connection point between the superconducting line and the fourth superconducting line, and an outflow terminal for the word line current is provided at the connection point between the fourth superconducting line and the first superconducting line. a bit line and a ninth superconducting line are arranged so as to cause electromagnetic coupling with the third and fourth superconducting lines, a sense line including a gate circuit using a Josephson junction arranged to cause electromagnetic coupling with the first superconducting line, and arranged so as to produce electromagnetic coupling with the bit line or the fifth superconducting line; A Josephson memory circuit is obtained which is characterized in that it is provided with.

(Detailed Description of the Structure of the Invention) The present memory circuit constitutes a part that stores information by two loops A and B made of a Josephson junction and an inductance. When writing, current is passed through the word line and bit line to write binary numbers “1” and “0”.
information is given by changing the direction of the current. Also, when reading, current is passed through the word line, bit line, and sense line. Now, the number of magnetic flux quanta stored in each loop of A and B is n _A , n _B , and the state of magnetic flux in the memory circuit is expressed as ( n _A , n _B . Binary number "1")
The state of "0" corresponds to (0,0), and the state of "0" corresponds to (1,0). When reading (0,
The magnetic flux of loop B is changed from the state of (0) to (0,1), and the change is sensed by, for example, a two-junction interferometer gate. At this time, when the current in the word line and bit line is cut off, the line returns to (0,
In order to return to the state of (1, 0), the memory circuit returns to (1,
0), the parameters are determined so that the state does not change even if current is applied to the word line and bit line. Therefore, a random access memory capable of non-destructive reading can be realized.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing embodiments.

Embodiment 1 FIG. 1 is a diagram for explaining an embodiment of the first invention, and shows a circuit diagram of the invention. 1 and 2 are Josephson junctions with critical current values I ₁ and I ₂ respectively, 3, 4,
5 and 6 are the first, second, third, and fourth superconducting lines, respectively, and electrically have inductance values L ₁ , L ₂ ,
It can be expressed as the inductance of L ₃ and L ₄ . Reference numeral 7 denotes a readout gate, which is a two-junction interferometer gate and is electromagnetically coupled to the first and second superconducting lines 3 and 4. 8 is a bit line electromagnetically coupled to the third and fourth superconducting lines 5 and 6, through which a bit current _Ib flows; 9 is a word line through which a word current Iw flows; 10 is a sense current Is
It is a flowing sense line. 11 is a damping resistance that provides appropriate braking conditions. Josephson junction 1 and first, third, and fourth superconducting lines 3, 5, 6
loop A (which is a figure-8 loop in Figure 1), loop B consisting of Josephson junction 2, first and second superconducting lines 3 and 4, bit line 8, and word line. FIG. 2 shows the threshold characteristics of a memory cell composed of 9 and 9. The threshold curve of the memory loop consisting of loop A and loop B is derived by deriving the potential energy of loop A and loop B, and determining the applied current condition that provides the minimum value of the potential energy.
Specifically, a method well known in the art is used in which the minimum value is determined by numerically solving the simultaneous differential equations regarding the phase of the two Josephson junctions included in the potential energy equation. The number of magnetic flux quanta captured in loop A and loop B is included in the phase term in the potential energy equation as 2n _A π and 2n _B π. n _A , n _B
is an integer whose sign depends on which direction with respect to the loop the flux quantum is trapped.
Therefore, the threshold curves for (0, 0), (1, 0), and (0, 1) are calculated by using the values of n _A and n _B as the values in parentheses, respectively, and following the method described above. , which was derived. The result is a threshold curve of the same shape that has been shifted in parallel. The circulating current in loop A induced by the magnetic flux quantum stored in loop A is
It is equivalent to the current induced by Ib (a similar situation occurs even if an offset current is added to Ib), so
For N _A , the threshold curve shifts parallel to the Ib axis.
On the other hand, the circulating current in loop B induced by the magnetic flux quantum stored in loop B will not be in the same situation unless an offset current is added to both Ib and Iw, so the threshold curve for N _B is Move diagonally. At this time, the values of each parameter are L ₁ ; L ₂ ;
L ₃ ;L ₄ ;=1PH;7PH;4PH;5PH, _I1 ; _I2 ;=
The horizontal axis shows the bit current Ib and the vertical axis shows the word current Iw. Let the numbers of magnetic flux quanta stored in loop A and loop B be n _A , n _B , and the state of the magnetic flux quanta in the memory cell be expressed as (n _A , n _B ). However, the sign of n _A and n _B depends on the direction of the circulating current in loops A and B, and clockwise is assumed to be positive. 21,
22 and 23 are (0,0), (1,0), respectively
This is a threshold curve in the state of (0, 1). A direct current is constantly passed through the memory cell through the bit line 8. The operating point at that time is 24, and at this point it can be in either the (0, 0) or (1, 0) state. Now, in order to write the binary number "0" into this memory circuit, the magnetic flux quantum state of the memory cell is set to (1,
0). That is, a word current i _w is injected from the word line 9 into the selected memory cell. At the same time, a bit current i _b is applied from the bit line 8 in addition to the DC current. However, the sizes of i _{w and} i _b are |i _w1 |<i _w <|i _w2 | (|i _w1 |=1/2・|i _w2 | |i _b1 −i _b0 |<i _b <|i _b2 −i _b0 | ( _{| i b1 −i b0} |= ₁ /2・|i _b2 −i _{b0 |} When the magnetic flux state of this memory cell is (0, 0), the word current
By injecting i _w and bit current i _b , the operating point moves to 25 and enters the (1,0) threshold curve from the (0,0) threshold curve. Therefore, the magnetic flux state of this memory cell becomes (1, 0), and "0" is written. On the other hand, when the magnetic flux state of this memory cell is (1,0), the operating point moves from 24 to 25, but all points are within the threshold curve of (1,0), and the magnetic flux quantum There is no change in the status of. Subsequently, by cutting off the bit current i _b and the word current i _w , the operating point moves to 24, the state of the magnetic flux quantum at that time is maintained as (1, 0), and writing of "0" is completed.

Next, writing the binary number “1” is the “0” mentioned above.
In the explanation of writing, i _w , i _b are changed to −i _w , −i _b ,
Also, i _w1 , i _w2 , i _b1 , i _b2 , are replaced with i _w3 , i _w4 , i _b3 , i _b4 , operating point 25 is replaced with operating point 26, and (0,0) and (1,0) are By replacing them with each other, they can be explained in exactly the same way.

The threshold curve in Figure 2 shows three states; for example, (2,0),
There are also states such as (0, 2), and when they are calculated, it becomes clear that there are multiple stable points at the operating points 25 and 26 mentioned above. However, as a result of calculating the equipotential plane for the external drive current value corresponding to the movement path from operating point 24 to 25 or from 24 to 26, it is found that from the (0,0) state to (1,
From the (1,0) state of transition to the 0) state, the (0,
It has become clear that the probability of transition to state 0) is the highest. The value of the damping resistor 11 can be selected to ensure this transition.

For half-selected cells in the storage array, the bit current,
Only one of the word currents is applied, and the operating point moves to one of 28, 29, and 30 in FIG. That is, the operating point does not move outside the shaded area in FIG. 2, and the magnetic flux state does not change. Therefore, when the word current or bit current is cut off, it returns to the original stable state and becomes "0" or "1".
No new writing is performed.

Reading in the memory circuit of this embodiment is achieved by passing a current through the sense line 10 and reading out changes in the magnetic flux state of the loop B of the memory cell using the read gate 7. When a word current -i _w and a bit current i _b are respectively applied to the memory cell in the "1" state, the operating point shifts from 24 to 27 and a magnetic flux transition occurs. At this time, the sizes of i _w and i _b are set to |i _w3 |<i _w <|i _w4 | |i _b1 −i _b0 |<i _b <|i _b2 −i _b0 |.

Although there are multiple stable points at the operating point 27,
As a result of calculating the equipotential plane for the external drive current value corresponding to the transition path from operating point 24 to 27, the probability of transition from the (0, 0) state to the (0, 1) state is the highest. It became clear. In other words, the magnetic flux state of loop B has changed. The value of the damping resistor 11 can be selected to make this transition more reliable. When the memory cell is in the “0” state, that is, the (1,0) state,
Even if the word current and bit current are applied in the same way as in the "1" state and the operating point is moved to operating point 27, the threshold curve of the (1,0) state will not be exceeded.
(1,0) State does not change. Therefore, in the "1" state, the magnetic flux in the loop B changes, and in the "0" state, it does not change. This change in magnetic flux within loop B is read by a readout interferometer. Now, the phase difference of the order parameters of Josephson junction 2 is θ, the critical current value of Josephson junction is I ₁₂ , the current value injected into loop B is Ia,
Let the inductance values of superconducting wires 3 and 4 be La and Lb. In FIG. 1, the word current flowing through the word line 9 flows through the third superconducting line 5 and the fourth superconducting line 6.
It is divided into two parts. Further, the bit current flowing through the bit line 8 generates magnetically induced currents in the third superconducting line 5 and the fourth superconducting line 6. That is, part of the word current and the induced current due to the bit current are superimposed on the third superconducting line, and this superimposed current is the current injected into loop B.
That is, it flows into the connection point between the first superconducting line 3 and the second superconducting line 4 and branches there, one flowing through the first superconducting line 3 and the other flowing through the second superconducting line 4 and Josephson junction. 2, and then merges and flows out to the connection point between the Josephson junction 2 and the first superconducting line 3. This current is Ia. The following relationship holds between each parameter.

La・Ia=(La+Lb)I ₁₂ sinθ+φ ₀ /2πθ However, φ ₀ is a natural constant and has a value of 2.07mAPH.
In FIG. 1, loop B is composed of one Josephson junction 2 and a superconducting line. Since superconducting lines act as electrical inductance,
Loop B is a superconducting loop composed of Josephson junction and inductance, and can be thought of as an rfSQUID. The above equation can be derived in the same manner as the general equation for the phase of the Josephson junction of the rfSQUID and the current injected into the rfSQUID. FIG. 3a shows the relationship between Ia and θ. Also the third
Figure b shows the threshold characteristics of the two-junction interferometer 7, and the critical current values of the two junctions are each 0.1.
The value of the inductance magnetically coupled to the mA and 0.2 mA superconducting lines 5 and 6 is 3.45 PH. In the figure, the horizontal axis is the input magnetic flux φin, and the vertical axis is the sense current Is. Third
φin shown in figure b represents the magnetic flux input to the readout gate and is proportional to the magnitude of the magnetic flux trapped in loop B. Phase θ of Josephson junction
The relationship between and the magnetic flux φ captured in loop B is φ=
(φ ₀ /2)θ, so φin is proportional to θ. The operating points of the memory cell are operating points 24 (when in the (1, 0) state), 24 ((0,
0) state) 27 ((0,0) state), 27((1,
0) state), the phase of Josephson junction 2 is
They are in the states 31, 32, 33, and 34 shown in FIG. 3a. At this time, the magnetic fluxes generated in loop B are φ ₀ /2πθ ₁ , −φ ₀ /2πθ ₁ , −φ ₀ /2πθ2, φ ₀ /
2πθ ₃ , . (The phase difference value θ ₁ of Josephson junction 2,
The meanings of θ ₂ and θ ₃ are shown in FIG. 3a. )
Furthermore, the coupling coefficient between loop B and sense gate 7 is
0.5 and the magnitude of the sense current is set to i _s , the operating point of the two-junction interferometer 7 is as shown in FIG. 3b, corresponding to the operating points 31, 32, 33, and 34 in FIG. 3a. These are points 35, 36, 37, and 38. That is, in reading when the binary number is "1", the operating point of the two-junction interferometer 7 moves from 36 to 37 in FIG. Read out. In addition, when in the "0" state, the operating point of the two-junction interferometer simply moves from 35 to 38, remaining in the superconducting state, and "0" is read out. On the other hand, consider the case where the word line current and bit line current are cut off when reading is completed.
From the operating point 27 in the state of (0, 1) to the operating point 24,
When the operating point is moved, there are multiple stable points at the operating point 24, but as a result of calculating the equipotential plane for the external drive current value corresponding to the moving path from the operating point 27 to 24 (0, ) state to the (1,0) state has the highest probability. The value of the damping resistor 11 can be selected to ensure this transition.
Further, in the (1,0) state, there is no change in the (1,0) state even if the operating point moves from 27 to 24.
In this way, when reading is completed, the original state is restored, and non-destructive reading can be realized.

In this memory circuit, assuming that there are no manufacturing variations in parameters, the operating margin for the word current and bit current during writing is approximately ±33% as shown in Figures 2 and 3, and when reading, the operating margin for the word current and bit current is approximately ±33%. The operating margin for current and bit current is approximately ±33%, and the operating margin for sense current is approximately ±37%.
(However, the operating margin of the sense current is the word current,
This is the case when the current value of the bit current is fixed at the center value of the operating region.

As described above, by using the Josephson storage circuit of the present invention, a random access memory with non-destructive readout can be realized. The storage medium of this storage circuit is one magnetic flux quantum, and the speed of the circuit can be increased. Furthermore, compared to the conventional example, a three-junction interferometer gate for writing is not required, and the area of the chip becomes significantly smaller. Moreover, there is no need to take timing between the word current, bit current, sense current, etc. flowing for reading and writing, and extremely high-speed access is possible. Furthermore, as described above, it is possible to improve the operating margin compared to the conventional example. Therefore, the design and process tolerances become larger, making it suitable for higher density and higher integration.

Embodiment 2 FIG. 4 is a diagram for explaining an embodiment of the second invention. In this embodiment, the bit line 8 in the embodiment shown in FIG. 1 is replaced with a fifth superconducting line 12 and the bit line 8. In this embodiment, the direct current flowing through the bit line explained in the embodiment shown in FIG. 1 is injected through the fifth superconducting line 12. The other components of the fifth superconducting line 12 and bit line 8 shown in FIG. 4 are the same as those shown in FIG. Therefore, the first, second, third, and fourth superconducting lines 3, 4, 5, and 6, the Josephson junctions 1 and 2, the word line 9, the bit line 8, and the fifth
The threshold characteristics of the memory cell constituted by the superconducting line 12 are similar to those shown in FIG. A direct current is constantly applied to the fifth superconducting line 12. At that time, the operating point of this memory cell is at point 24 in FIG. Hereinafter, the operation of writing and reading binary numbers "1" and "0" will be the same as in the embodiment shown in FIG. Therefore, this embodiment has the same effect as the embodiment shown in FIG. Furthermore, as an advantage unique to this embodiment, since the DC current that is constantly flowing in this embodiment is passed independently of the bit line 8 for cell selection, the design of the decoder that selects the bit line is facilitated. .

Embodiment 3 FIG. 5 is a diagram for explaining an embodiment of the third invention. This embodiment uses the sixth gate which is electromagnetically coupled to the readout gate 7 in the embodiment shown in FIG.
In addition, a superconducting line 13 is added. The other components of the sixth superconducting line 13 shown in FIG. 5 are the same as those shown in FIG. 1. A direct current is constantly passed through the sixth superconducting line. Therefore, the operating point of the read gate 7 in FIG. 5 is shifted by the magnetic flux φ _DC induced by the direct current. The write and read operations of this embodiment are the same as those of the embodiment shown in FIG. 1, except that the operating point of the read gate 7 is shifted by φ _DC . FIG. 6 shows the threshold characteristics of the read gate of this embodiment and its operating point. The numbers in FIG. 6 have the same meaning as the numbers shown in FIG. 3b.
This embodiment has effects similar to those of the embodiment shown in FIG. Furthermore, as an effect unique to this embodiment, during readout, the operating point is shifted by the magnetic flux φ _DC induced by the DC current applied to the sixth superconducting line 13, as shown in FIG. current
This has the effect of widening the operating margin of Is.

Embodiment 4 FIG. 7 is a diagram for explaining an embodiment of the fourth invention. In this embodiment, the bit 8 in the embodiment shown in FIG. 15. Other components of the seventh and eighth superconducting lines 14, 15 and the bit line 8 shown in FIG.
Same as shown in the figure. In this embodiment, the DC current flowing through the bit line explained in the embodiment shown in FIG. I'll keep it. Therefore, the operating point of the read gate 7 in FIG. 7 is shifted by the magnetic flux φ _DC induced by the direct current. Consisting of the first, second, third, and fourth superconducting lines 3, 4, 5, and 6 of this embodiment, the Josephson junction 1 and 2 word lines 9, the bit line 8, and the seventh superconducting line 14. The threshold characteristics of the memory cells are similar to those shown in FIG. By constantly applying a direct current to the seventh superconducting line 14, the operating point of this memory cell is at point 24 in FIG.

Hereinafter, the write and read operations of this embodiment are the same as those of the embodiment shown in FIG. 1, except that the operating point of the read gate 7 is shifted by φ _DC .
FIG. 6 shows the threshold characteristics of the read gate of this embodiment and its operating point. The number in Figure 6 is number 3.
They have the same meaning as the numbers shown in Figure b. This embodiment has similar effects to the embodiment shown in FIG.

Furthermore, in this embodiment, since the DC current that is constantly passed is passed independently of the bit line 8 for cell selection, there is an effect that the design of the decoder for selecting the bit line is facilitated. In addition, as shown in FIG. 6, during readout, the operating point is shifted by the magnetic flux φ _DC induced by the DC current applied to the eighth superconducting line 15, and the operating margin of the sense current Is is expanded. There is.

Embodiment 5 FIG. 8 is a diagram for explaining an embodiment of the fifth invention. In this embodiment, the bit line 8 and the sixth superconducting line 13 in the embodiment shown in FIG. 5 are replaced with a common bit line 16. The other components of bit line 16 shown in FIG. 8 are the same as those shown in FIG. When a bit line current is applied to the bit line, the operating point of the read gate 7 shown in FIG. 8 is shifted by the magnetic flux φ _bit induced by the bit line current. The write and read operations of this embodiment are the same as those of the embodiment shown in FIG. 1, except that the operating point of the read gate 7 is shifted by φ _bit . The threshold characteristic of the read gate of this embodiment and its operating point can be expressed by replacing φ _DC shown in FIG. 6 with φ _bit . This embodiment has the same effects as the embodiment shown in FIG. Furthermore, as shown in FIG. 6, an effect unique to this embodiment is that during reading, the operating point is shifted by the magnetic flux φ _bit induced by the bit line current applied to the bit line 16.
This has the effect of widening the operating margin of the sense current Is. Furthermore, compared to the embodiment shown in FIG.
The number of lines can be reduced by one, which has the effect of simplifying the circuit.

Embodiment 6 FIG. 9 is a diagram for explaining an embodiment of the sixth invention. In this embodiment, the seventh superconducting line 14 and the eighth superconducting line 15 shown in FIG. 7 are replaced with a common ninth superconducting line 17. The other components of the ninth superconducting line 17 and bit line 8 shown in FIG. 7 are the same as those shown in FIG. In this embodiment, the direct current flowing through the bit line explained in the embodiment shown in FIG. 1 is injected through the ninth superconducting line. Therefore, the operating point of the read gate 7 in FIG. 9 is shifted by the magnetic flux φ _DC induced by the direct current. The first, second, third and fourth superconducting lines 3, 4, 5, 6 and Josephson junction 1,
The threshold characteristic of the memory cell composed of the word line 9, the bit line 8, and the fifth superconducting line 12 is as follows.
It is similar to FIG. By constantly applying a direct current to the fifth superconducting line 12, the operating point of this memory cell is at point 24 in FIG. The write and read operations of this embodiment are the same as those of the embodiment shown in FIG. 1, except that the operating point of the read gate 7 is shifted by φ _DC . FIG. 6 shows the threshold characteristics of the read gate of this embodiment and its operating point. The numbers in FIG. 6 have the same meaning as the numbers shown in FIG. 3b. This embodiment has the same effects as the embodiment shown in FIG. Furthermore, in this embodiment, since the DC current that is constantly passed is passed independently of the bit line 8 for cell selection, there is an effect that the design of the decoder for selecting the bit line is facilitated.
In addition, as shown in FIG. 6, the operating point is shifted by the magnetic flux φ _DC induced by the DC current applied to the ninth superconducting line 17 during readout, and the sense current
This has the effect of widening the operating margin of Is. Furthermore, compared to the embodiment shown in FIG. 7, the number of superconducting lines is reduced and the circuit can be simplified.

(Effects of the Invention) A non-destructive read random access memory can be realized by the Josephson storage circuit of the present invention. The storage medium of this storage circuit is one magnetic flux quantum, and the speed of the circuit can be increased. Furthermore, compared to the conventional example, a three-junction interferometer gate for writing is unnecessary, and the area occupied by the chip is significantly reduced. Furthermore, extremely high-speed access is possible without the need to take timing between word current, bit current, sense current, etc., which are applied for reading and writing. Furthermore, as described above, it is possible to improve the operating margin compared to the conventional example. As a result, design and process tolerances become greater, leading to higher density and higher integration.

[Brief explanation of drawings]

1, 4, 5, 7, 8, and 9 show first, second, third, fourth, fifth, and sixth embodiments of Josephson memory circuits, respectively. FIG. 2 is a circuit diagram for explanation. FIG. 2 shows the threshold characteristics of the memory cell of the present invention, and FIG. 3a shows the phase of the Josephson junction 2 shown in FIG. It shows the relationship between the current injected into the third
FIG. b shows the threshold characteristics of the reading gate, both of which are for explaining the first embodiment.
FIG. 6 shows the threshold characteristics of the read gate of the third embodiment. FIG. 10 is a circuit diagram for explaining a conventional example of the present invention, and FIGS. 11a and 12a are a two-junction interferometer gate for reading and a three-junction interferometer gate for writing in the conventional example. The circuit diagram of the metagate, and FIGS. 11b and 12b show its threshold characteristics. In the figure, 1, 2, 81, 82, 91, 9
2,93...Josephson junction, 3,4,5,
6, 12, 13, 14, 15, 17...1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th
superconducting line, 7... readout gate, 8,1
6, 76...bit line, 9,75...word line,
77... Auxiliary word line, 10, 78... Sense line, 11, 79... Damping resistor, 84, 96
...Gate current path, 85,97,98...Input line, 83,94,95...Inductance, 2
4, 25, 26, 27, 28, 29, 30, 3
1, 32, 33, 34, 35, 36, 37, 38
. . . Operating points, 21, 22, 23 . . . Threshold curves are shown.

Claims (1)

[Claims] 1. One end of the first superconducting line and one end of the second superconducting line including the second Josephson junction are connected, and the other ends of the first and second superconducting lines are connected to each other. to form loop B, connect the connection point of the first superconducting line and second superconducting line of loop B to one end of the third superconducting line, and connect the other end of the third superconducting line. and the first
One end of a fourth superconducting line including a Josephson junction of A loop A consisting of a conductive line and a first Josephson junction, a third superconducting line of loop A and a fourth
An inflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, an outflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, and A bit wire is arranged so as to cause electromagnetic coupling with the superconducting line of No. 4, and arranged so as to produce electromagnetic coupling with both the first and second superconducting lines or with the first superconducting line. A Josephson memory circuit characterized in that it includes a gate circuit using a Josephson junction and is provided with a sense line. 2 Connect one end of the first superconducting line and one end of the second superconducting line including the second Josephson junction, and connect the other ends of the first and second superconducting lines to form loop B. , connect the connection point of the first superconducting line and the second superconducting line of loop B to one end of the third superconducting line, and connect the other end of the third superconducting line to the first
One end of a fourth superconducting line including a Josephson junction of A loop A consisting of a conductive line and a first Josephson junction, a third superconducting line of loop A and a fourth
An inflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, an outflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, and A bit line and a fifth superconducting line are arranged so as to generate electromagnetic coupling with the superconducting line of No. 1. A Josephson memory circuit characterized by having a sense line including a gate circuit using a Josephson junction arranged so as to cause an optical coupling. 3 includes one end of the first superconducting line and a second Josephson junction. One end of the second superconducting line is connected, and the other ends of the first and second superconducting lines are connected to form a loop B, and the first superconducting line and the second superconducting line of loop B are connected to each other. The connection point of the line is connected to one end of the third superconducting line, the other end of the third superconducting line is connected to one end of the fourth superconducting line including the first Josephson junction, and the fourth superconducting line is connected. The other end of the conductive line and the other end of the first superconducting line are connected to form a loop A consisting of the first, third, and fourth superconducting lines and the first Josephson junction, and a third An inflow terminal for word line current is provided at the connection point between the superconducting line and the fourth superconducting line, and an outflow terminal for word line current is provided at the connection point between the fourth superconducting line and the first superconducting line. ,
A bit line is arranged so as to cause electromagnetic coupling with the third and fourth superconducting lines, and
or the first superconducting line, and a sixth superconducting line, using A Josephson memory circuit characterized by including a gate circuit and a sense line. 4 Connect one end of the first superconducting line and one end of the second superconducting line including the second Josephson junction, and connect the other ends of the first and second superconducting lines to form loop B. , connect the connection point of the first superconducting line and the second superconducting line of loop B to one end of the third superconducting line, and connect the other end of the third superconducting line to the first
One end of a fourth superconducting line including a Josephson junction of A loop A consisting of a conductive line and a first Josephson junction, a third superconducting line of loop A and a fourth
An inflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, an outflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, and A bit line and a seventh superconducting line are arranged so as to generate electromagnetic coupling with the superconducting line of No. A Josephson memory circuit characterized in that a sense line is provided, including a gate circuit using a Josephson junction, which is arranged to cause magnetic coupling and electromagnetic coupling with an eighth superconducting line. . 5 Connect one end of the first superconducting line and one end of the second superconducting line including the second Josephson junction, and connect the other ends of the first and second superconducting lines to form loop B. , connect the connection point of the first superconducting line and the second superconducting line of loop B to one end of the third superconducting line, and connect the other end of the third superconducting line to the first
One end of a fourth superconducting line including a Josephson junction of A loop A consisting of a conductive line and a first Josephson junction, a third superconducting line of loop A and a fourth
An inflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, an outflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, and A bit wire is arranged so as to cause electromagnetic coupling with the superconducting line of No. 4, and arranged so as to produce electromagnetic coupling with both the first and second superconducting lines or with the first superconducting line. and a gate circuit using a Josephson junction arranged to cause electromagnetic coupling with the bit line.
Josephson memory circuit characterized by providing a sense line. 6 Connect one end of the first superconducting line and one end of the second superconducting line including the second Josephson junction, and connect the other ends of the first and second superconducting lines to form loop B. , connect the connection point of the first superconducting line and the second superconducting line of loop B to one end of the third superconducting line, and connect the other end of the third superconducting line to the first
One end of a fourth superconducting line including a Josephson junction of A loop A consisting of a conductive line and a first Josephson junction, a third superconducting line of loop A and a fourth
An inflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, an outflow terminal for word line current is provided at the connection point of the fourth superconducting line and the first superconducting line, and A bit line and a ninth superconducting line are arranged so as to cause electromagnetic coupling with the superconducting line of No. the bit line or the fifth
A Josephson memory circuit characterized by having a sense line including a gate circuit using a Josephson junction arranged so as to cause electromagnetic coupling with a superconducting line.