JPH0368478B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding a loop-type superconducting memory cell, the purpose of this invention is to expand the operating margin during reading, and the present invention includes a memory loop that holds written data in the loop as a circulating current; A first OR gate that switches when a predetermined bias current is supplied when a circulating current is flowing in the memory loop, a first OR gate that switches in response to the switch of the sense gate, and a predetermined read address signal. and an AND gate that switches in response to the switching of both the first and second OR gates.

[Industrial application field]

The present invention relates to a superconducting memory cell, and particularly to a loop-type memory cell, and relates to a superconducting memory cell intended to expand the operating margin during reading.

In general, superconductors have excellent features that normal conductors do not have, such as magnetic flux quantization, where the interlinkage magnetic flux in a loop formed by a superconductor can only take discrete values. When two superconductors are brought very close to each other, a switching phenomenon between a superconducting state and a normal conducting state is observed due to a tunneling phenomenon unique to superconductors called the Josephson effect.

Recently, various ultra-high-speed devices have been attempted using the features of superconductors, and superconducting memory cells are one of them.

[Conventional technology]

FIG. 2 is a diagram showing an example of a conventional superconducting memory cell. The loop-type memory cell 1 includes a storage loop 2 having a first branch path 2a and a second branch path 2b, and a write gate inserted into the first branch path 2a and to which a write address line 3 is magnetically coupled. 4, and a sense gate 6 to which the second branch path 2b and the read address line 5 are magnetically coupled.

In addition, the abbreviation D in the figure is write data (logic "1" or "0"), W _A is a write address signal that specifies loop type memory cell 1, and R _A is a read address signal that specifies loop type memory cell 1. , R _E are read enable signals input in the read mode. In addition, the symbol X in the figure indicates Josephson junctions J ₁ to _{J 5} , and each junction has an appropriate value of critical current Ic (which is the threshold when the junction switches from a superconducting state to a normal conducting state). The current flowing through the junction) is selected.

In such a configuration, data writing and reading operations are performed as follows.

Writing Assuming that the loop memory cell 1 is in the "0" state, let us consider the case where "1" is written to the loop memory cell 1. First, when loop memory cell 1 is selected from a large number of loop memory cells by inputting W _A , almost simultaneously D
(Write data, in this case "1") is input. When W _A and D are input, W _A is transmitted from the write address line 3 to the write gate 4 via magnetic coupling, so the rise is slightly slower than the rise of D. Therefore, during the input transient period of W _A and D, J ₁ to _{J 3} of the write gate 4 are in a superconducting state, and D is connected to the first branch path 2 a according to the magnetic flux preservation side of the superconducting loop shown in the following equation. and second branch road 2
An equal current (I _D /2, where I _D is the current flowing due to D) flows through both of b.

La × Ia = Lb × Ib ... However, La, Lb: the first branch road 2a and the second
Reactance Ia, Ib of each branch path 2b: Current flowing through the first branch path 2a and second branch path 2b (I _D /2) When W _A rises sufficiently, the write gate 4 is affected by this W _A. When the induced current flows, J ₁ to J ₃ are switched and the first branch path 2a is opened.

Therefore, Ia flowing through the first branch 2a flows to the second branch 2b, and Ia+Ib (that is, I _D ) flows into the second branch 2b.

As a result, the current flowing through the first branch path 2a becomes 0.
Then, the power to the write gate 4 is cut off, and J ₁ to _{J 3} of the write gate 4 return to the superconducting state again. As a result, the first branch road 2a and the second
The branch path 2b constitutes a superconducting loop, and a circulating current I _cir expressed by the following equation flows within this loop.

I _cir = 2Φo/LI _D /2... However, Φo: Magnetic flux quantum L: La+Lb If D is set to 0 in this state, I _cir becomes I _cir 2Φo/L... and I _D is removed, The remaining I _cir is permanently contained within storage loop 2. That is, the state in which I _cir is flowing in the storage loop 2 corresponds to logic "1".

On the other hand, when writing logic “0”, W _A
D is not input because the write data is "0". If the previous state is "0", nothing happens and the inside of the storage loop 2 remains "0". If the previous state is “1”
I _cir is playing. J ₁ to _{J 3} are switched by I _cir and W _A , so that I _cir quickly becomes 0.
becomes. Therefore, storage loop 2 is “0”
becomes.

Readout In the readout operation, first, J ₄ of sense gate 6,
It starts by supplying bias current IB by _RE to _J5 . Next, when R _A for selecting this loop-type memory cell 1 is input, a control current I _CT due to the input of R _A flows through J ₄ and J ₅ of the sense gates 6 . Now, J ₄ and J ₅ of sense gate 6 have (IB+
I _CT ) is flowing, but it is not switched because it is still below the critical current Ic. At this time, if "1" is written in storage loop 2 (I _cir is flowing), I _cir is added to J ₄ and J ₅ of sense gate 6 in addition to the above I _B and I _CT . An information current Id accompanying this also flows, and J ₄ and J ₅ are switched to a voltage state due to these (IB+I _CT +Id). In this way, the switch operation of the sense gate 6 corresponds to the write information of the storage loop 2 (with switch operation → “1”,
By monitoring this switch operation, the written information can be read.

[Problem to be solved by the invention]

However, in such a conventional superconducting memory cell, IB and _ICT are connected to the sense gate 6.
When setting the critical current Ic of J 4 and J 5, it was necessary to set the critical current Ic of J ₄ and J ₅ . exceeds (IB+I _CT ), and (IB+I _CT +Id)
should be below, but in fact, IB,
It is extremely difficult to precisely set the sizes of I _CT and Id, and some variation in Ic is also unavoidable, so the problem is that it is not possible to have a wide operating margin during readout. The point was hot.

The present invention was made in view of these problems, and the current flowing into the sense gate is divided into a bias current (corresponding to the conventional IB) and an information current (corresponding to the conventional Id).
The purpose of the present invention is to provide a superconducting memory cell with an expanded operating margin during reading.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a memory loop that holds written data as a circulating current in the loop, and a predetermined bias current is supplied when the circulating current is flowing in the memory loop. and a first sense gate that switches in response to the switching of the sense gate.
an OR gate, a second OR gate that switches according to a predetermined read address signal, and an AND gate that switches in response when the first and second OR gates both switch;
It is configured with the following.

[Effect]

In the present invention, a state in which a circulating current is flowing in the memory loop (information "1" is written)
When a predetermined bias current is supplied to the sense gate, the sense gate transitions to a switch state, and as a result, information "1" is read out.

In other words, the current flowing into the sense gate is two: a predetermined bias current (corresponding to the conventional IB) and an information current accompanying the circulating current (corresponding to the conventional Id), and the current flowing into the sense gate is different from the conventional three currents (IB, I _CT , Since the error associated with setting the above two current values is smaller than Id), the design margin for the critical current Ic (threshold value of Josephson junction) increases, and the operating margin can be expanded.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a diagram showing an embodiment of a superconducting memory cell according to the present invention, and is an example applied to a superconducting memory device composed of a large number of loop-type memory cells.

In FIG. 1, 10 is one memory cell among many. The memory cell 10 is inserted into a storage loop (memory loop) 11 having a first branch path 11a and a second branch path 11b, and a write address line 12 is magnetically coupled to the first branch path 11a. write gate 13
and a first read gate (sense gate) 14 to which the second branch path 11b is magnetically coupled;
OR gate 15, second OR gate 16 and
MTVL (modified
(variable threshold logic) unit cell 18,
A second read gate 19 is configured.

Note that MTVL unit cells usually have two ORs.
It is composed of a gate and one AND gate,
In the case of the present invention, each of the two OR gates has one input, and essentially functions as a switch. In addition, the abbreviation DATA in the figure is write data (logic "1" or "0") input as necessary at the timing of clock φ ₃ , and W _ADRS designates this memory cell 10 as necessary at the time of writing. Write address signal (input at timing φ ₃ ), R _ADRS is a read address signal (input at timing φ ₁ ) that specifies this memory cell 10 as necessary during read operation, R _BIAS is input at timing φ during read operation. The read bias input at timing _{φ 2} and R _ENBLE are read enable signals input at timing φ ₂ during the read operation.
The clocks φ ₁ to _{φ 3} are timed in the order of φ ₁ , φ ₂ , and φ ₃ , and the phase difference between each clock is 120°.

The symbol X in the figure indicates Josephson junctions J ₁₀ to J ₁₈ , and an appropriate critical current is selected for each junction. In addition, R ₁₀ to _{R 16} are resistances, L ₁₀ , L ₁₀ ′ to _{L 14} ,
L ₁₄ ′ represents a reactance for magnetic coupling in which pairs of the same subscripts are arranged.

Next, the effect will be explained.

In the above configuration, for example, write gate 1
3 and Josephson junction in sense gate 14
The critical current of J ₁₀ ~ _{J 14} , J ₁₀ → 0.1mA, J ₁₁ →
0.2mA, _J12 →0.1mA, _J13 →0.1mA, _J14 →0.1mA
And the circulating current I _cir in the storage loop 11 is
Write and read operations when I _cir →0.2mA will be explained.

Write operation Now, when I _cir in the storage loop 11 is 0, that is, when “0” is written, DATA _and W _ADRS are
When inputted, first, almost equal currents flow through the first branch path 11a and the second branch path 11b due to DATA. Then W _ADRS is from L ₁₀ , L ₁₁
L ₁₀ ′, L ₁₁ ′ are magnetically transmitted, thereby switching J ₁₀ to _{J 12} of the write gate 13 into a voltage state, and the current flowing through the first branch 11a becomes
It is added to the current in the second branch path 11b, and the current in the first branch path 11a becomes zero. As a result, J ₁₀ to J ₁₂ of the write gate 13 return to the superconducting state again, and the first branch path 11a and the second branch path 11
A superconducting loop consisting of b is formed, and a circulating current I _cir (0.2 mA in this example) flows within this loop. This I _cir continues to flow almost forever even after DATA and W _ADRS are set to 0, and remains "1" in the storage loop 11. Note that writing "0" is realized by the same operation as that described in the conventional example.

Read When information “1” is written in the storage loop 11, first, when R _ADRS is applied to the second OR gate 16 at the timing of clock φ ₁ , the second OR gate 16 is applied to the second OR gate 16 at the timing of clock φ ₂ . The gate is switched by R _BIAS applied at the timing of , and the output current I ₁ is supplied to the AND gate 17. At this time, the AND gate 17 maintains the superconducting state only with _I1 , and keeps the potential at point A at OV.

On the other hand, the R _BIAS input at the timing of the clock φ ₂ is also supplied to the first read gate 14 , and the first read gate 14 receives a bias current IB due to this R _BIAS and a bias current IB in the storage loop 11 . The sum of the information current Id generated in L ₁₂ ′ by the circulating current I _cir flows.

Now, if the value of (IB+Id) exceeds the critical current of J ₁₃ and J ₁₄ , J ₁₃ and J ₁₄ are switched, and the potential at point B on the output side of the first read gate 14 increases.

Here, the current flowing through the first read gate 14 is equal to IB when reading information "1".
Id, and when no information is written to the storage loop 11 (i.e., information “0”)
, only IB is available. Therefore, information “1”
and “0”, “1” → Id + IB, “0” respectively
→ IB, and the values of the critical currents of J ₁₃ and J ₁₄ are determined by these Id
It is only necessary to set it appropriately so that it falls between +IB and IB. This means that compared to the conventional critical current setting that considers three currents, IB, I _CT , and Id, only two currents (IB, Id) need to be considered, so L ₁₂ , L ₁₂ ′, J ₁₃ , _J14, etc., in the design of each part of the superconducting circuit, and as a result, the operating margin can be expanded and stable circuit operation can be obtained.

Returning to the explanation of the read operation, the first read gate 14 is switched by IB+Id,
When the potential at point B increases, the first
OR gate 15 switches and AND gate 17
supplies an output current I ₂ to Since I ₁ is already supplied to the AND gate 17, the AND gate 17
is switched by supplying the sum of I ₁ and I ₂ (I ₂ +I ₂ ). As a result, the potential at point A rises, and a control current flows from L ₁₃ and L ₁₄ to L ₁₃ ′ and L ₁₄ ′. As a result, the second readout gate 19
J ₁₇ and J ₁₈ are switched in response to write information “1” in the storage loop 11, and by monitoring this switch state, information in the memory cell 10 is read out.

In this way, in this embodiment, the current flowing through the first read gate 14 is divided into two currents, IB and Id (however,
When reading "1"), it is possible to provide some margin in the design of the first read gate 14 (for example, the threshold values of J ₁₃ and J ₁₄ ). In other words, the operating margin during reading can be expanded, and the circuit operation can be stabilized.

〔Effect of the invention〕

According to the present invention, since the current flowing into the sense gate is divided into two, the bias current and the information current, the operating margin during reading can be expanded, and a superconducting memory cell with stable circuit operation can be realized. be able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a superconducting memory cell according to the present invention, and FIG. 2 is a block diagram showing a conventional superconducting memory cell. 11...Storage loop (memory loop),
14...first read gate (sense gate),
15...first OR gate, 16...second OR gate
Gate, 17...AND gate.

Claims (1)

[Claims] 1. A memory loop that holds written data as a circulating current in the loop, and a sense gate that switches when a predetermined bias current is supplied while the circulating current is flowing in the memory loop. a first OR gate that switches in response to the switch of the sense gate; a second OR gate that switches in response to a predetermined read address signal; and both the first and second OR gates switch. Then, the AND that switches in response to this
A superconducting memory cell characterized by comprising a gate and.