JPS6196826A - Dc drive type josephson frequency divider - Google Patents

Abstract

PURPOSE:To attain high speed operation by combining two DC drive type Josephson FF circuits, giving each output signal as other input signal and giving it to each element so as to bring the Josephson element in order thereby setting a bias current. CONSTITUTION:A frequency divider is formed by connecting CS circuits CS1, CS2 in cascade. Asymmetrical two-junction magnetic quantum interference elements are used for the Josephson elements 71-74. Each element has three control lines 85, 86 and 87. Bias currents Ib1, Ib2 are given respectively to wires 78, 79, and an input current IN flows to a wire 77. Since a gate current is constant, the operating point exists on a curve A and the operating point on the A is decided by the sum of currents flowing to the said control line. For example, currents +IN, Ib1, I2A are inputted to an element Q1A. In deciding the bias currents Ib1, Ib2, the input of each element changes according to the change in the current IN. That is, output powers I1A, I1B, I2A, I2B show one period change against two periods of change in the input current IN.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a frequency divider formed by combining DC-driven Josephson logic circuits formed on a semiconductor substrate, and in particular,
The present invention relates to a DC-driven Josephson frequency divider whose operating speed is increased so that it is suitable for application to Josephson computers.

[Background of the invention]

The prior art and its problems will be explained with reference to FIGS. 1 to 7. Conventionally, various types of frequency dividers using semiconductor integrated circuits have been proposed. For example, Charles A.
Lietchi, “A GaAs MS IWor.
d Generator Operating
at 5Gbist/5DataRa
te”IEEEEJ, o
f Microwave Thechnics and
Theory, Vol, MTT-30.

Na 7 , ], 980 , P , 988 discloses a frequency divider consisting of Ga As field effect transistors operating at 6.5 GHz. Power consumption is estimated to be approximately 100 mW per bit. Such a frequency divider is constructed by combining logic gates. Since Josephson logic circuits can also form logic gates, they can also form frequency dividers. In particular, Josephson logic circuits are characterized by ultra-high-speed operation that exceeds conventional semiconductor devices, so it is expected that frequency dividers with unprecedented high-speed operation will be constructed. In fact, H,C.

Jones, “Self-Activating
Toggle” I B MTechnic
al Disclosure Bulletin,
Vol, 2 3.

Nα9. Feb. 1981 discloses a frequency divider using a Josephson logic circuit. In the above document, an AC driven circuit is used. In the AC drive method, the current waveform flowing through the Josephson logic circuit becomes a rectangular wave as shown in FIG. In FIG. 1, a region 1 in which the current is kept at a flat value is a valid period, and a logic operation proceeds during this period.

Region 2 is an invalid period during which the polarity of the driving power source is switched, and no logic operation proceeds. In an AC drive circuit, if the region 2 is made too small, a malfunction called a punch-through phenomenon will occur.

This phenomenon is explained by E, P, ) (Arris, “P
unchIl, through 1nJosephson
Logic Devices”IEEET
rans.

on Magnetics, Vol, MA
G-17, Nn1.

Jan, 1981. It is disclosed in PP603-606. For example, in order to suppress the probability of malfunction to 10-22, region 2 must be 200 ps (picoseconds) or more. Then, the upper limit of the movable frequency of the frequency divider is 5 GHz (
(considering the positive and negative halves of FIG. 1 as independent periods), and the performance is lower than that of the conventional semiconductor circuit configuration. One solution to address these difficulties is to use DC driven circuits. Various types of DC-driven Josephson logic gates are known, but a typical one is the Curren
t, Sjeering C1rcuit (hereinafter referred to as C
S circuit) and Hybrid Unlatch
ng F lip F 1apL logic E le
ment (hereinafter abbreviated as HUFFLE). These are S, M, Faris, Loop'fE
Recorder for Josephson Me
mory Arrays" I E E E
Journal of 5solid 5tate
C1rcuits.

Vol, SC-14, Nn4. August, 197
9゜pp, 699-70'7 and A, F, He
bard et al., “A DC-Powered Jose
phson Flip Flop” I E E
E Trans, on Magnetics
, Vol, MAG15, Nα1. These are logic gates disclosed in Jan.

The operation of the C8 circuit and HUFFLE will be explained below using diagrams. The C8 circuit and HUFFLE are basically implanted with a combination of two Josephson elements, an inductance, and a resistance. One Josephson element is a Josephson magnetic quantum interferometer consisting of a single Josephson junction or a plurality of Josephson junctions. It is assumed that the threshold characteristic of this Josephson element is as shown in FIG.

In FIG. 2, 11 represents a threshold curve, 12 represents a Josephson device, and ■ represents a gate current.

I, is a control current fIil is a bias current.

In the C8 circuit and HUFFLE, the operating point of the two Josephson elements that constitute them is the alternating input current fI.
B is the bias current t, I2 is the current flowing through the nine-side loop and the right lunip, respectively, and Ll and L2 are inductances. The ratio of Ll and L2 is about 1:3 or more apart. This is for initial settings. Bias electrician. 1°1112 (i.e. operating point 13 in Figure 2)
．． 14), the crowding characteristics shown in FIG. 4 will be shown. Figure 4(a) shows the input current Iih
, (b) is the output current 11. of each loop. I2 is shown. Note that in the O8 circuit, it is common to provide a damping resistor in parallel with the Josephson element, but this is omitted in FIG. Similarly, the circuit configuration and input/output characteristics of HUFFLE are shown in FIGS. 5 and 6.

L is load inductance, RL is load resistance I IoT
m is the output current, and the other symbols are the same as in FIG. The bias current 8 is set so that operating points 13 and 14 in FIG. 2 are achieved in this case as well.

The C8 circuit and HUFFLE perform majority logic operation.・
Therefore, by appropriately setting the magnitude of the bias current and appropriately setting the input direction, □R, AND, N
Any function of OR or NAND can be implemented in C8 circuit or HUF.
This can be realized by FLE.

Here, FIG. 7 shows an example of a circuit diagram of a frequency divider constructed from an existing semiconductor circuit. This is SEM-ICONDU
CTRDATA BOOK (TTL) HI TAC
H.I., 1980. P, 90i: Disclosure 0. This is what is being done. Consists of two NAND AND elements, two NOR elements, and input signal CLK.
In contrast, the Q output or the d output is divided into half the frequency. Each gate in Figure 7 is connected to a C8 circuit or HU.
If FFLE is used instead, a frequency divider circuit can be obtained, but there are limits to the degree of integration and speed of the circuit. The operating speed of the 68 circuit and HUFFLE depends on the magnitude of the damping resistance and load resistance, but it mainly depends on the load inductance (third
L1+L2 in the diagram. It depends on L) in FIG. And unless these inductances are set to a certain value or higher, gate operation will become unstable. For example, as a Josephson element, the critical current density is l O00A/cnf
, the half cycle in which the output reaches 90% of the steady value from the time when it exceeds the 2-junction value consisting of two Josephson junctions with a junction area of 5 μmφ must be approximately 90 ps or more, HUFFLE.
When using the
．． 7 GHz, and a frequency divider operating at 6.5 GHz, also made of conventional GaAs field effect transistors (the aforementioned Charles AL 1ejc
It is possible to achieve a performance that is lower than that of the literature published by H.I.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems in the prior art and to provide a frequency divider that uses a DC-driven Josephson integrated circuit and can operate at higher speed than existing frequency dividers made of semiconductor elements. It is in.

[Summary of the invention]

In order to achieve such an object, the present invention has at least two DC-driven Josephson flip-flop circuits each having two Josephson elements formed by one or two Josephson junctions, and each output signal is An embodiment of a frequency divider is described below, in which each Josephson element is connected to provide another input signal, and a supply path is combined with each Josephson element so that one of the four Josephson elements is in a voltage state in turn. First, the most basic frequency divider using an O5 circuit as a flip-flop circuit will be explained with reference to FIG.

This frequency divider has a configuration in which two C8 circuits C3I and C82 are connected in series, as shown in FIG. 8(a). 8th
In figure (a), +71.72, 73°74 is CS circuit C5
The Josephson element is a component of I, C52, and here an asymmetric two-junction magnetic quantum interferometer is used. @ They are each driven by a flow source 76. Each Josephson element has three control lines. The wiring 78 applies a bias current Ib2 to the cables 71 and 72, and the wiring 79 applies a bias current Ib2 to the cables 73 and 74. The wiring 77 is a wiring through which the input current IN flows. The structure of the Josephson element is shown in FIG. 8(b). This device has a Josephson junction J1. A closed circuit is formed by J2 and an inductance connecting these.

, three control lines 85, 86, and 87 are magnetically inductance vertical axis, and gate current 1. It is.

Since the gate current is constant at 11, the operating point exists on A.

The operating point on A is determined by the sum of the currents flowing through the control lines 85, 86, and 87. Due to the asymmetric structure of the device, the shape of threshold curve 88 is asymmetric. The reason for this asymmetry is that the slope ΔI of the threshold curve 88 at B
This is to obtain a stable operating region by making g/ΔIo steep and suppressing fluctuations in the threshold current I Tic due to fluctuations in the gate current 1 due to expected noise, crosstalk, and the like. Since it is asymmetrical, the part where the gate current is injected is marked with C. The magnitude of the damping resistance Ro is determined by the junction capacitance of Jl and J2 being c and T, and the element 7
1.72 and an inductance of 8o, where LT is the total inductance of the closed loop. The input current IN has an offset of 1/2 and a peak-to-peak amplitude of 2, which is a sine wave or a similar waveform.

The operation of this frequency divider will be explained with reference to FIG. 8(e).

Prior to that, the name of each element and the name of the output current were
Define as shown in figure (d). That is, elements 71, 72° 73
．． 74 respectively Q1. A I Q L B + Q
2 A! Q 2 B, and each output current is 11
1°rzat rzAt rza. 1A of element
3 currents +IN and IゎLtI2A are input to. Similarly, O18 has +IN=I-1,I2B.

02 k has -IN, 1%, □, ■18, Q 2 B
-IN, I, 2. I and A are input. Figure 8 (c
), the bias currents I5° and Ik
2 is determined, the input to each element changes as shown in FIG. 8(e) as the input current IN changes. In the same figure,
The length of the arrow indicates the magnitude of the current, and the direction of the arrow indicates the direction of the current. First, as the initial layer state, the input current IN is zero, the gate current flows to Qze, which is gradually raised from zero to a steady value, and 0.11B in 11A*I2A.
Medium I211 Medium I, =I. At this time, in the 91 column of Figure 8(e), the current shown by the size of each arrow flows beside each control, and the total current flows as shown by the arrow in the 96 total column below. . As a result, the sum of the control line currents exceeds the threshold ITlc only in Q 2 A, but since no gate current flows through Q 2 A from the beginning, there is no change in the state of the output current. When the input current IN is increased from 0 to I in this state, the current shown in column 92 flows through each control line of each element, resulting in a total current as shown in column 97. As a result, the sum of the control line currents only at C4 becomes the threshold value. exceed. At this point, Qllll has a gate current ■
, is flowing, so C18 switches from the zero voltage state to the voltage state. Then, almost all of the gate current that had been flowing to Q 1 B flows to Q 1 k, and Io, jI
, r, 11so. When the gate currents of Q and 11 approach zero, Q and n return to the zero voltage state again. Q
Since the sum of the control line currents of LA is 1 or less, Q i
k is still in a zero voltage state. IiA from 0 to I
Due to the increase in voltage, it remains in the zero voltage state.

That is, a steady state is reached when 11 houses - 9118 wholesale 09 I2 A ki 0° I2B wholesale I are reached.

Next, when IN advances by half a cycle and reaches 0, the current shown in column 93 will flow through the control line of each element, so Q 2
B causes a switch from zero voltage state to voltage state to zero voltage state, and the output current changes. Similarly, in column 94, Ql
A switches Q2A in the 95 column.

That is, for two periods of input current IN, output current i'tA
+ l1RI I2&? I211 shows a change of one cycle, and a frequency division operation is established.

Now, there is still room for improvement in the performance of the frequency divider shown in Figure 8.
There is. Let us consider the operation of the CS circuit again. Figure 9 (
a) shows the specific structure of the C8 circuit, and FIG. 9(b) shows its C8 circuit.
8 shows the relationship between the magnitude of the load inductance L1 or L2 and the time τ. The switching time τ is
From the time when the input crosses the threshold of the element to the time when the output reaches 90% of the steady value, the Josephson junction uses a lead alloy electrode and a 5 μm diameter Josephson junction with a critical current density of 1000 mA/ant. Realized. In this C8 circuit, when the load inductance L2 increases, the switching time τ increases as shown in the figure. If L2 becomes too small, the O8 circuit will not operate, but
To aim for high-speed operation, L2 should be small.

On the other hand, in the circuit shown in FIG. 8, the inductance corresponding to L2 is 80.8 in terms of load inductance.
1 has to become huge. Here again, the element has a critical Josephson current of 0.2 mA and a junction capacitance of 0.8.
A numerical discussion will be given using an example using a two-junction magnetic quantum interferometer composed of two pF Josephson junctions. It is now assumed that all wiring has a width of 5 μm. The film thicknesses of each electrode and insulating film constituting the Josephson element are those of known examples J and H.

G reiner et al.”Fabricat, ion Pr
ocess for J osephson I
ntegrat, ed C1rcuijs” I
BMJ-Res, Develop
Vol, 24. Na2. March, 1980
Follow. Then, if Ll is not used as it cannot be lower than approximately 50 pH, and if only Step 2 is used, all the inductance caused by coupling with the next stage element will be L2.
added to the side, Ll is minimized 1.12,113,1
Reference numeral 14 denotes a Josephson element, and a two-junction magnetic quantum interferometer shown in FIG. 8(b) is used.

ill and 112 are driven by a current source 115 with gate current 1, and 113 and 114 are driven by a current source 116, respectively. Li2, 119゜120.121 is a bias current ■bx+ ■b for elements 111 to 114, respectively.
□+Ib□1Ib4 is the current line. 117
is the wiring through which the input current IN flows. The difference from the circuit in FIG. 8(a) is that the output lines of Josephson elements 112 and 114 are directly connected to ground, while the output lines of Josephson element 111 are connected to element 1 through elements 113 and 114.
The output line No. 13 is connected to ground via elements 111 and 112. In other words, element 111
, 113 are much longer and have a larger inductance than the output lines of elements 112 and 114, so the output lines shown in Fig. 8 (
Inductances 80.81 and 82.83 shown in a) are unnecessary.

Threshold curve 12 whose bias conditions are shown in FIG. 10(b)
2 will be explained. The threshold value of the device at gate current T5 is set to 1. Then, it is. The input current IN is a sinusoidal or similar waveform current with an offset of I/2 and a peak-to-peak amplitude of 1. The operation of this frequency divider is shown in Figure 10 (C
).

First, assume that the input current IN is 0 as an initial state, and the gate current is gradually raised from 0 to a steady value .

In that state and thereafter, control suI to each element every time IN advances by 1/2 period! The states of the A input are shown in [131 to 135] in the same way as in FIG. 8(e).

In this case as well, the output current I L A for two input cycles
112A changes by one cycle, and normal frequency dividing operation is performed. According to the embodiment in FIG. 10, the method in FIG. 8(a) is as follows:
It must be such that the load inductance present on the input line of the next stage divider is minimized. This load inductance can be divided into contributions from the coupling portion with the next-stage frequency divider element and the wiring connecting them. now,
Assuming that the wiring has a line width of 5 μm, the critical Josephson current of the device is 0.2 mA, and the junction capacitance is 0.8.
Two pH Josephson junctions and about 0.8p connecting them
Considering the use of an asymmetric two-junction magnetic quantum interferometer configured with an inductance of
, H. Greiner, et al.), the inductance at the junction with the element is 1.
The wiring inductance of approximately 20 pH1 for each element is approximately 1 pH per 10 μm of wiring length. In normal wiring methods, the contribution of the former tends to be large. Therefore, in order to reduce the load inductance, the number of coupled load elements must be minimized. If two C3 circuits constitute one frequency dividing circuit, and two or more stages can be connected,
This shows how to connect a bit frequency divider. 1 frequency divider to 3 C
It consists of eight circuits, two of which are for driving the next stage.

Three CS circuits 141, 142, 14 forming a frequency divider
The number of load elements in No. 3 is 4, 2, and 4, respectively, which is an improvement. In addition, giving top priority to increasing the speed of the first frequency divider will lead to improving the operating speed of multi-stage frequency dividers, so we changed the wiring method of the first frequency divider and the second frequency divider. The length of the wiring, which is a load on the device, is kept to a minimum. Each C8 circuit 141, 142, 14 in the diagram
The load inductance of 3,144,145°146 is approximately 126°90.125,155,95,155 respectively.
It becomes pH.

However, the load on the C8 circuit 146 was determined assuming that the third all-frequency divider is also connected in the same type as the second frequency divider.

147 is an input line for the divided signal current IN.

1480.1490,1500,1510°1520.
1530 is bias current I51゜■1□* Ibme
Ib4v Iゎ591ゎ, is the input line, 15
40. ．． 1550, 1560°, I g=0.3
mA, Ibtx~1.4 is subject to the same limitations as in equation (3), each having an example, and giving a sinusoidal current with a peak-to-peak amplitude of 0.3 mA. FIG. 11(b) shows simulation results when the input frequency is 16 GHz. rl, r2. ryo.

I4 are CS circuits 141, 142, 143°14, respectively.
4 output current. It can be seen that normal operation is performed and performance superior to the conventional example (authored by Charles AL 1e11.chi, cited above) is obtained.

The operation of the frequency divider configured by combining two or three C8 circuits has been explained above, but as a flip-flop circuit,
A similar frequency divider can also be constructed using UFFLE. The basic 1-bit configuration is shown in FIG. 12(a). In the figure, 151, 152°, 153, and 154 are elements that are the constituent elements of HUFFLE, and here an asymmetric two-junction magnetic quantum interferometer is used. . Element tSt has a current control line for gate current Ig. The wiring 1160 applies bias current to the elements 151 and 153, and the wiring 161 applies bias current to the elements 152 and 154, respectively. 159 is a person 166.167
is magnetically coupled to the inductance L. The threshold curve of this device is shown in FIG. 12(C). The reason why the threshold curve is asymmetric is the same as that of the C8 circuit. In FIG. 12(b), R is a load resistance, and if the quasi-particle tunnel resistance of Josephson junction J1 or J2 is R, then RL is set to approximately. If R is made too large, a hang-up phenomenon occurs and the switching operation is inhibited. on the other hand,
When RL is made smaller, switching becomes slower. 12th
The method for setting the bias currents 1 bl and Ib2 is also shown in FIG. The threshold value of the device at gate current Ig is ■. , and t-2 (ro,<r.2), the current has a sine wave or a waveform similar to the sine wave with a two-peak amplitude of about 2I.

The operation of this frequency divider will be explained with reference to FIG. 12(e). Prior to the explanation, the names of each element and output current are determined as shown in FIG. 12(d). + I N, r b for 1A of the element
x and +I2 are input. Similarly, Q t g has +IN, 1. □, -I2, but -IN, I for Q 2 k
,,, -I 1 is -IN for Q2Ii.

11□, +11 is input. When the bias currents ■, , 1 and Ib2 are determined as shown in Figure 12(c), the input to each element changes as the input current IN changes as shown in Figure 12(e).
). First, it is assumed that the input IN is zero as an initial state and the gate current (2) is gradually raised to a steady value. Next, the bias current 1bL is temporarily set to I T
Increase the IC to 2 or more and return to the original value as the primary. Then Sakuko Q1A
and Q 2 A becomes a voltage state, and ■1 + Ig, I2
It becomes shi+rg. In this state, when IN is raised from zero to {circle around (2)}, currents as shown by the size of each arrow in the column 181 in FIG. 12(e) flow through the control lines of each element, but are not total. When the input IN advances for the next half cycle and reaches 1, the control line current shown in column 182 flows, Q2B switches, and Q z A returns to the zero voltage state as a reaction. Similarly, in the column 183, Q z A switches at the time of Q engineering 8°184, and in the column 185, the original event returns again and QIA switches.

That is, for two periods of IN, the output is 11. I2 shows a change of one cycle, and a frequency division operation is established.

Now, let's consider the operation of HUFFLE again.

FIG. 13 shows the switching time τ for a particular structure of HUFFLE and its load inductance. In this case, too, the time is defined as the time from the time when the input crosses the threshold value of the element to the time when the output reaches 90% of the steady value.

In the same figure, 191 and 192 are two-junction magnetic quantum interferometers constructed of two Josephson junctions with critical Josephson currents of 0 and 2 mA and a junction capacitance of 0.8 pF. This HUFFLE increases as the load inductance L increases as shown in the figure. If L becomes too small, consider configuring the operating layer and container of H, UFFLE. In that case, the wiring method is HUF that constitutes the leading pin 1-.
It must be such that the inductance of the FLE is minimized. Based on the same discussion as in the case of the C8 circuit, the wiring method as shown in FIG. 14 (,'a) is adopted. One frequency divider is composed of three HUFFLEs, one of which is used for driving the next stage. Furthermore, the wiring methods for the first frequency divider and the second frequency divider are different. Under the same assumption as in the case of the O8 circuit, each HUFFLE201°202.203,
The inductances of 204, 205, and 206 are approximately 130.75, 125°165.105, and 125PH, respectively. However, the load of 206 was determined assuming that the third frequency divider is also connected in the same type as the second frequency divider. 207 is a frequency-divided signal IN (7) input line, and 208, 209, 21
0°211 is the bias current Ibl+Ib□+Ibyo.

11.4 input line. 212,213,214゜2
15.216, 217, 218, 219, 220°22
1.222 and 223 are current sources that supply gate currents that drive each HUFFLE, respectively.

The bias conditions will be explained with reference to the above-mentioned FIG. 12(c). I rw: 2-0, 9 mA, 1. r
T, knee 11i3+Ib4 are both set to 0.8 mA.

Input: Input IN is peak-to-peak 1 with no offset
A sinusoidal current with an amplitude of 0.5 mA is assumed.

FIG. 114(b) shows simulation results when the input frequency is 6 GHz. In the figure ■□, ■2+” 37■
4 is HUFFLE201,202°203.2 respectively
04 output current. It can be seen that normal operation is occurring.

The structure and operation of a frequency divider that combines two or three O8 circuits and HUFFLEs has been described above. All of these systems employ a combination of two flip-flops that operate on tarock signals shifted by half a period. Other types of frequency dividers use short pulses within the switching time of a flip-flop. In this method, it is necessary to generate short timing pulses in synchronization with the input, so it cannot follow inputs with very high frequencies. However, apart from the pulse generation circuit, it is basically possible to divide the frequency into 1/4 using two flip-flops, so it may have functional advantages. In the embodiment shown below, FIG. 15 of the above-mentioned document also shows the structure and operation of a 174 frequency divider formed by combining a pulse generation circuit and two C8 circuits. FIG. 15(a) is a circuit configuration diagram. In the same figure, 231, 232, 233, 234 are shown in Figure 8 (
The elements shown in b) constitute C8 circuits 239 and 240. 235 and 236 are current sources that supply gate current 1, 237 and 238 are wirings that provide bias current 5□1Ib2, and 241 and 242 are two-junction magnetic quantum interferometers whose structure is shown in Fig. 15(b). be. These 241 and 24
2 are connected by an inductance L of 400 pH to form a closed circuit. JP is a Josephson junction with a critical current of 0.2 rnA and a junction capacitance of 0.8 pH, and R is a resistance of 1Ω. 246 is the wiring through which the input current IN flows, 244.24
5 is a wiring for supplying bias current II, □TIb4, 241 to 246 and JP.

R forms a pulse generating circuit 250 as a whole.

This pulse generating circuit is described in U.S. Patent Specification No. 4.144,4.
No. 65 (1979), 257 is the element 231.
~234 threshold curve, curve 258 in FIG. 15(d)
indicates the threshold curves of the elements 241 and 242, and the first
Bias conditions are shown in Figures 5(c) and 5(d). The amplitude of the pulse generated by the pulse generation circuit 250 is I
, (2-0,2mA). It must be in Figure 15(c). If I g = 0.3 mA, t,
, > 0.9 mA, so I i, , = 0.8 mA.

rk, □=0.5mA. On the other hand, it must be as shown in FIG. 15(d). I cx = 0, 6 mA
Then, I TNc=1-0, 9 mA, so -I
b m = 0.75 mA.

Iba=1.05mA.

The frequency division operation of the circuit of FIG. 15(a) will be explained with reference to FIG. 15(f). Prior to that, the names of each element and output current are determined as shown in FIG. 15(e). -1 for element Q I A
2 and I, 1 and + (current pulse) are input. Similarly, Q 1 II has 10T2 and □ and + (current pulse), and -Q2A has +I and 1. □ and + (current pulse) are Q
-11 and digit, □ and + (current pulse) are input to 2B. Each time a current pulse arrives, the input of each element is
It changes as shown by the arrow in Figure 5 ([). First, assume that the gate current Icc is gradually raised from zero to a steady value without applying a current pulse as an initial state. Due to the inductance of the wiring, ■ is almost a Q-factor. and Q2B
The flow becomes I and yi 2. On the other hand, the pulse generation circuit also has a gate current ■. Gradually raise the value from the atmosphere to the steady value. Next, when a pulse-like input with a height of Ib4 1-b3 is applied to the input IN, the pulse generation circuit 250 is connected to the C8 circuit 239, 2 via the Josephson junction JI) and the resistor R.
40 with very short width current pulses. At this time,
The inputs other than the current pulse for each element should be like 261. Only Q2u switches due to the arrival of the current pulse, and the state changes as shown in column 262. Similarly, I
When N human power is injected, Q 1 DI Q 2 k
IQsA switches back to its original state. Actually I
b3) + peak-to-peak amplitude is C1b4 I
All you have to do is add the sine wave current b3). Then part 4
Output 11 or ■2 indicates a change of one cycle with respect to the cycle. That is, the frequency division operation by 174 is established. FIG. 16 shows simulation results when a sinusoidal current with an offset of 0.15 rnΔ, a peak-to-peak amplitude of 0.3 mA, and a frequency of 2.5 GHz is applied as the input IN. In the figure, 1 (Vll) is the current flowing through the inductance L in the pulse generation circuit 250, and I (V12) is the current flowing through the O8 circuit 239, 240 through the Josephson junction JP and the resistor R.
The current pulse supplied to I(V2+) is I, −I
1. I (V22) is 1111 (VB2) is Ig r
2. I (V32) represents ■2, respectively.

Now, a similar 1/4 frequency divider circuit can be constructed by using lUFFLE instead of the C8 circuit. This is the first
This will be explained with reference to FIG. FIG. 17(a) shows a circuit configuration diagram. In the figure, 271 to 274 are elements shown in FIG. 12(b), which constitute IUFFLEs 281 and 282.

275 to 278 are current sources that supply the gate electrode 1°;
79 and 280 are bias currents Ib1. The wiring 250 for providing +Ib□ is the pulse generating circuit shown in FIG. 15(a). FIG. 17(b) must show the threshold open lines (283) and bias conditions of the elements 271-274. I g = 0, r for 3 m A
b 1 = I b z = 0', 5 mA. The frequency division operation of the circuit in FIG. 17(a) is shown in FIG. 17(d).

The names of each element and output current will be defined and explained as shown in FIG. 17(C). Element Q x A+ rQ 1u IQ
2 AQ2.3, in addition to the current pulses generated by the pulse generating circuit 250, I 2 + I k31. −
I 2+Ib□, -d, +Ik, 1, 11+I, □ are input. Each time a current pulse arrives, the force applied to each element changes as shown by the arrow in FIG. 17(d). First, assume that the gate current Iff is gradually raised from zero to a steady value without applying a current pulse as an initial state. here 15
□ temporarily■. Do the above and switch Q, A, Q2A3. At this time, the human power of each element is as shown in column 291, and only 02B is switched by the arrival of the current pulse, and the state becomes as shown in column 292. Similarly, each time a current pulse continues to arrive, Q1a+Q2ArQ□ switches and returns to the original state. That is, the output I□+Iz shows a change of one cycle for four cycles of the input IN.

That is, 1/4 cycle operation is established. No offset as input IN, peak-to-peak amplitude is 0,
FIG. 18 shows simulation results when a sinusoidal current of 3 mA and a frequency of 2-5 GHz is applied. Curve I (Vll) in the figure is the current flowing through the inductance L in the pulse generation circuit 250, I (V12) is the current flowing through the Josephson junction JP, the HUFFLE281 through the resistor R,
282, I(V21) represents the output I□, and f(V3]) represents the output ■2.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to provide a frequency divider that is composed of a Josephson logic circuit and operates at a frequency of 16 GHz, and in that case, the power consumption per one bit is reduced by the power supply resistor network. 10-15 including power consumption
It is approximately μW, and the input current required for operation is extremely small at a peak value of 0.1 to 0.3 mA, resulting in faster speeds, lower power consumption, and higher sensitivity ( can be realized.

[Brief explanation of drawings]

Figure 1 is a diagram showing the power supply current waveform used in a conventional AC-driven Josephson circuit, Figure 2 is a threshold open diagram of a Josephson element, Figure 3 is a configuration diagram of a C3 circuit, and Figure 4 is O8
An explanatory diagram of the operation of the circuit, Fig. 5 is a configuration diagram of the HUFFLE logic gate, Fig. 6 is an explanatory diagram of the operation of the HUFFLE logic gate, and Fig. 7i7I is an example of a frequency divider constructed using conventional semiconductor technology. Figures 8 to 18 are explanatory diagrams of embodiments of the present invention. Figure 8 is a frequency divider using an O8 circuit and an explanatory diagram of its operation. Figure 9 is a characteristic diagram of the O8 circuit. Figure 10. is a frequency divider based on an improved C8 circuit and an explanation diagram of its operation, Part 1
Figure 1 is a 2-bit O8 frequency divider connection and operation explanation diagram, Figure 12 is a frequency divider using HUFFLE and its operation explanation, and Figure 13 is the characteristics of HUFFLE. figure,
Fig. 14 is a diagram showing the connection and operation of a 2-bit HUFFLE frequency divider, Fig. 15 is a diagram showing a 1/4 frequency divider using a CS circuit and an explanation of its operation, and Fig. 16 is a diagram showing an example of its operation. 17th
The figure is an explanatory diagram of a 1/4 frequency divider using HUFFLE and its operation, and FIG. 18 is a diagram showing an example of its operation. 71.72,73,74,111,112゜113.1
14,151,152,153°154...Josephson element consisting of a two-junction magnetic quantum interferometer 75.76.115. ] 16,1540°1550.
15CiO, t570. [580°1590+15
5+ 156,157,158+212~223...
・Current source 77.117, 147, 1 that provides gate current
59,207 Human force line 78.79,1480,149
0,1500゜1.510,1520,1530,16
0,161°208-241...Bias current line 141-146,239,240-CS flip-flop 20 1-206. 281. 282...
) I U F F L E flip-flop 250...Current pulse generation circuit draft, 8-Group (6L) (C) Figure 2 (cl) Figure q (9°R...) Le C = 16PF ( 72nd (d) (C) Figure 72 (FSE +I3 Δ I2 o I. J）
/ left figure Ce) Fig. 72 ki r-f 乇sJ ORD (l V?2) Φ (l Vm め 77 figure (/:2) CI)nq lyx No. 770 (C) No. 1. ? Figure closed (4Lsl Wl (Vul) + 1 (V21) M H (V/2) 01 (Vlυ

Claims (6)

[Claims] (1) At least two DC-driven Josephson flip-flop circuits each formed by combining two Josephson elements formed by one or two Josephson junctions with a load inductance and a load resistance are connected in cascade. A DC-driven Josephson frequency divider, characterized in that the frequency divider obtains an output signal having a frequency obtained by dividing the frequency of an input signal. (2) The DC-driven Josephson flip-flop circuit uses current steering (Current S
hybrid unlatching
) The DC-driven Josephson frequency divider according to claim 1, which is a DC-driven Josephson flip-flop circuit using a flip-flop logic element. (3) Three of the DC-driven Josephson flip-flop circuits are connected in cascade, the first and second flip-flop circuits constitute a frequency dividing circuit for one bit, and the third flip-flop circuit is The DC-driven Josephson frequency divider according to claim 1, wherein the DC-driven Josephson frequency divider is used as a DC-driven buffer gate for driving the next bit. (4) A large number of the DC-driven Josephson flip-flop circuits are connected in series to form a set of three, and the frequency is divided by 1 bit between the first and second flip-flop circuits in each set. The circuit is configured, the third flip-flop circuit is used as a DC drive buffer gate for driving the next bit, and the relative placement of the flip-flop circuit in the first bit and the relative placement of the flip-flop circuits in the next bit and below are determined. 2. The DC-driven Josephson frequency divider according to claim 1, wherein the load inductance of each flip-flop circuit constituting the first bit is reduced by changing the first bit. (5) A pulse signal from a DC-driven Josephson pulse generation circuit is used as an input signal to a frequency divider composed of two DC-driven Josephson flip-flop circuits. A DC-driven Josephson frequency divider according to range 1. (6) The DC-driven Josephson flip-flop circuit according to claim 5, characterized in that a current steering circuit or a hybrid unlatching flip-flop logic element is used as the DC-driven Josephson flip-flop circuit. Son frequency divider.