JPS6387697A - Josephson memory - Google Patents

Abstract

PURPOSE:To improve the degree of integration by selecting one memory cell with the first and second control signals and controlling the magnetic flux quantum state of this memory cell. CONSTITUTION:An offset current Ioff is always supplied to a memory cell 6, and the memory cell 6 is set to one of two quantum states P and Q. Negative currents -IX and -IY in opposite directions of control currents IX and IY are supplied to set the memory cell 6 to the first quantum state P in case of write of data '0' to the memory cell 6, and positive control currents +IX and +IY are supplied to the memory cell 6 to set it to the second quantum state Q in case of write of data '1'. In case of read of the memory cell 6, either polarity is selected as polarities of control currents IX and IY and they are supplied to the memory cell 6 to read it. Thus, peripheral circuits are simplified and the degree of integration is improved.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a memory circuit using a Josephson device, in which a memory cell is configured from a -junction quantum interference device and two control signal lines magnetically coupled to the device. When this memory cell undergoes a magnetic flux quantum transition due to a control signal, the pulse voltage generated across the Josephson element causes a current to flow through the sense gate, which is separate from the memory cell, to read out and overturn, thereby increasing the number of constituent elements of the memory cell. The number of required lines such as bit lines, word lines, data lines, sense lines, etc. can also be reduced, and the number of integrated circuits can be improved.

[Industrial application field]

The present invention relates to a Josephson memory, and particularly to the structure of its memory cells and sense gates.

Josephson memory is one of the integrated circuits that takes advantage of the ultra-high switching time of Josephson elements. A gate structure is required.

[Conventional technology]

An example of a circuit of a main part of a conventional Josephson memory is not shown in FIG. 6 (final diagram). In the figure, Josephson element J+,
The 3-junction a-son interference element consisting of J2 and J3 and the inductance loop constitutes a write gate, and for the superconducting loop 1 including this 3-junction quantum interference element,
A sense gate consisting of Josephson chords J4 and J5 is magnetically coupled. Further, the three-junction quantum interference device is magnetically coupled to two control signal lines 2 and 3.

During a write operation, in a state where the signal D1 is applied to the superconducting loop 1 as a bias current, the control signal line 2
When control current x 1 and Yl are given to and 3, respectively, 3
The junction quantum interference device switches to a voltage state, and a persistent current Ic1r flowing along the superconducting loop 1 is induced, causing Ic
1r is taken in (for example, data "1" is taken in.) 1° On the other hand, in the state where the signal D1 is not received, the 3-junction 1
When switching the child interference element, the persistent current I. ir disappears (data "0" is written). At the time of reading, by applying the signals D1 and Sl, the persistent current I is generated by the sense gate. IR is read out.

FIG. 6 shows the circuit configuration of one memory cell of a conventional Josephson memory. A large number of these memory cells are arranged in a matrix, and control signal lines 2 and 3 are connected in the X direction (horizontal direction), respectively. It is wired in the Y direction (vertical direction) and is used to selectively cover one memory cell. Also, signal D
The terminal 4 to which 1 is applied is wired in the Y direction. Furthermore, the sense gates are wired in the X direction, and writing and reading are performed using these four lines.

-5= (Problem that Akira tries to solve) In the conventional Josephson memory, one memory cell has a circuit configuration as shown in Figure 6, and each memory cell requires four wires, which increases the number of wires. In addition, since each memory cell has a sense gate, the number of memory cell components is large, and the influence of variations in the components is large, the overall size of the memory is large, and the peripheral circuitry is complicated. However, since a persistent current with a smaller value is read out by current control, there are problems in that the operating margin is small, the yield is poor, and the degree of integration cannot be increased.

The present invention was created in view of the above points, and an object of the present invention is to provide a Josephson memory that can realize a high degree of integration.

[Means for Solving the Problems] The Josephson memory of the present invention includes a single-junction quantum interference device and a plurality of first and second control signal lines magnetically coupled to the single-junction quantum interference device arranged in a matrix. A sense gate including a Josephson element connected in series with both terminals of a one-junction quantum interference system f in each memory cell arranged in the vertical or horizontal direction. In this configuration, first control signal lines in each memory cell are commonly connected, and second control signal lines in each memory cell arranged in the vertical direction are commonly connected.

[Effect]

The first and second control signals sent to the first and second control signal lines select one memory cell among a large number of memory cells arranged in a matrix, and
The magnetic flux quantum state of the memory cell is controlled.

The memory cell is in one of the first and second quantum states, and depending on the polarity of the first and second control signals,
The sewing thread is controlled to one of these two states. As a result, information is written 11 times.

On the other hand, as the first and second control lI signals, control currents with polarities that control the memory cells to one of the two quantum states set in advance are generated, and these are applied to each memory cell. By sequentially applying the magnetic flux, the memory cells in the predetermined quantum state retain the same quantum state, while the memory cells not in the predetermined quantum state undergo a magnetic flux quantum transition to the predetermined quantum state.

A memory cell in which this magnetic flux quantum transition has occurred generates a voltage pulse, which is applied as a current pulse to the sense gate and read out. In this way, information is read out depending on the presence or absence of current pulses.

The memory cell consists of a single junction quantum interference device and two control signal lines, and does not have 11 sense gates as in the conventional case, but has a configuration in which the sense gate is shared by the memory cells arranged vertically or horizontally. can do. Furthermore, the first control signal lines of each memory cell arranged in the horizontal direction,
Since the second control signal lines of the memory cells arranged in the Tjwi and Tjwi directions are commonly connected to each other, the number of required lines can be reduced.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of the main part of the present invention. In the figure, reference numeral 6 denotes a memory cell, which includes a one-junction quantum interference device consisting of one Josephson element 7 and an inductance through 18, and a first control blind line 9 and a first control blind line 9 magnetically coupled to an inductance loop 8, respectively. 2 control signal lines 10.

11 is a sense gate, which is a Josephson element 12.1
It consists of a 3-junction quantum interference device including 3 and 14, and an offset current I between both terminals of the 1-junction quantum interference device in the memory cell 6. They are magnetically coupled and connected in series via a signal line 15 for H.

Further, the sense gate 11 is supplied with a bias current Is. As will be described later, one sense gate 11 is provided for a plurality of memory buildings arranged in one direction.

The operation of this memory cell 6 and sense gate 11 will be explained with reference to FIG. FIG. 2 shows the movement of the quantum state (movement of the operating point) of the memory cell 6, the vertical axis shows the internal magnetic flux Φi of the inductance loop 8, and the horizontal axis shows the control current IX supplied to the memory cell 6. , IY, offset current I. ff is shown.

Offset current I, which is a direct current. ff is memory cell 6
is constantly supplied to the memory cell 6, which causes the memory cell 6 to
One of the two quantum states indicated by P and Q in the figure is achieved. Now, the memory cell 6 is in the first state indicated by P in FIG.
Assuming that the memory cell 6 is in the quantum state of
It transitions to the second quantum state indicated by Q in the figure.

When controlled currents I× and ly are applied to the memory cell 6 in the first quantum state in the direction opposite to that shown in FIG.
The memory cell 6 remains in the first quantum state. When the memory cell 6 is in the second parlor state, the control currents I× and IY are caused to flow in the directions shown in FIG. 2, and by flowing IY and Iv in the opposite direction to that in FIG. 1, it is possible to transition to the first quantum state shown by P in FIG. 2.

Therefore, when writing data "o" to the memory cell 6, for example, the control currents Ix and IY are set to negative currents = lx, -IY in the opposite direction to those in FIG. - When writing the register “1”, positive control current +I
X, +IY may be applied to the memory cell 6 to set it in the second quantum state.

Next, reading of the memory cell 6 is performed using the control main stream Ix and Iv.
This is done by predetermining the polarity of the signal to either one and supplying it to the memory cell 6. For example, when negative control currents -■× and -IY are applied to the memory cell 6, the magnetic flux quantum transition does not occur when the memory cell 6 is in the first quantum state indicated by P in FIG. 2 as described above. However, when in the second suspender state indicated by Q, magnetic flux quantum transition occurs. At this time, a voltage pulse corresponding to one magnetic flux quantum expressed by Φo-fVdt is generated across the memory cell 6, and the current pulse resulting from this is added to the offlet current 'off, which controls the sense gate 11 shown in FIG. line 15
, which switches the sense gate 11 to the voltage state.

Therefore, the data stored in the memory cell 6 can be determined depending on whether the sense gate 11 switches or not.

FIG. 3 shows an example of a current waveform in the present invention obtained by computer simulation. Here, eight memory cells 6 shown in FIG. 1 are connected in series in the horizontal direction, a 5Ω resistor IRR is connected between the eighth memory cell and the ground, and a 1.44 pH as wiring capacity
This is a simulation performed for a circuit configuration in which inductance elements of In Figure 3, II indicates the output current waveform that occurred when the first memory cell underwent magnetic flux quantum transition, and similarly, 14.17 indicates the output current waveform that occurred when the fourth and seventh memory cells underwent magnetic flux quantum transition, respectively. The output current waveform, IRR, indicates the output current waveform of the eighth memory cell flowing through the resistor IRR.

As can be seen from Figure 3, the current is delayed and the current 11
is a steep waveform with a peak value of 60μA and a pulse width of 2.7DS, whereas the final output current IRR has a peak value of 20μA and a pulse width of 4.8ps, and is a small amplitude waveform with a gentle slope. It is a waveform.

Therefore, in order to determine the readout output as a ratio value, the number of memory cells commonly connected to the sense gate cannot be unlimited, but is subject to certain limitations.

Next, each embodiment of the present invention will be described. FIG. 4 shows a route system diagram of the first embodiment of the memory of the present invention. In the same figure,
Components that are the same as those in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 4, m and n memory cells having the same configuration as the memory cell 6 in FIG. . In addition, memory cells 6 arranged in the horizontal direction
t+~6in (however, i is 1.2...9m) is X
Memory cells 6+j to 6mj commonly connected to the control signal line 91 from the data driver 18 and arranged in the vertical direction
(where j is 1, 2, . . . , n) is commonly connected to the control signal line 10j from the Y decoder driver and the Y decoder driver in the sense circuit 19.

Furthermore, each memory cell 6i+ to 5in arranged in the horizontal direction
A sense gate 11i is connected in series to both terminals of the one-junction quantum interference device. Furthermore, the sense gates 111 to 11 are connected to be commonly supplied with a bias signal from a bias signal line 20, and have a common load resistor 21 between the bias signal line 20 and ground.

In addition, each memory cell 611 to 6 inches arranged in the horizontal direction
control signal lines 15; are commonly connected.

According to the Josephson memory having such a configuration, among the m·n memory cells 611 to 6mn, the first control current ■× from the X decoder/driver 18 and the second control current IY from the Y decoder/driver 18 Only the memory cell to which the and is supplied at the same time is selected, and the magnetic flux quantum state of that memory cell is controlled as explained in conjunction with FIG. 2, and writing is performed.

Further, at the time of reading, only one memory cell to which the control currents 1× and IY are simultaneously supplied is selected, and
Whether the memory cell has undergone a flux ti4on transition at its +15 is detected by the same laterally arranged sense gate. For example, when the memory cell 62Tl is selected and undergoes a magnetic flux quantum transition, the pulse current due to the pulse voltage generated at that time flows to the sense gate 112.
Since the current flows through the load resistor 21 and switches it, a current flows through the load resistor 21. This is detected by the Y decoder driver and the sense circuit in the sense circuit 19, and the memory cell 62T
Detection of the stored data "'1" is performed. Note that a constant cycle cock pulse is sent to the bias signal line 20 as a bias current.

FIG. 5 shows a +11 path system diagram of a second embodiment of the memory of the present invention. In the figure, the same components as those in FIG. 4 are denoted by the same reference numerals, and the explanation thereof will be omitted. In this embodiment, the sense gate is not a magnetically coupled Josephson gate as shown in FIGS. It is characterized in that a direct-coupled Josephson gate directly connected to the common connection line 151 of both terminals of the one-junction quantum interference device is used as the sense gate 231.

Since the sense gates 23+ to 23T11 are connected to the memory cells 611 to 6In independently from each other, in order to obtain the OR output of these, the sense gates 231 to 23Tn
Each output terminal is connected to a sense circuit 25, respectively.

Memory cells 611 to 61n are X decoder/driver 18
One of the memory cells is selected by the control I lightning current × from the Y decoder/driver 24 and the control current IY from the Y decoder/driver 24, and its ω state is controlled, thereby causing a magnetic flux quantum transition. At this time, the sense gates 231 to 23I11 in the same row switch, and current flows through the load resistance in the sense gates.

In other words, writing and reading can be performed in this embodiment in the same manner as in the first embodiment. Compared to the first embodiment, this embodiment has the advantage of higher sensitivity because the sense gate is of a direct connection type.

In FIG. 5, the direct-coupled sense gate 1- is provided only at one end of all the memory cells 611 to 6 inches in the same row (horizontal direction), but it may be provided at both ends, respectively. Furthermore, in each embodiment, the sense gates were connected to the memory cells 6i+ to 5in arranged in the horizontal direction, but the sense gates were connected to the memory cells 6+j to 6R1 arranged in the vertical direction.
It goes without saying that the connection to j may be changed to J:.

(Effects of the Invention) As described above, according to the present invention, since the number of constituent elements of a memory cell is smaller than that of conventional memory cells, the influence of variations in constituent elements can be reduced, and the sense gates are arranged vertically. Alternatively, since one memory cell is provided for each memory cell of multiple Ayu1 in the horizontal direction, the dimensions of the entire menu can be reduced and the occupied area can be reduced, and the number of wires required is smaller than in the past. The peripheral circuitry can be simplified, the degree of integration can be improved compared to the conventional technology, and the operating margin can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the main part of the present invention, FIG. 2 is an explanatory diagram of memory operation in the present invention, FIG. 3 is a diagram showing an example of a current waveform obtained by operation simulation of the present invention, and FIG. 1 is a circuit system diagram showing the first embodiment of the present invention;
FIG. 6 is a circuit diagram showing a second embodiment of the present invention, and FIG. 6 is a circuit diagram showing an example of a main part of a conventional Josephson memory. In the figure, 6.611~6in is a memory cell, 7 is a Josephson element, 8 is an inductance loop, 9.91~9m is a first control signal line, 10. 10+~10η is a second control signal line, 11 .11
+ "11m, 23+ ~ 23tn is the sense gate, 20 is the bias signal line, and 21 is the load resistance. Moon's Memory Society Kai's Famous B Moon ■ Lovely Q
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Claims (3)

[Claims] (1) Consisting of a one-junction quantum interference device (7, 8) and first and second control signal lines (9, 10) magnetically coupled to the one-junction quantum interference device (7, 8) , a large number of memory cells arranged in a matrix (6, 6_n to 6_m
_n) is connected in series with both terminals of the one-junction quantum interference device in each memory cell arranged in the vertical or horizontal direction among the large number of memory cells (6, 6_n to 6_m_n), and from the memory cell. Sense gates (11, 11_1 to 11_m, 23_1 to 23_m
), which commonly connects the first control signal lines (9, 9_1 to 9_m) in each memory cell arranged in the horizontal direction, and connects the second control signal line (9, 9_1 to 9_m) in each memory cell arranged in the vertical direction. control signal line (
10, 10_1 to 10_n) are commonly connected, one memory cell is selected by both control signals of the first and second control signal lines, and the magnetic flux quantum state of the memory cell is controlled. Features Josephson Memory. (2) The sense gate is a magnetically coupled Josephson gate (11_1 ~11_m), and having one load resistance (21) in common between the common bias line and ground of the magnetically coupled Josephson gates arranged in the horizontal or vertical direction. Josephson memory described in item 1. (3) The sense gate is a direct-coupled Josephson gate (23_1 to 23_m) directly connected to a common connection line between both terminals of the one-junction quantum interference device in each memory cell arranged in the vertical or horizontal direction. 2. The Josephson memory according to claim 1, wherein the memory cells are arranged at one end or both ends of the plurality of memory cells arranged in the vertical or horizontal direction.