JPS6020840B2 - Magnetic flux quantum memory storage cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a magnetic flux quantum memory type unit memory circuit or memory cell consisting of a superconducting open loop including a Josephson element.

Typical conventional memory cells of this type include those shown in FIGS. 1A to 1C.

In the cell shown in FIG. 1A, a closed circuit 2 is made of superconducting thin film wires including Josephson elements 3 and 4, and circuit current lines 1 and 6 made of superconducting wires are connected to two points of this closed circuit. .

First and second control lines 5a and 5b are provided via inductive couplings 7a and 7b to this closed circuit 2, respectively. One of these control lines is necessary for selecting X in the cell array, and the other one is necessary for selecting diagonal or DC bias. This type of memory circuit requires: (i) DC bias, which increases power consumption in peripheral circuits; 0) Even if you don't need it,
A control line is required to select the diagonal, and the peripheral circuitry becomes large-scale.

iii) The drive fin flow or pulse must be bipolar;
There are drawbacks such as. In the memory cell shown in FIG. 1B, circuit current lines 1 and 6 made of superconducting wires are connected to two points of a superconducting closed circuit 2 including a Josephson element 3, and conductive couplings 7a. Control lines 5a and 5b are provided via line 7b to reduce the critical current of the element 3.

Furthermore, for the purpose of discussion, a Josephson element 8 exclusively used for discussion is provided in the readout line 5c at a position where the critical current is reduced by the current flowing through the closed circuit 2.
A damping resistor 9 adjusts the performance characteristics of this memory circuit.

In this type of unit memory circuit, when a memory cell array is configured with a large number of cells, i) two wires for X and two wires for Y, a total of four wires are required, which increases the complexity of the wires and the peripheral circuitry. ii) The operating margin of the read-only Joseph Soso element 8 is also narrow. The memory cell shown in FIG.
The line inductance of the left branch circuit including the Josephson element 3 and the right branch circuit including the Josephson element 4 is significantly different from each other at each connection point, and the pair of control lines 5a and 5b is They are magnetically coupled via conductive couplings 7a and 7b.

In this cell, the pair of control lines 5a and 5b can be made into one from the viewpoint of the operation of the cell itself, but even if this is done, i) the drive current is bipolar, and h) the operating margin is limited. There is a large difference between the positive and negative sides of the zero control line current, and the disadvantage is that the negative side region is particularly narrow.

The present invention was made in view of the actual situation of conventional memory cells, and the cell itself requires at least two lines to operate, and the driving warm current or driving pulse can be unipolar. It is an object of the present invention to provide a skid type memory cell that has a large operating margin and is easy to design.

In addition, an example of a desirable configuration when the cells of the present invention are assembled as a secondary memory array with X rows and Y columns is also listed later in this document, but in such a cell array, three lines are required in the case of an XY coincidence selection configuration. However, with the word selection configuration, it is possible to search for a line configuration that could not be achieved with the occupied cell, that is, a configuration with a number of lines that cannot be reduced any further.

Hereinafter, an embodiment of the memory cell 10 of the present invention will be described with reference to FIG. 2.

FIG. 2A shows the basic schematic configuration or equivalent circuit of the cell of the present invention, and shows Josephson switching sections 13 and 14 that have the same switching function as a single Josephson element.
The circuit current lines 11 and 16 are connected to the superconducting closed loop 12 including the superconducting closed loop 12 so that one switching section 13 is distributed to the left branch or branch circuit 12L, and the other switching section 14 is distributed to the right branch 12R. .

For example, one of the Josephson switching parts 13 and 14 may be made of an open circuit including a plurality of Josephson elements such as a three-junction skid, but the basic operation is the same and simple. Here, each Josephson switching section 13, 14 will be described as a single Josephson element. A control line I5 is arranged for one Josephson element 13 to be inductively coupled thereto and to control its critical current.

In the figure, as shown by the arrow lx, the control current lx is applied to the control line 15.
Flowing reduces the critical current value of the element 13, that is, the element current value that causes a transition from the zero voltage state to the voltage state. A damping resistor 19 placed in parallel with the inductances 17 and 18 and a damping resistor 25 placed in parallel with the cell adjust the dynamic characteristics of this memory cell, but are unnecessary for explaining the basic configuration. It is. left branch 12
The inductance 17 of L and the inductance 18 of the right branch 12R are the circuit current line 1 to the open loop 12.
In the present invention, the inductance 17 on the branch 12L side, which has the Josephson element 13 inductively coupled to the control line 15, is reduced by 4° as much as possible. , the closed loop inductance L is almost included in the inductance 18 of the counterpart branch 12R to strengthen the asymmetry.
Therefore, the equivalent circuit shown in FIG. 2A can be further modified as shown in FIG. 2B. The same symbols are of course the same components as in FIG. 2A, and the inductance 17 of the left branch
(although of course the equivalent inductance of the element 13 itself does exist). When the control current lx = 0 flowing through the control line 15, the critical current lo, (lx = 0) of the Josephson element 13 is equal to the critical current lo, (lx = 0) of the other Josephson element 1.
Critical current lo of 4 (lo, (lx=0) Z1.

2) is fine, but basically, to simplify the design, lo, (lx=0)=1 solution=lo, and L1 in relation to the closed loop inductance L mentioned above.

=0.5~2■o (■. is one magnetic flux quantum), for example, L1
. =■Choose o. Also, when the control line current lx=X, the reduced critical current lo, (l
L1o, (lx=×) in x:X) is 0.6 to 0.
1■.

, for example, select 1/4■o. In addition, below, lx (lx=
0) is expressed as lx(0), and lx (lx=×) is expressed as lx(X).

Here, if the relationship between the control current lx and the critical current 1 (x) of the Josephson element 13 is a linear relationship as shown in FIG. It can be clearly shown on the coordinates as shown in FIG. 3B.

The curve To connecting the points plotted with white circles indicates that the magnetic flux doji is held within the closed loop 12 in FIG. 2 A or B,
The curve T, which connects the points plotted with black circles, is the curve T when a permanent circulating current i is flowing in the closed loop 12 in a clockwise direction as described below. , that is, the threshold value curve when the magnetic flux doji is held in the loop. For convenience, the case where the magnetic flux doji is grasped or not is set as logic "0", and the opposite case is set as logic "1", and when the illustrated polarity ly is logic "0" and the control current lx is 0. Let the critical current value of the cell 10 be lco(lx=
0) (also abbreviated as lco(0)), the critical current value lco(0) for the reverse circuit current -1y is lc
A triangular threshold curve To that is symmetrical with respect to the lx marrow is realized in the first and second quadrants at the point where o(0) is symmetrical with respect to the origin 0 and the value of the current lx becomes lo, = 0. , its internal state becomes a military voltage state of logic "0".

On the other hand, as shown by the virtual line i in FIG. 2B, the persistent current i flows clockwise in the closed loop 12.
” state, the circuit current ly is in the direction of canceling the current i for the Josephson element 13, so the cell 10
The critical current lco(0) is that in the “0” state lco
(0), and the circuit current in the opposite direction -1y is in the same direction as the permanent circulating current i, so that the critical current lc, (0) is the same as that in the "0" state described above.
co(0) in absolute value.

in the end,. This threshold curve T, is the threshold curve To in the “0” state.
The triangular shape created by is translated in parallel to the positive direction of the ly axis, and the inside becomes a zero voltage state when the logic is '11'.In addition, the circuit current in the reverse direction -1y was mentioned as follows. For ease of explanation, the cell of the present invention operates only in the first quadrant of FIG. (The same applies when both have negative polarity).

In addition to the lco(0) etc. already mentioned, the calculation also calculates 1o,
,1.

2 can be found, but since specific values or relational expressions are not required to explain the operation, these equivalent values and mathematical expressions will be omitted.

To explain the operation, first, for the roofing, connect l to the control line 5.
By adding x=X, the critical current of the Josephson junction element 13 is reduced to lo·(×) as shown in FIG. ×
) or lc. (X).

Of course, lco(X) is the critical fin flow value for the control current lx=X when it is logic "0" and lc,(X) is logic "1". In the above state lx=X, the current l in the circuit current line
The information to be embedded is selected as either "0" or "1" depending on whether or not y is flown, that is, whether ly=0 or ly=Y.

If ly=0, no permanent return current is generated in the closed circuit 12 or disappears, and the written information is "0".

To be more specific, if the previous state is logic "0", the threshold curve of cell 10 will follow the curve To in FIG. 3B,
Therefore, nothing happens when lx=X, ly=0, but
If the previous state is logic "1" and a permanent circulating current i is flowing, the threshold curve 0 line is the curve T. in FIG. 3B. Therefore, since lx crosses point P on the way to x, it instantaneously transitions to a voltage state (a so-called vortex transition occurs), Josephson element 13 opens, and ly
At =0, the persistent current flows away into the circuit line, and immediately thereafter the closed loop returns to the zero voltage state.

At this time, there is no permanent circulating current in the loop. When the circuit current ly=Y is added to the control current lx=X, the information to be inferred is "1".

The value of OY is selected in the range of 1 (×)miYSIo, (X)+lo. This is lco(×)miYSic in Figure 3B.
, (X). At this time, curve L is point Po
(X) and transitions to the "1" state. The transition at this time can also be made into a vortex transition by selecting the damping resistors 19 and 25 to be mutually exclusive. After returning the control fin current lx to zero, the write operation is completed by returning ly to zero, leaving a permanent circulating current.

0 In the read operation, a current ly=Y is first passed through the circuit current line, contrary to the write operation.

Next, when current lx=X is passed through the control line 15, the closed circuit 12
In the “1” state where a permanent circulating current flows through the
Since the curve T in the middle is not exceeded, no crab pressure is generated between the lines 1 and 16. However, in the "0" state where no permanent circulation fin flow is flowing in the open circuit 12, the curve T in Fig. 3 is not exceeded. Point Po
When the voltage is exceeded, a voltage is generated between the lines 11 and 16 (a so-called voltage transition is exceeded). In order to enable such an operation, the values of the damping resistors 19 and 25 are appropriately selected. If no voltage is generated between the lines 11 and 16 during the readout operation, lx is first returned to zero, and then ly is returned to zero to complete the readout operation. If a voltage is generated between the lines 11 and 16, ly is first returned to zero, and then lx is returned to zero to complete the starting operation. In this way, the former will be in the write state of “1”, respectively.
The latter goes through the write state of "0" and returns to the steady state of lx:ly=0. The operation of the basic embodiment of the cell of the present invention has been described above, and it can be seen that the above-mentioned purpose has been fully achieved. Furthermore, although the operating margin is inherently large, for example, the points Po(X) and Po(X) in both curves in Figure 3B
It will be the largest if designed to match. By the way, although the cell of the present invention can obtain non-destructive readout as a result, in the above-mentioned case, the operation procedure is changed according to the contents of the discussion, so the operation is a process of devising destruction and then trying again.

Therefore, a desirable configuration for assembling the cells of the present invention into an array, automatically performing this operation without determining the read contents, and achieving non-destructive logic will also be described. FIG. 4 shows an example of the configuration method in the case of 16 bits. C,. -C44 are shown in FIG. 2A. 8 units of memory circuits or cells 10. 15-. 15-2,15-
3.15-4 respectively correspond to the control line 15 shown in the second diagram.

Cells C, ., included in the same Y row. ~C Small CM~C Ground C,
3~C wire, C, and 4~C wire are the circuit current lines 11 in Fig. 2, respectively.
, 16, and constitute circuit current lines 11-, 16-: 11-4, 16-4 for each row. In the circuit current line in each row, a reset Josephson element 20 is inserted in series with each series cell, and a set Josephson element 21 is inserted in parallel therewith.
The reset Josephson elements 20-, ~20-4 include
An input line 23 for selectively transitioning these elements to a voltage state runs along the line, and set input lines 24-2 and 24-4 for each row are arranged in the set lines 21- and 21-4. ing. Then, a damping resistor 25' is connected to each element 20.
, 21 in parallel. Considering two sets of Josephson Shigeko 21, 20 for reset per each row (suffixes are omitted unless specifying each row) and four cells 10 of the present invention per row as one closed loop, the circuit current line 11.16 When a DC supply current is passed through the open loop, almost all of the supply current flows into the Josephson element 21 for each set because there is an inductance in this open loop.

Here, referring also to FIG. 5 below, when a set signal or a set pulse is applied to the set input line 24 to cause the Josephson element 21 to transition to a voltage state, the supplied current flows to the series of cells 10... This current flows into the circuit current ly for each cell as explained with reference to FIGS.

When this happens, the setting Josephson element 21 will automatically return to the drop voltage state. here, now,
For example, if control line 15-2 is selected, different memory circuits C2, to C24 are selected, and lx, ly
Accordingly, each operation explained in FIG. 3 is performed.

No change occurs in other unselected memory circuits. To return ly to zero, a pulsed reset signal is applied to the input line 23 of the reset Josephson element 20.
Then, the Josephson element 20 becomes a voltage state, the circuit current ly becomes zero, and the supply voltage is again bypassed to the setting Josephson element 21. As the circuit current ly becomes zero, the resetting Josephson element 20 automatically returns to the zero voltage state and becomes the initial state.
Next, the non-destructive motion is performed as follows.

A pulse-like set signal is applied to the input line 24 of the Josephson element 21 for setting, and a circuit current ly=Y is caused to flow in the closed circuit. Assuming that the control line 15-2 is selected and a control current lx=X is applied to the control line 15-2, the memory circuits C2, to C24 enter the setting operation. To describe cell C2, if this cell C2 is in the "1" state,
As mentioned earlier, no voltage is developed in this cell, and the current ly
= Y is flowing). After a certain period of time × selection current lx
is set to zero, and then a pulsed reset signal is applied to the input line 23 of the reset Josephson element 20 to return the current ly to zero. On the other hand, if cell C2 is in the "0" state, a voltage is generated in this cell, and the circuit current ly is driven back toward the setting Josephson element, so the current ly eventually becomes zero. At the same time, C2 returns to the voltage receiving state. Until this point, lx=X is flowing, and after this point, lx=0 is 1×
= Determine the time that × is flowing. In this case, ly returns to zero first, and then lx returns to zero, so C2 remains in the "0" state), and can be maintained in the state before the gun was ejected. Thereafter, even if a reset signal is applied to the input line 23, no change occurs because the current ly is already zero. In this way, even with the same procedure of motion, the state of the memory circuit before and after motion does not change (i.e., non-destructive motion)
is obtained. The logic "0" and "1" can be detected by detecting whether the current ly is flowing or not at time A in FIG. The above configuration has been explained using a word selection configuration in which when one control line is selected, all the corresponding memory circuits are selected. It can also be configured.

FIG. 6 shows an equivalent circuit or a schematic configuration of the second embodiment of the present invention as a unit memory circuit or memory cell suitable for such a configuration example, and the difference from the first embodiment is that one branch 12L. A pair of control lines 15 are inductively coupled to the Josephson switching unit 13 (this may be a single element as described above, or may be a skid type open circuit, but here it is simplified as a single element). The only difference is that it is constructed of lines 15a and 15b. That is, to describe the first embodiment, when the control current lx flowing through one control line 15a and the control current ly' flowing through the other control line 15b are applied simultaneously, the critical current of the Josephson element 13 The value 1 is made to satisfy (lx+ly) of L1; 0.6 to 0.1 ■o.

Using this, the memory space shown in FIG. 7 is derived from the 16-bit configuration similar to FIG. 4.

Damping resistors and the like are omitted, and the same reference numerals as in FIG. 4 indicate the same or similar Ayaseko. Among the pair of control lines, one control line 15a-, ~15a-4 is for flowing a selective current lx from the X selection circuit, similar to the control line 15 in the previous embodiment, and the other control line 15b -, ~15b-4 are parallel to the cell groups in each row and receive selection current ly' from the Y selection circuit.

The control line 15b and the input line 24 of the setting Josephson element 210 are selected in a mesh for each row. Regarding the operation, for cell C selected by lx and ly',
If lx and ly' are collectively considered as lx, the explanation of the previous embodiment can be applied as is. As described in detail above, according to the memory cell of the present invention, it is possible to provide a highly reliable skid type memory cell in which the drive current is unipolar, the operating margin is large, and the design is easy. Depending on the application, it has a structure that allows it to be driven by two wires even if a memory array is assembled, and even if it is a three-wire system, it does not have the drawbacks of conventional methods. be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a conventional Josephson memory cell, FIG. 2 is a schematic block diagram of a basic embodiment of the present invention,
FIG. 3 is an explanatory diagram of the operation of the cell of the present invention, FIG. 4 is a schematic configuration diagram of an applied example of the first embodiment, FIG. 5 is an explanatory diagram of the operation in the applied example shown in the fourth embodiment, and FIG. FIG. 7 is a schematic diagram of an applied example of the second embodiment of the cell according to the present invention. In the figure, 10 is the magnetic flux quantum memory type memory cell as a whole, 1
1, 16 are circuit current lines, 12 is an open loop, 13, 14
15 is the Josephson switching section, 15 is the control line, 18
is the inductance. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. Two Josephson switching sections are provided in the superconducting closed loop, and circuit current lines are connected so as to distribute the two Josephson switching sections into left and right branch circuits,
The two branch circuits have different inductances, and a control line for controlling the critical current is inductively coupled to the Josephson switching section in the branch circuit with a relatively small inductance. Magnetic flux quantum memory storage cell.