JPS5829198A - Josephson memory circuit - Google Patents

Abstract

PURPOSE:To decrease the size of a gate and to make the entire memory cell small in size, by controlling the phase conditions of each junction through a control current directly injected to a super-condition closed loop including Josephson junctions via a gate and performing the switching operation. CONSTITUTION:A series connection of Josephson junctions 4A and 4B and a Josephson junction 4C connected in parallel are provided in a super-conduction closed loop 3, and at each middle point of the Josephson junctions 4A, 4C; 4A, 4B; 4B, 4C, a word current line 2A flowing an input current, a control current line 5 to a closed loop 3, a word current line 2B picking up and output current are respectively provided. A switching gate connected with a control current branching resistor 6 is provided on one point on the line 5. Thus, since the phase conditions of each junction are controlled with a control current directly injected to a closed loop 3 via one gate and switch operations made, the size of gates can be decreased and the entire memory can be made small in size.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Josephson memory circuit consisting of a computer element that uses the Josephson effect, which is one of the superconducting phenomena.

Conventionally, this type of circuit includes one or two write gates and one read gate in a closed loop made of superconductors, and these gates are called SQUIDs. Some used quantum interference gates consisting of two or three Josephson junctions and an inductance loop, or gates consisting of a single vertical Josephson junction.

However, in this type of memory circuit, the write and read gates are switched by a magnetic field generated by a control current via an inductance, so that a magnetic flux quantum Φ, which is the smallest unit of magnetic flux, is used. (Φ.

It is necessary to provide a special inductance sufficient to generate at least one of the gates (~2X10-'Hatawb), and there is a logical limit to the miniaturization of the gate itself, and writing and reading are performed using separate gates. Therefore, there is a problem that the memory cell as a whole cannot be sufficiently miniaturized, and there is a theoretical limit to increasing the density and speed of memory circuits for computers.

This invention was made in order to eliminate such problems with conventional memory circuits.

Both readout methods include three or four Josephson junctions in a superconducting closed loop, and the phase condition of each junction is determined without using inductance by means of a control current injected directly into this closed loop. This is a 5K device that operates the switch with a single starting gate, and there is no need to use a magnetic field generated through an inductance to control the switch operation of the gate, so it is not necessary to use an inductance as in the conventional method. The gate itself can be made much smaller than a switching gate, and the number of gates is one per memory cell, so the memory
The entire cell can be miniaturized and can be used as a high-density computer circuit.
Suitable for high speed. Hereinafter, the present invention will be described in detail based on the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which 1 is a memory loop made of a superconductor that stores memory as a magnetic flux medium generated in the loop by a persistent current, 2A,
2B is a word current line through which a word current I for generating magnetic flux is generated in the memory loop 1; 3 is provided at the midpoint between the two coupling points of the memory loop 1 and the word current lines 2A and 2B; 4A, 4B, and 4C are Josephson junctions provided in the superconducting closed loop 3, and 5 is a bit current flowing into the superconducting closed loop 3 from an intermediate point between the Josephson junctions 4A and 4B. IIs or sense current 1. A control current line 6 is used to control gate switching by injecting the bit current ■■ or sense current I3 from a part of the control current line 5 when the Josephson junction 4B transitions to a voltage state. It is a resistor that flows in.

Writing to memory loop 1 is performed using word current line 2A,
Word current ■1 from 2B to memory loop 1, and
Reading is performed by feeding the bit current Im from the control current line 5 to control the circulating current IL flowing in the memory loop 1. When the sense current 3 is fed from the control current line 5, the readout is performed by feeding the bit current Im from the control current line 5. It is used to detect whether voltage is generated or not.

FIG. 2 shows the circulating current 1 of the switching gate shown in FIG. and bit current II or sense current! I was able to write the operating point in mesori operation on the threshold characteristic that shows the relationship between . The Josephson junctions 4B and 4C transition to a finite voltage state, but when the operating point crosses the part indicated by the dotted line, the Josephson junction 4B transitions to a finite voltage state, but the voltage generated at the Josephson junction 4A is a Josephson junction state. Since the voltage at Josephson junction 4CK is opposite to and equal in magnitude to, no voltage is generated at Josephson junction 4CK. The existence of these two areas allows memory writing and non-destructive reading with one gate.

#! First, we will explain the write operation using Figure 2.0
For convenience, the counterclockwise circulating current of memory loop 1 is defined as positive IL, and the circulating current IL corresponds to the IL point in FIG.
The flowing state of the memory is ``1-circulating current IL is 0''
The state where the flow corresponds to the point is defined as "o" of the memory. Initially, ``1'' is written, and to write 10'', a word current of 1W is applied and the circulating current IL is 1W.
If the bit current is increased from point b to point b, and then a bit current 1 corresponding to point 0 is injected, the operating point will move from point b to point d, but at this time, the operating point will be on the solid line of the threshold curve. The Josephson junction 4C transitions to a finite voltage state because it crosses the region of
, all moved to the above branch, he Josephson junction 4C
returns to zero voltage state again. In this state, the word current ■w,
If the bit current II is cut off, the circulating current IL will flow in an amount corresponding to the 0 point in order to preserve the magnetic flux in the memory loop 1, and this means that ``1'' has been written.

When writing “】”, if the word current 1 and the bit current 1 are made to flow in the same magnitude as the writing of @O” in the opposite direction, the operating point will shift from K to a - f - g, and during this time. Since the threshold curve is not crossed, the gate remains in a zero voltage state and the word current Iw.

If the bit current ■- is turned off, it returns to the original point a and maintains the state of 11', even if 0" is written initially. If 10" is written using the same operation and operating principle as above, the operating point is @ -o f -m 6 and @ol'' is saved, but when @11 is written, it moves to e -h -1. After cutting off the word current Its bit current Lm, it moves to point a, and @1 ” is written.

For reading, a sense current corresponding to one point from the control current line 5 flows into the memory loop 1 (if "@1" is written in the memory loop 1, the operating point is m-
+, and during this time the threshold value l! The Josephson junction 4B for crossing the dotted line portion of lIs transitions to a finite voltage state and a voltage ゛ is also generated in the resistor 6, but the Josephson junction 4C remains at zero voltage state 1liilK.
When the sense current I, is cut off, the circulating current I, is conserved,
Return to point a again. If @f is written, when the same sense current I as above is applied, it changes to e −a l・, and since the small operating voltage remains inside the threshold curve, all Josephson junctions 4A to 4C are at zero voltage. No voltage is generated in the resistor 6 as it is.In this way, no matter which one is read out, the same circulating current IL as before the readout is preserved after the readout, so this readout is a non-destructive readout.

Word current If and bit current II used in the above explanation
The threshold curve of the s sense current Is and the range of the voltage transition region and the non-voltage transition region of the Josephson junction 4C are as follows:
The ratio of the critical values of the Josephson currents in each Josephson junction of the switching gate.

It can be controlled by the size of the capacitance of the Josephson junction and the size of the resistor 6, and the operating point can also be selected in a wide range depending on the left and right division ratio of the memory loop 1. Further, in the above embodiment, the memory loop 1 of the switching gate includes three Josephson junctions 4A to 4C.
By inserting two Josephson junctions in series instead of one Josephson junction 4C, a total of four Josephson junctions are included in memory loop 1 for switching.
The same effect can be obtained even when used as a gate.

As described in detail above, the Josephson memory circuit according to the present invention includes three or four Josephson junctions in a superconducting closed loop for both writing and reading, and a control current directly injected into the closed loop reduces the inductance. The switch operation is performed by controlling the phase conditions of each junction without using a gate switch, and there is no need to use a magnetic field generated through an inductance to control the gate switch operation. Therefore, the gate itself can be significantly smaller than conventional switching methods using inductance, and the number of gates is only one per memory cell, making it easier to use memory cells.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the characteristic curve and operating point of the switching gate shown in FIG. In the figure, 1 is a memory loop, 2A, 2B are word current lines, 3 is a superconducting closed loop, 4A, 4B. 4C is a Josephson junction, 5 is a control current line, and 6 is a resistor. Agent Nobu Kuzuno - (1 other person) Figure 1 Figure 2 L Procedural amendment (voluntary) January 13, 1980 1, Indication of case Patent application 1982-12698'l
No. 1, No. 2, Title of the invention Jisho Setsun Mesori Circuit 3, Relationship to the case of the person making the amendment Patent applicant address Higashi 5rC Tocho, 2-2 Marunouchi, Daita-ku
No. 3 Name (601) Mitsubishi Electric Corporation Representative Hitoshi Katayama 4, Agent address □2-2-3 Marunouchi, Chiyoda-ku, Tokyo
No. Mitsubishi Electric Corporation 5 Claims column 1 Detailed explanation of the invention and drawings 6 of the specification to be amended Contents of the amendment (1) Amend the claims of the specification as shown in the attached sheet do. (2) On page 2, line 16 of the specification, it says "Special". Correct "to have". (3) Similarly, the words ``this closed loop'' in line 6 of page 3 and line 8 of page 9 are corrected to read ``superconducting closed loop.'' (4) Correct Figure 2 as shown in the attached sheet. Above 2. - Claims A series body of first and second Josephson junctions in one superconducting closed loop, and a third Josephson junction or third and fourth Josephson junctions in parallel to this series body. A word current line for passing an input current is provided at an intermediate point between the first and third Josephson junctions, and a word current line is provided at an intermediate point between the first and second Josephson junctions, and a word current line is provided at an intermediate point between the first and second Josephson junctions. A control current line is provided for flowing a closed loop control current, and a word current line is provided for taking out an output current from an intermediate point between the second and third Josephson junctions or an intermediate point between the second and fourth Josephson junctions, and further A Josephson memory circuit characterized by including a resistor for branching a control current at one point on a control current line.

Claims (1)

[Claims] A series body of first and second Josephson junctions and a series body of w3 Josephson junctions or third and fourth Josephson junctions connected in parallel to this series body are provided in one superconducting closed loop. , a word current line for passing an input current is provided at an intermediate point between the first and third Josephson junctions, and the first and! A control current line through which the superconducting closed loop control current flows is provided at a midpoint between the second and third Josephson junctions, and from a midpoint between the second and third Josephson junctions or a midpoint between the second and fourth Josephson junctions. A Josephson memory circuit characterized in that a word current line for taking out an output current is provided, and a resistor for branching the control current is connected to one point on the control current line.