JPH0772995B2 - Superconducting memory circuit - Google Patents

Description

The present invention relates to a superconducting memory circuit using a superconducting element.

(Prior Art) A conventional superconducting memory circuit is, for example, IEEE Journal of solid-state Circuits Vol.sc-1.
4 No.5 1979 October 794 by Henkel et al. As shown in FIG. 5, a conventional superconducting memory circuit has a superconducting loop composed of first and second branches 44 and 45, a signal line Iy43 for inputting and outputting a superconducting current to the superconducting loop, and the first branch 44. Of the write gate 46 provided in the middle of the line and signal lines Ix47 and Iy electromagnetically coupled to the write gate 46, respectively.
'48 and a read line Is50 having a read gate 49 electromagnetically coupled to the second branch 45.
The memory system of this conventional superconducting memory circuit is as follows. The method of writing “1” of binary (1,0) logic is to apply an appropriate current to each of the signal lines Ix47 and Iy′48 to switch the write gate 46 to the voltage state and then apply an appropriate current to the signal line Iy43. Then, the currents of the signal line Ix47 and the signal line Iy'48 are turned off, and then the current of the signal line Iy43 is turned off, and a permanent current is passed through the superconducting loop. In this case, the inductance L of the superconducting loop
The product of _Loop and the permanent current I _circ is the magnetic flux quantum Φ ₀ (2 × 10 ^-15
It is quantized in units of Wb). That is, L _Loop・ I _circ
= NΦ ₀ (n is an integer).

In the method of writing "0", an appropriate current is applied to each of the signal lines Ix47 and Iy'48 to switch the write gate 46 to the voltage state, and then no current is applied to the signal line Iy43. As a result, no permanent current flows in the superconducting loop. As a method of reading stored information, an appropriate current is passed through the read line Is50, the read gate 49 is biased, and then an appropriate current is passed through Iy43.
Information 1 is stored and the persistent current I in the superconducting loop
_{When circ} is flowing, a part of the current flowing from Iy43 and the permanent current I _circ are superimposed on the second branch 45 that is electromagnetically coupled to the read gate 49, and flow, and the read gate 49
Is switched to the voltage state and it is determined that the information is 1. When the stored information is "0", there is no permanent current I _{circ in the} superconducting loop, and only the current flowing from Iy43 flows into the second branch 45 that electromagnetically couples to the read gate 49, and the read gate has a supercurrent. The conduction state is maintained and it is determined that the information is zero.

(Problems to be Solved by the Invention) In the conventional superconducting memory circuit, when writing “1”, a signal current is passed through the signal line Ix47 and the signal line Iy′48, and then the signal line.
It is necessary to turn off the currents of the signal line Ix47 and the signal line Iy'48 after passing the current through 43, and then turn off the current of the signal line Iy43.
This has hindered the simplification and speedup of the "1" write operation.

An object of the present invention is to provide a superconducting memory circuit that solves this problem.

(Means for Solving the Problems) According to the present invention, a first superconducting line and a second superconducting line which have the same inductance and which connect the point where the superconducting current flows in and the point where the superconducting current flows out, A first write gate provided in the middle of the first superconducting line, a second write gate provided in the middle of the second superconducting line, and a first electromagnetically coupled to the first write gate. Signal line, a second signal line electromagnetically coupled to the second write gate, a read gate electromagnetically coupled to the first superconducting line, and a read line in which the read gate is arranged midway. And a third signal line electromagnetically coupled to the first and second write gates and the read gate, respectively, and at the time of writing, the first and third signal lines or the second,
By passing a current through the third signal line, the first or second write gate is momentarily brought into a voltage state and then returned to the superconducting state, and the current flowing through the superconducting line provided in the middle of the write gate is changed to the other state. It is smaller than the current flowing in the superconducting line and is not zero, and the difference between the current values of the two lines is large enough to be discriminated by the reading gate. When reading, the current is applied to the reading line and the third signal line. By flowing, the superconducting memory circuit is obtained in which the stored contents are read out depending on whether the read gate is in the superconducting state or the voltage state.

(Operation) FIG. 1 is a circuit configuration diagram for explaining a superconducting memory circuit according to the present invention.

Superconducting bias line B1 is at the branch point P8 and the branch B _1, 7 of the superconducting line branches to branch B ₀ 6 superconducting line, the coupling point Q9 and branch B1,7 superconducting line the superconducting line Branch B ₀ 6 joins. Write gate G ₁ , 11 Branch B in the middle of branch B 1,7
_The write gate G ₀ 10 is arranged in the middle of ₀ 6.
The signal line Y ₁ 3 and the signal line X 4 are electromagnetically coupled to the write gate G ₁ 11. The signal line Y ₀ 2 and the signal line X 4 are electromagnetically coupled to the write gate G ₀ 10. Branch B ₁ 7 and the read gate GS12 which electromagnetically coupled to the signal line X4 is positioned in the middle of reading line S5. Inductance of branch B ₁ 7 and branch B ₀ 6
L _B1 and L _B0 are equally designed to be L _B1 = L _B0 = L _B. The control characteristics of the write gates G ₁ , G ₀ 11, 10 are shown in FIGS. The control characteristics of the read gate GS12 are shown in FIG. The shaded area in Figures 2 and 3 indicates the gate G ₁
11, G ₀ 10 and GS 12 are regions showing the superconducting state.
_{Also, i B1, i Y1, i} X, i B0, i Y0, i S each branch B ₁ 7, signal lines
It is a current flowing through Y ₁ 3, signal line X 4, branch B ₀ 6, signal line Y ₀ 2, and read line S 5. The state of “1” corresponds to the state of i _B1 <i _B0 , and the state of “0” corresponds to the state of i _B1 > i _B0 . ("1"
The name "0" is for convenience and can be explained in reverse. ) Indicates a method of writing "1". Bias line B ₁
A current of i _B = a is passed. Branch as the initial state
A current of i _B0 = i _B1 = a / 2 flows through B ₀ , B ₁ 7, 6. Signal line Y ₁ 3
Flow to i _Y1 = C becomes current, the signal line X4 i _X = b becomes current simultaneously. Due to the control characteristics shown in FIG. 2, the write gate G ₁
11 switches to the voltage state, but in parallel the superconducting line branch B ₀
Since there is 6, the voltage state is not maintained, and a current of i _B1 = I _Gmin is left, and a current of a / 2−I _Gmin is sent to the branch B ₀ 6. Here, I _Gmin is defined by nΦ ₀ = L _B (a−2I _Gmin ). n is a branched B ₁ 7, B ₀ 6 flux quantum number that is Ho捉in the closed loop constituted by (n1). Then i
_{Let Y1} = i _X = 0. Result write gate G ₁ 11, G ₀ 1
0 becomes a superconducting state, and i _B1 = I _Gmin and i _B0 = a−I _Gmin . That is, the “1” state of i _B1 <i _B0 is realized. Next, a method of reading "1" will be described. Current IS = d will read line S5, flow i _X = b becomes current to the signal line X4. I _B1 = I
It is _Gmin . Under this condition, the read gate 12 having the control characteristic shown in FIG. 3 remains in the superconducting state. The "1" state is determined by the fact that no voltage is generated across the read line S5.

Next, a method of writing "0" will be described. Iyo = c on signal line Y ₀ 2
A current i _x = b is simultaneously applied to the current signal line X4. Since the circuit stores the “1” state, i _B0 = a−I _Gmin
Is. Due to the control characteristics shown in FIG. 2, the write gate is
G ₀ 10 switches to the voltage state. However voltage state because of the branch B ₁ 7 superconducting line in parallel is not maintained i _B0 = I
I _B1 = a−I _Gmin , leaving a current of _Gmin in the branch B ₀ 6. After that, i _Y0 = i _X = 0. As a result the writing gate G ₁ 11, G ₀ 10 becomes superconducting state. That is i _B1 ＞ i _B0
“0” state of is realized.

Next, a method of reading "0" will be described. Read line S5 is =
A current of d and a current of ix = b are applied to the signal line X4. I _B1
= A-I _Gmin . Under this condition, the read gate 12 having the control characteristic shown in FIG. 3 switches to the voltage state. A "0" state is determined by the voltage generated across the read line S5.

As described above, by the superconducting memory circuit according to the present invention, "1""0"
It has been shown that writing and non-destructive reading can be performed. The superconducting memory system of the present invention and the bias line in the superconducting memory circuit
A current i _B is always flowing in B1, and when writing “1”, a current is temporarily supplied to the signal line Y ₁₃ and the signal line X 4 at the same time. As a result, it is possible to simplify and speed up the "1" write operation.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 4 is a circuit diagram showing an array configuration of a 4-bit Josephson junction high speed memory circuit showing an embodiment of the present invention.

The superconducting memory circuit shown in FIG. 1 is arranged in an array of 2 rows × 2 columns to form four memory cells A, B, C and D. Bias line
In the A cell, B ₁ 13 becomes the branches B ₀₁ 23 and B ₁₁ 24 having the same inductance, and in the C cell connected in series with the A cell, the branches B ₀₃ 27 and B ₁₃ 28 having the same inductance. Similarly, the bias line B ₂ 14 becomes the branches B ₀₂ 25 and B ₁₂ 26 having the same inductance in the B cell, and the branches B ₀₄ 29 and B ₁₄ 30 having the same inductance in the D cell connected in series with the B cell. Become. The signal line Y ₀₁ 15 is electromagnetically coupled to the write gates G ₀₁ 31, G ₀₃ 35 of the A cell and the C cell. The signal line Y ₁₁ 16 is a write gate for cells A and C G ₁₁ 32, G ₁₃
Electromagnetically coupled to 36. The signal line Y ₀₂ 17 is electromagnetically coupled to the write gates G ₀₂ 33 and G ₀₄ 37 of the B cell and the D cell. The signal line Y ₁₂ 18 is a write gate G _{12 for} B cells and D cells.
Electromagnetically coupled to 34, G ₁₄ 38. The read gates GS ₁ 39 and GS ₃ 41 of A and C are connected in series by a read line S ₁ 21. The read gates GS ₂ 40 and GS ₄ 42 of B and D are read lines S
₂ 22 are connected in series. GS ₁ 39 to B ₁₁ 24, GS ₂ 40 to B ₁₂ 2
6, GS ₃ 41 is electromagnetically coupled to B ₁₃ 28, and GS ₄ 42 is electromagnetically coupled to B ₁₄ 38. Further signal lines X ₁ 19 is electromagnetically coupled to the writing of the A cell and B cell gate _{G 01 31, G 11 32,} G 02 33, G 12 34 and the read gate GS ₁ 39 and GS ₂ 40. Signal line X ₂ 20 is C
Write gate for cell and D cell G ₀₃ 35, G ₁₃ 36, G ₀₄ 37, G ₁₄ 3
8 and read gates GS ₃ 41 and GS ₄ 42 electromagnetically coupled.

The bias lines B ₁ 13 and B ₂ 14 are each supplied with a current of value a. For example, a method of writing "1" in the A cell is shown. Only G ₁₁ 32 switches to the voltage state by supplying a current of C value to Y ₁₁ 16 and a current of b value to X ₁ 19. As a result, the current flowing in B ₁ 13 flows mainly in B ₀₁ 23. Then Y
_The current flowing to ₁₁ 16, X ₁ 19 is set to 0. Finally, the minimum gate drive current I _Gmin flows to B ₁₁ 24, and a-I _Gmin flows to B ₀₁ 23.
The current of a certain value flows. In this state, the A cell stores "1".

Next, a method of writing "0" in the A cell will be described. Y _{01 to} 15 C
In particular, only G ₀₁ 31 switches to the voltage state, since a current of value B and a current of value b in X ₁ 19 respectively flow. As a result B
_The current flowing through ₁ 13 mainly flows into B ₁₁ 24. Then Y ₀₁ 15, X ₁
The current flowing through 19 is set to 0. Finally, the gate minimum drive current I _Gmin flows through B ₀₁ 23, and a current of a−I _Gmin flows through B ₁₁ 24. In this state, the A cell stores "0". Although the cell A has been described above, the write operation is performed on the other cells on the same principle.
For example, when writing "0" to the D cell pass a large portion of the Y _02, 17 C a value of current, the bias current flowing through the B ₂ 14 by flowing b becomes current each X ₂ 20 to B ₁₄ 30. Next, a method of reading the information of the A cell will be described. A current having a value d is applied to the reading line S ₁ 21 and a current b is applied to X ₁ 19. In this state, cell A is selected. If a-I _Gmin is flowing through B ₁₁ 24, GS ₁ 39 switches to voltage and the read line S
_A voltage is generated across _{1 1} 21. This state is "0". Also, if you are the I _Gmin flows in if B ₁₁ 24 GS139 is voltage across the read line S ₁ 21 remain in superconducting state will not occur. This state is "1". As a result, B ₁₁ 24
The information of the A cell can be read nondestructively in accordance with the value of the current flowing in the cell. The cell A has been described above, but the reading operation is performed on the other cells on the same principle. For example, when reading the information of the D cell, a current having a value of d is supplied to S ₂ 22 and a current of b is supplied to X ₂ 20. At this time S ₂ 22
Two states can be discriminated by whether or not a voltage is generated at both ends of.

Although 4 bits have been described above, 1 × m bits can be stored by forming a 1 × m matrix array.

As a result, a superconducting memory system and a superconducting memory circuit that can store binary information can be realized by changing the current path.

(Effect of the Invention) According to the present invention, the operation of writing "1" can be achieved by temporarily passing a signal current to the signal line Y1 and the signal line X at the same time.
That is, the amount of operation of the signal current at the time of writing "1" is reduced. As a result, it is possible to simplify and speed up the "1" write operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a superconducting memory circuit according to the present invention, FIGS. 2 (a) and 2 (b) are diagrams showing control characteristics of a write gate used in the superconducting memory circuit of the present invention, and FIG. FIG. 4 is a diagram showing a control characteristic of a read gate used in the superconducting memory circuit of FIG. 4, and FIG. 4 is a circuit diagram showing an array configuration of a 4-bit Josephson junction high speed memory circuit for showing an embodiment according to the present invention. FIG. 5 is a circuit diagram showing a conventional superconducting memory circuit. In the figure, 1 is a bias line B, 2 is a signal line Y ₀ , 3 is a signal line Y ₁ , 4 is a signal line X, 5 is a read line S, and 6 is a branch.
B ₀ , 7 are branches B ₁ , 8 is a branch point P, 9 is a junction point Q, 10 is a write gate G ₀ , 11 is a write gate G ₁ , 12 is a read gate GS, 13 is a bias line B ₁ , 14 Bias line B ₂ , 15 is signal line Y ₀₁ , 16 is signal line Y ₁₁ , 17 is signal line Y ₀₂ , 18 is signal line Y ₁₂ , 19 is signal line X ₁ , 20 is signal line X ₂ , 21 is read Line S
₁ , 22 is read line S ₂ , 23 is branch B ₀₁ , 24 is branch B ₁₁ , 25
Is branch B ₀₂ , 26 is branch B ₁₂ , 27 is branch B ₀₃ , 28 is branch B ₁₃ ,
29 is branch B ₀₄ , 30 is branch B ₁₄ , 31 is write gate G ₀₁ , 3
2 is a write gate G ₁₁ , 33 is a write gate G ₀₂ , 34 is a write gate G ₁₂ , 35 is a write gate G ₀₃ , 36 is a write gate G ₁₃ , 37 is a write gate G ₀₄ , 38 is a write gate G ₁₄ , 39 Is the read gate GS ₁ , 40 is the read gate GS ₂ , 41 is the read gate GS ₃ , 42 is the read gate GS
₄ , 43 is the signal line Iy, 44 is the first branch, 45 is the second branch, 4
6 is a write gate, 47 is a signal line Ix, 48 is a signal line I _Y ′, 4
9 is a read gate, 50 is a read line Is.

Claims (1)

[Claims] 1. A first inductor having an equal inductance, which connects a point where a superconducting current flows and a point where a superconducting current flows out.
And a second superconducting line, a first write gate provided in the middle of the first superconducting line, a second write gate provided in the middle of the second superconducting line, and a first A first signal line electromagnetically coupled to the write gate, and a second signal line electromagnetically coupled to the second write gate,
A read gate that is electromagnetically coupled to the first superconducting line, a read line in which the read gate is disposed, a first and a second write gate, and a third that is electromagnetically coupled to the read gate. Has a signal line of, and at the time of writing, a current is caused to flow through the first and third signal lines or the second and third signal lines to momentarily bring the first or second write gate into a voltage state and then superconducting. Returning to this state, the current flowing in the superconducting line provided in the middle of this write gate is smaller than the current flowing in the other superconducting line and is not zero, and the difference in the current values of both lines is discriminated by the read gate. The read gate is in a superconducting state or in a voltage state by flowing a current through the read line and the third signal line during reading. Superconducting storage circuit, characterized in that for reading stored contents.