JPH01192087A - Josephson memory cell - Google Patents

Abstract

PURPOSE:To make an inductor unnecessary a circuit current line to two points in a superconductive closed loop, and inserting a prescribed number of Josephson devices in series to the right and left branch loops of closed circuits separated setting the two points as a boundary, respectively. CONSTITUTION:The circuit current line 12 is connected to the two points P1 and P2 in the superconductive closed loop 11 which forms a memory cell, and one Josephson device Jo, etc., of integer k=1 of one or more to be inductively coupled with a control current line 13 is inserted in series to the left branch loop separated setting the points P1 and P2 as the boundary, and integer (m) more than three of Josephson devices (J1-Jm) to the right branch loop in series. Thereby, four or more Josephson devices are inserted in series to the loop 11, and the sum of the phase differences at the ends of the devices (Jo-Jm) goes to at least 2npi, and the current can be branched to a right and left branch circuits without using inductance to generate signal delay, etc., and no inductor can be required in the memory cell. As a result, the constitution of the memory cell can be miniaturized, and high performance is attached.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a magnetic flux quantum memory type Josephson device that can selectively store binary logic information depending on whether or not magnetic flux quanta are captured in a superconducting closed loop. - Concerning improvements in memory cells.

[Prior Art] Among the Josephson memory cells of this type that have been proposed in the past, the one with the simplest structure and the one that can be driven with unipolar drive current is the one made by Kogannin. The already proposed Special Publication No. 60-20840 (Patent No. 1,
No. 294,806).

Details regarding this cell are left to reference to the same publication, but to briefly explain it in this book, a typical and basic configuration example thereof is as shown in the fourth figure.

First, inside this Josephson memory cell lO,
Two Josephson elements J. There is a superconducting closed loop 11 including +JI and an inductor R intentionally designed to a sufficient value, and in order to selectively flow the external circuit current 1y into this superconducting closed loop 11, there are two points PI and P2.
External circuit current lines 12 and 12 are connected at.

Therefore, the connection point PI of the circuit current lines 12, 12.

Looking at P2 as the boundary, the superconducting closed loop 11 can be divided into a left branch circuit (left branch) and a right branch circuit (right branch), and the left branch includes a unit Josephson element J.
. is included, and the right branch includes a series circuit of an inductor L and a unit Josephson element J.

Motoko Josephson J on the left branch. In this case, the Josephson element JO can be selectively switched between a zero voltage state and a voltage state depending on the case, depending on the presence or absence of an externally applied control current, or alternatively, as a cell configuration. A control current line 1 for flowing the control current Ix so as to cause a so-called portex transition (instantaneous state transition and immediate return to the original state).
3 are inductively coupled.Furthermore, in order to realize the memory operation described later without any inconvenience, damping resistors R, , ,
R2 is connected.

In the cell 10 having such a configuration, it is difficult to determine whether or not magnetic flux quanta are trapped in the superconducting closed loop ll, in other words, whether or not there is a permanent current flowing due to the presence of the magnetic flux quanta. 1. The binary logic of stored information is defined depending on whether or not it exists, but for convenience,
As shown by the imaginary line in Fig. 4, the case where a permanent current 1eir flows in the direction of the arrow (clockwise) in the superconducting closed loop ll corresponds to the stored state of logic "1", and the case where it does not flow corresponds to the stored state of logic "1". Corresponds to the storage state of logic "0".

However, writing of the logic "θ" is performed by simply passing a control current Ix of a predetermined magnitude only through the control current line 13 and then returning it to the original state (setting it to zero).

The state of the cell before this operation is logic "0", and a permanent current fair flows in the superconducting closed loop 11.

If not, even if the control current I× is applied, the result is essentially the same as if nothing had happened,
After the control current Ix falls, no permanent current cir is generated in the superconducting closed loop ll, so that a logic "0" storage state can be achieved.

On the other hand, if the cell state before the logic "0" write operation is a logic "1" storage state and a permanent current Ic1r is flowing in the superconducting closed loop ll, then the values of the damping resistors R, , R2 By passing through the cell, the memory contents of the cell 10 can be rewritten to "0" using portex transition.

That is, when a permanent current of 1elr is flowing,
The threshold curve for the cell is different from that when no current is flowing, and the application of the control current Ix allows the Josephson element J in the left branch to transition to a voltage state even momentarily. This Josephson Motoko J.

Both ends p, , p, are shunted by the superconducting branch circuit of the right branch, but since the Josephson element is also a nonlinear inductance element, a voltage is actually generated momentarily across the Josephson element Jo. Afterwards, it returns to the zero voltage state.

Therefore, at the timing when this Josephson element Jo transitions to the voltage state, the permanent current flowing in the superconducting closed loop flows away to the circuit current line 12.12, and the state inside the cell changes as described above. As before, the logic “
Similarly to when a logic "0" was stored, the threshold curve for the cell IO follows that when a logic "0" is stored.

This is a portex transition, and therefore, if this control current Ix is subsequently reduced, a state in which magnetic flux quanta are not captured in the superconducting closed loop 11, that is, a memory state of logic "0" in which no permanent far current fair is flowing, is achieved. can be made.

Incorporating logic "1" means that after the control current lx flows in the above, the circuit current 1y also flows, and while this circuit current 1y continues to flow, the control current lx is first lowered, and then the circuit current ■y This is done by lowering the .

In this way, if the previous cell memory content was logic "0", the control current fx and the circuit current y cause the Josephson element Jo to transition to the voltage state, and then the circuit current ty changes to the right The energy necessary for generating at least one magnetic flux quantum is stored in the inductor LR, and therefore, if the circuit current 1y is removed after the control current Ix falls, there is no permanent flow in the superconducting closed loop 11. The current fair will remain, and if the previous cell memory content was logic "1", the aforementioned portex transition will occur with the first application of control current lx, and the memory content will become "0".
'', so in the end, as above, the current is supplied as a circuit current using the same mechanism as when the previous cell content was ``0'' and the stiffness is rewritten to logic ``1''. The current component can be left in the superconducting closed loop as a permanent current 1elr, and a state in which magnetic flux quanta are captured, that is, a storage state of logic "1" can be achieved.

For reading, contrary to the above writing, first the circuit current I is
This is done by flowing control current lx after flowing y,
Whether the stored binary logic information was “0” or “1”
’, at that time, the pair of circuit current wires 1
This is determined by whether or not a voltage is generated for a significant period of time between 2 and 12.

If the cell IO stores a logic "0", that is, if the permanent current 1air is not present in the superconducting closed loop 11, the Josephson element J in the left branch.

Regarding, the direction of the current induced by the control current ■×,
In the circuit current 1y, the direction of the shunt flowing through this left branch is the same, so the Josephson element J. After switching to the voltage state, the Josephson element J in the right branch also transitions to the voltage state due to the interference effect, and the state of the entire cell changes to the voltage state (between the pair of circuit current lines 12 and 12). (a voltage of a significant value is generated),
The logic "0" can be read.

On the other hand, if cell lO stores logic "1",
Regarding the Josephson element JO in the left branch, the direction of the left branch branch of the circuit current ty and the permanent current Ic1r
This Josephson element J
. This can create a state in which the cell does not switch to a voltage state, and therefore the cell as a whole remains in a zero voltage state, and no significant value of voltage occurs between the pair of circuit current lines 12.12. It is possible to read the logic "1'" by

[Problem to be solved by the invention]
Memory cell 10 was clearly superior to previous Josephson memory cells of this type.

For example, the control current lx and the circuit current Iy can be unipolar, which greatly simplifies the configuration of the peripheral drive circuit, and in principle, the number of external lines can be kept to two (12, l: l). This is because it is extremely advantageous when integrating, not only making it possible to reduce the overall size, but also being advantageous in terms of manufacturing.

However, in the course of experiments for the subsequent practical application of the present invention, it was found that there was still room for improvement in the above-mentioned Josephson memory cell produced by the present applicant.

As in the above-mentioned Josephson memory cell, at least two Josephson elements J are included in the superconducting closed loop 11. , J.
In the case where an inductor LR is required in order to obtain magnetic flux quantum generation energy or to obtain a magnetic flux quantum interference effect, the existence of the inductor LR itself may be detrimental in various ways.

First of all, in general, in order to obtain the required amount of inductance in a Josephson circuit, this inductor must be made as a line section having a fairly large physical area, and therefore The inductor R has the disadvantage that it imposes an upper limit on miniaturization of the cell as a whole. Particularly in recent years, when it has become possible to miniaturize the Josephson element itself to about 0.5 μm, the size of the area required to form the inductor LR becomes noticeable.

On the other hand, in terms of design and characteristics, the presence of this inductor resistance sometimes makes it difficult to obtain desirable results.

For example, the complicated relationship between inductance and the current density of a Josephson element has hindered the improvement of design efficiency and inhibited the degree of freedom.Due to the difference in frequency response between a Josephson element and an inductor, Attempting to operate at high speeds tended to cause problems with stability.

This is due to the damping resistance R,
, R, there is a limit to this damping effect, so it was a fundamentally unsolvable problem.On the contrary, it was difficult to derive design conditions for such resistance values, The effort required to actually create the resistor has become troublesome. This is by no means desirable for constructing an extremely high-density Josephson memory space in the future.

In the first place, although it uses a Josephson device, which is originally an element capable of extremely high-speed switching operation,
It was rather unethical that the presence of the inductor R would cause a propagation delay in the signal.

Based on this viewpoint, the present invention aims to further improve the Josephson memory cell shown in the above patent, eliminate the various drawbacks mentioned above, and provide a basic cell structure that is even smaller and has higher performance. It is something.

[Means for Solving the Three Problems] In the Josephson memory cell disclosed in the above-mentioned Japanese Patent Publication No. 60-20840, current was shunted into left and right branch circuits using inductance.
To perform a similar current shunting function, the idea was to utilize the phase difference between multiple Josephson elements in a series circuit. Simply put, the inductor in the above conventional example is replaced with a series configuration of a plurality of Josephson elements.

However, in the most advanced cases, the sum of the phase differences at both ends of at least each Josephson element (
Since the total phase difference (loop-to-cycle phase difference) must be 2nπ, there is a lower limit to the total number of Josephson elements to be used, and the minimum number of Josephson elements connected in series in the blood conduction closed loop is four. When constructing a superconducting closed loop from only Josephson elements without using an inductor,
Unless there are four or more, the phase difference will not be 20π. Therefore, if one of them is inductively coupled to the control current line in the left branch, the number of Josephson elements to be included in the right branch will be three.

However, on the contrary, as long as the number is greater than or equal to the above minimum number, the number can be increased quite arbitrarily, as will be understood from the embodiments described below.

The main structure of the Josephson memory cell of the present invention can be summarized as follows.

Connect circuit current lines to two points of the superconducting closed loop, divide the superconducting closed loop into left and right branch circuits using the two points as a boundary, and: With k being an integer of 1 or more, one of the left and right branch circuits is connected to the superconducting closed loop. A number of Josephson elements are inserted in series in the branch circuit; an external control current line is inductively coupled to at least one of the number of Josephson elements; m is an integer of 3 or more; A Josephson memory cell characterized in that the m Josephson elements are inserted in series.

[Function] To simplify the understanding of the function of the Josephson memory cell of the present invention, for m in the above summary structure, first =
1. Assume that m≧3, and therefore the number of Josephson elements to which the control current line is inductively coupled is also − (k=1), and that the branch circuit containing these Josephson elements is the left branch.

Magnetic flux quanta are captured in the superconducting closed loop, causing a permanent current (
As in the explanation regarding the previous conventional example, when the current Icir is flowing, it is assumed to be the storage state of logic "1", and when a significant voltage value appears between a pair of circuit current lines in the read mode, that is, when the cell If we define the reading of logic “0” as when the transition to the voltage state, then the selective write and read operations of logic “0” and “1” are substantially the same as the fourth one described above.
It may be similar to the illustrated Josephson memory cell.

When the value of the control current (referred to as Ix) that is selectively passed through the control current line inductively coupled to one Josephson element in the left branch is designed, the logic 1a OII can be written using only the control current lx, In addition, to write logic “1”, the control current lx is applied and then the circuit current (
This can be done by a sequence of flowing the control current Iy), decreasing the control current lx, and then decreasing the circuit current Iy.

For example, the cell state before the above write operation is logic “0”
It is clear that if the storage state was , the above operation regarding writing a logic "0" would not cause any change. Qualitatively speaking, in a state where there is no circuit current ty and no permanent current 1e I'r, the application of the control current lx will cause the control to occur no matter what happens to the Josephson element in the left branch. After removing the current lx, it is easy to return to the original state, leaving a permanent current Ic1r in the superconducting closed loop that is closed afterwards.

On the other hand, if the cell state before the write operation is a storage state of logic "1" and a permanent current fair is flowing, the portex transition described above can be used. That is, in order to store the logic “0”, the control current [x
, causing an instantaneous voltage transition in the Josephson element inductively coupled to this control current line, causing a permanent current 1elr to flow through the circuit current line, and then reducing the control current lx. Logic "0" can be rewritten.゛When writing logic “1”, the previous cell state is changed to logic “1”.
1", the permanent current Ic,...
flows away to the circuit current line, the cell becomes substantially once in a state equivalent to the logic "O" storage state described above, so that the logic "1" is changed from the logic "0" storage state described above.
The sequence is similar to the sequence in which the memory state of "1" is maintained, and the memory state of logic "1" is maintained as expected.

In contrast to these write operations, in the read operation, as in the conventional example described above, the circuit current Iy is caused to flow, then the control current lx is caused to flow, and then the sublayer current IX is first brought down, and the retention current 1. By lowering , substantially non-destructive reading can be performed.

In other words, if the control current lx is applied while the circuit current ry is applied, if the memory contents of the cell become logic "1".
When a permanent current Iel'r is flowing, this permanent current Iel'r is equal to the applied circuit current shunt with respect to the inductively coupled Josephson element of the control current line. Since the current component is in the opposite direction to the control current and control current, it is possible to create a situation in which the Josephson element does not transition to the voltage state, and when looking at the cell as a whole,
The content of this logic "1" can be read because the superconducting state is maintained and the circuit current line voltage is continuously zero. Moreover, since there was no change in the cell state, after the control current IX and the zero warning current 11 fell,
The cell can maintain a logic "1" storage state.

When the memory content of the cell is logic "0", the synergistic effect of the control current lx and the circuit current xy causes the Josephson element in the left branch whose critical current value is reduced by the control current Ix to be in a voltage state. Therefore, after that, all the circuit current Iy flows into the Josephson element series circuit in the right branch, so these m Josephson elements in series transition to the voltage state, and as a result, the entire cell also transitions to the voltage state. do.

Therefore, the logic “
0", the circuit current Iy is lowered (generally returned to zero) and the control current Tx is also lowered (generally returned to zero) to prevent magnetic flux quanta from being trapped in the superconducting closed loop. can be returned to a non-superconducting state,
Equivalent non-destructive reading can be performed.

However, the present applicant has also separately proposed an improvement in the method of driving a Josephson memory cell having the configuration shown in FIG.
Regarding the application sequence of the control current and the circuit current, a method has been developed in which the order is the same, but this driving method can also be adopted for the Josephson memory cell consisting only of the Josephson element of the present invention. Can be done.

In other words, the Josephson memory cell according to the present invention is basically functionally compatible with the Josephson memory cell shown in FIG. 4, and more effectively eliminates only its drawbacks. I can say that I got it.

To put it simply, the Josephson memory cell of the present invention does not require an intentionally formed inductor or damping resistor, which is found in the conventional example described above, and does not require any wiring paths between elements. Although the inductance that is intentionally formed is unavoidable to some extent (in fact, it can be ignored),
In principle, a superconducting closed loop containing only Josephson elements can be used to store binary logic.

Therefore, various remarkable effects can be achieved, which are summarized at the end of the article.In the next section, through examples of the present invention,
For understanding of the present invention, a more detailed explanation will be provided.

Embodiment FIG. 1 shows a typical or basic embodiment of a Josephson memory cell constructed in accordance with the present invention.

However, in order to correspond to the conventional example shown in FIG. 4, the same reference numerals are used for corresponding components.

In fact, when the Josephson memory cell IO shown in the figure includes one Josephson element JO in the left branch, the Josephson element J in the right branch in the conventional example shown in the fourth figure, and the inductor R. A series circuit consists of a plurality of m Josephson elements Jl + J2 +...
・Replace with +J1m and damping resistance R,, R,
This is also because what could have been omitted would be the Josephson memory cell shown in FIG. 1 as an embodiment of the present invention.

First, the static configuration of the Josephson memory cell IO in this embodiment will be explained.
In the memory cell IO, there are − Josephson elements Jo and 3
m Josephson elements Jl e J that are an integer greater than or equal to
There is a superconducting closed loop 11 consisting only of It is intentionally designed not to form either an inductance component or a resistance component.

In practice, if each Josephson element is formed to have a width of, for example, 0.5 μm or less, no significant inductance will be formed in a wiring path with a line width commensurate with this, and it can be considered to be negligible. .

However, in order to selectively flow the external circuit current ly into the superconducting closed loop 11 as described below as necessary, the external circuit current lines 12 and 12 are connected at two points p, , p2 on the loop. Connected.

Therefore, the connection point p of this circuit current line 12.12, ,
If we look at p2 as the boundary, we see a superconducting closed loop l! can be divided into a left branch circuit (left branch) and a right branch circuit (right branch), and in this example, (k=) in the left branch
One unit Josephson element J0 is included, and m Josephson elements J, , J, , are included in the right branch.
..., Jl series circuit is included.

Motoko Josephson J on the left branch. This Josephson element J depends on the presence or absence of an externally applied control current lx. The control current line 13 for passing the control current lx is inductively coupled so that the control current lx can be selectively switched between a zero voltage state and a voltage state, or the so-called portex transition described above can occur. are doing.

In the Josephson memory cell IO of the present invention having such a basic configuration, in order to ensure reliable operation and to provide a wide operating margin, it is necessary to follow the design example described below with reference to FIG. Critical current value I of each Josephson element
It is good to set m etc. to 0 or the number, but here first,
Assuming that the cell 10 shown in the first figure has such a desirable design, the operation of the Josephson memory cell of this embodiment will be explained using the threshold curve shown in the third figure.

Here, when magnetic flux quanta are captured in the superconducting closed loop 11 and a permanent current fcir exists in the clockwise direction as shown in the figure, it is defined as a storage state of logic "1", and therefore a storage state of logic "0". The state is such a permanent far current ■e
Assume that there is no Ir.

Also, 1x of this Josephson memory cell shown in FIG.
In the −1yL threshold characteristic, the curve C(O) is the cell lO
Curve C(1) is the threshold curve when the cell IO stores the logic "0", and the curve C(1) is the threshold curve when the cell IO stores the logic "B". This is the region where a so-called portex transition can occur.The operating margin is essentially the curve C(0), C(
1) becomes larger as they are farther apart from each other in the ly-axis direction,
As shown in the design example described below, the maximum critical current value ratio on the Iy wheel axle can be increased to about 1.5 times.

Furthermore, in Fig. 3, points a are sequentially clockwise from the origin 0.
, b, and c to return to the origin 0 is a path along which the control current lx and circuit current ry go back and forth in a predetermined manner in write mode and read mode. be.

First, considering writing logic "0", this means, for example, simply flowing a control current 1x=c (Fig. 3) of a predetermined magnitude only through the control current line 13, and then returning it to the original state (reducing it to zero). ) just by operating it.

For convenience, the operation of flowing the control current lx from the origin 0 to the amount corresponding to point C in FIG.
The operation to return to is expressed as "I×\". Similarly, the circuit current 1
Regarding y, the operation of causing the circuit current 1y to flow up to the value of Iy-a is expressed as "I31/", and the operation of returning it to zero or the origin 0 is expressed as "Iy\".

Therefore, the logic “0” write operation sequence 0 above is: @=Ix/=>IxX.

It can be expressed as The congruence symbol "Mi" indicates that the content of the sequence ■ is as shown in the right column,
The arrow symbol "u" indicates the order of operations. The same conventions regarding these symbols apply below.

In this way, if the state of the cell 10 before this operation is logic "0" and the permanent current Ic1r is not flowing in the superconducting closed loop 11, then as shown in FIG. The current trajectory that reaches point C and returns to the origin 0°
becomes. If this current trajectory is set to 0°, ■ゝmi0埠c ->.

However, as can be seen by tracing this trajectory, for cells in the storage state of logic "0", the threshold curve C(0) is not crossed at any point, so the contents of cell lO does not affect or make any changes. Therefore, when exiting write mode (
After the control current lx falls), the memory content of the cell 10 is "0", and conversely, the logic "0" is stored as expected.
This means that you can write .

On the other hand, if the previous cell content was logic "1" and a permanent current of 1 cir existed, the characteristic curve shown in FIG. When “o => c” at °, point R in Fig. 3
It is now written to a logic "0" because it crosses the portex transition region of threshold C(t), indicated by the dotted line at .

In other words, the Josephson element J in the left branch when the control current lx equal to or higher than the predetermined value R is applied. momentarily changes to the voltage state, and the permanent current IcI, . . . flows away to the circuit current +1!1112, thereby substantially becoming a logic "0" write state.

If logic “0” is written, the contents of the cell will not be as expected after the write mode ends due to the fall of the control current ×, since no threshold curve will be crossed during the return path of “c => o”. The logic becomes "0" as expected.

Next, considering the writing of logic "1", the operation sequence (2) can be set as (1)=lx/1y/->1x-1y%.

If you follow the thick line path in Figure 3, the current trajectory at this time ■°
becomes ■'=o6c:3b=>a6°.

The cell content before this write operation is logic “0”,
If the threshold curve C(0) in FIG. In the process, the curve C(0
) is crossed from bottom to top at point P, so cell lO
A logic "l" is written into the register.

In this process, point Q is also crossed from bottom to top in the figure by 7
However, since this point Q is on the threshold curve C(1) for logic "1", it is irrelevant.

Once the magnetic flux quantum is captured in the superconducting closed loop ll as described above, during the above sequence
By setting “x input −> Iy −”, the corresponding logic “
It is possible to exit the write mode while retaining the memory state of 1".In terms of the current trajectory, the threshold curve follows curve C(1) at the point when point P is crossed from bottom to top. Therefore, the following “b => a => o”
This is because in the process of becoming a cell, it no longer has any effect on the cell.

If the memory content of the cell 10 is logic "1" before starting the logic "L" write mode, the logic "1" is restored to its original state substantially according to the rewrite procedure from destructive read.
1” is re-memorized.

That is, according to the above sequence ■, in the process of "O->C" in the current trajectory ■°, the threshold curve (: (1) shown by the dotted line is crossed from left to right at point R, so Due to the portex transition described, the cell once becomes logical “
It is set to a storage state of 0''.

If this happens, the subsequent process will be similar to the rewriting process from the memory state of logic "0" to logic "1", and the next "Iy
In the process of the current trajectory part “c => b” accompanying “/”, the curve C(0) is crossed from bottom to top at point P, so
A logic "1" is written in the cell 10, and then during the above sequence (2), in the process of "b => a 6 o" accompanying the subsequent "lx\=>Iy\", the logic "1" is stably written. You can exit the write mode while retaining the memory state of ``.

On the other hand, the readout sequence (■) under the readout mode can be made as follows (■=Iy/啼lx/啼lx−啼Iy−), and therefore the current trajectory 0゛ at this time is ■'=o6aab=OL=> .

becomes.

Here, if a permanent return current of 1 clr flows in the superconducting closed loop 11 of the cell lO, that is, if logic '1' is stored, then the first 'Iy
The path "o => a ->b" associated with "/61 The cell 10 maintains a zero voltage state without causing any problem, and can determine this as a logic "1" readout, and then returns to its original state through the subsequent "b:>&:>O" path. If the cells are returned to normal state, the cell contents remain unchanged.

On the other hand, if the memory content of the cell IO is logic "0", the operation will naturally follow the threshold curve C(0) in FIG. Iy/:
The path “o 6 a => b” accompanying 31

In fact, the above operation sequence and the accompanying mechanism itself are the same as those of the conventional cell already explained with reference to FIG. The difference is that it does not require an inductor or resistor to perform these similar functions, and sufficient stability can be ensured.

However, the Josephson memory cell of the present invention also has a fourth
The Josephson memory cell in the conventional example shown is also
Operations according to other operation sequences disclosed separately by the applicant are also possible.

For example, in the above operation sequence, logic “1”
The write operation sequence ■ and the read operation sequence ■ follow different orders9. In principle, there is no problem with this, but in reality, the control current lx is selectively changed at a predetermined timing. When constructing a peripheral drive circuit system that generates or removes the control current Ix and the circuit current 1y, a delay circuit or the like is used to control the control current Ix and the circuit current 1y.
The order of occurrence of y is often different, and the circuit configuration itself tends to become complicated.

Therefore, for example, by changing the current value of the circuit current 1y instead of the order, it may be possible to distinguish between the write mode and the read mode even in the same order. It can be easily explained as follows.

In the above, the logic "1" write sequence ■ is ■=lx/->Iy/埠I×＼■y＼,
On the other hand, the read sequence O is 0=Ty13Ixz'
>IxX, ->ry%, and the relationship between application and removal of lx and Iy was exactly reversed.

However, for example, here, the circuit current x
With respect to the value Yr of y, the value Y of the circuit current 1y applied when writing a logic "1" is made smaller, and the point a shown in the third diagram when writing a logic "1" is lowered. If the current path for the current is made to cross the portex transition region shown by the dotted line of the threshold curve C(0) from left to right, a logic "1" can be written in the same sequence as the sequence 0 during reading. Become so.

Furthermore, in the case shown in the figure, the operation is performed exclusively in accordance with the first quadrant of the threshold characteristic, but operation in the fourth quadrant is also possible if necessary, and operation in other quadrants is also possible depending on the conditions. It's not possible. Of course, in that case, unless the control current Ix, the circuit current, and the road current Iy are both in the negative region in the third quadrant utilization type, the effect of maintaining the unipolarity of all current value relationships will be sacrificed. become.

Next, a design example for realizing the Josephson memory cell of the present invention will be described for reference.

As shown in Figure 1, regarding the permanent current Lir, the clockwise direction is positive, and the permanent current ■eIr for the left branch is the current I1 flowing from the bottom to the top in the figure, and for the right branch it is the current flowing from the top. Let the current flowing downward be IR.

Moreover, each Josephson element J that constitutes the superconducting closed loop 11. , Jl, J2, ......, J, respectively, represent the phase differences as θ. , θ1. θ2.・
..., 01, each Josephson element J. ＋Jl
+ J2 +..., J, each critical current value ■.

+Il+12+...+1m.

Essentially, the critical current value of each Josephson element is 10,
l, , I2. Although an optimal design is possible even if +L are all different, here, to simplify the calculation, we first calculate each of the m Josephson elements J1 in the right branch.
．． ......, J, are all the same critical current value 1s
Assume that there is all. This ultimately means that the m Josephson elements all have the same phase difference OR.

However, in order to generate an eternal far current 1e1r,
At least the phase condition within the superconducting closed loop 11 is 0°+0. ＋－－－－－＋0. =θ. 10m・0R=2
rrK; However, n=earth 0. ±1. ±2.・・・・・・
・・・・・・・・・(1) Must be (if n-0, permanent current ■.
(corresponds to the case where r does not exist).

On the other hand, considering that the circuit current [y] flows in the direction shown in the superconducting closed loop lO, the permanent current component IL flowing through the Josephson element in the left branch is in the opposite direction, so Iy= -IL+ l*= -1,・5inO0+I
-R-sinO.

・・・・・・(2) 1,=IC,,=10・sing.

・・・・・・(3) The following formula can be given.

Furthermore, aiming for the simplest design, all Josephson elements in the left and right branches have the same critical current value (
■. ” I−R), and when there is a permanent return current of 1 clr, the phase difference is 2π, that is, n
= 1, and from the above equations (1) to (3), ■e1. ．． =:I0・Sin[2d(m+1)]...
...(4) is obtained, and conversely, this equation is the permanent return current ■. The minimum current value that must be passed through the right branch (necessary for writing a logic "1") to obtain 1. . You can also think about it.

Based on these formulas, the result of calculation using the number m of Josephson elements included in the right branch as a parameter is the second
As shown in the figure.

In this figure, the current value Lee required to write the logic "1" and to be applied to the right branch is the critical current value (■) of each Josephson element. The ratio of the critical current value of the cell when storing logic "0" and when storing logic "1" is 1y(1
)/Iy(0) was also calculated and shown.

In addition, the maximum value I of the critical current value of the cell when storing logic “1”
On the threshold curve in FIG. 3, y(1) corresponds to the ty-axis intercept of the solid threshold curve C(1), and similarly corresponds to the critical current value of the cell when storing logic "0". Maximum value 1y(0
) is the solid threshold curve C on the threshold curve in FIG.
Corresponds to the ty-axis intercept at (0).

The first thing that becomes clear from Fig. 2 is that the ratio 1y(1)/Iy(0), which can indicate the size of the operating margin, does not change as the number m of Josephson elements in the right branch changes. Desirably, it is about 1.5 times as much.

On the other hand, in the above, for simplicity, the critical current value of all Josephson elements in the right branch is assumed to be the same, but in general terms, the supply current value to the right branch required to memorize a logic "1" is 1 me , , must naturally be smaller than the critical current value of the Josephson element that has the smallest critical current value among the Josephson elements included in the right branch.
From the viewpoint of operational margin, a value of at least half of the critical current value is desired.

Too small a value is undesirable in terms of signal-to-noise ratio characteristics.

Therefore, even in the case of this calculation example, the critical current value I. Looking at the upper limit of the number m in the range where it is more than half of , m≦
It can be seen that 10 is desirable.

However, the above calculation example is just an example of a simple design example, and is not an essential requirement for realizing the present invention. On the contrary, now that the present invention has been disclosed, those skilled in the art will be able to optimally design each case.

For example, inferring from the above design example, if the minimum number of Josephson elements (k+m) in the superconducting ° loop necessary to satisfy the phase difference of 2nπ is 4 or more, the number can be increased quite arbitrarily. The number of Josephson elements Q included in the left branch is not limited to one, but may be two or more, as long as the control current line 12 is operably connected to at least one of them. In this case, even if = 2, for example, there is no necessity that the lowest value 3 for the number m of Josephson elements in the right branch will be doubled to 6, and (k
It is sufficient that the sum of the phase differences of + m ) Josephson elements is 2nπ in a loop.

Rather, when it comes to increasing the number of Josephson elements used, the upper limit is determined by design, not by the theoretical upper limit, but by practical and practical conditions that do not need to increase the number unnecessarily. good. If you increase the number of remainders,
Although the Josephson memory cell of the present invention does not require a resistor or inductor and can be made from only extremely small Josephson elements, it does not allow for significant miniaturization, and the three-dimensional structure is troublesome to manufacture. This is because a multilayer structure or the like may be required.

In addition, in the operation sequence of the above embodiment, as shown in particular in the writing of logic "0", this Josephson
Since the memory cell can write logic "θ" only with the control current Ix, the Josephson memory cells are actually arranged in X rows and Y columns to form a two-dimensional memory space.
When the X-Y matching address method is adopted, multiple cells connected to the same control current line 13 are forcibly rewritten to logic "0" all at once when control current Ix is applied to this control current line. It may happen that you get lost.

To prevent this, the logic “O” or logic “
1'', other cells that are not targeted for writing must have a control current lx at least relative to the cell targeted for writing.
It is preferable to set it so that it becomes "ly/" before the timing when "lx/"' becomes "lx/"', that is, in accordance with the read mode.

[Effects] According to the present invention, various remarkable effects can be obtained as listed below.

■ Since the operating conditions are determined only by the quantum interference effect of the Josephson element, there is no need to use complicated design methods that take into consideration the values of inductance and damping resistance, which is required in the past, making the design extremely simple. In addition to simplifying the process, it also increases the degree of freedom in design.

■ Since there is no need for an inductor or resistor, which requires a fairly large area in order to obtain the required value of inductance, the positive effects of Josephson element miniaturization can be enjoyed as is, making it possible to create an extremely compact memory.・Can provide cells.

■ Since an inductor with high frequency dependence is not used, the rise and fall characteristics of external control signals and circuit current signals are not slowed down, and the inherent super-speed characteristics of Josephson elements can be fully utilized.

■ Since the superconducting closed loop in which a permanent current should flow is a strongly coupled loop that does not include inductance, it is possible to eliminate the so-called gray zone where switching conditions become unstable.
High stability can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a Josephson memory cell showing a preferred embodiment constructed according to the present invention, FIG. 2 is an explanatory diagram of a design example, and FIG.
Figure 4 is an explanatory diagram that explains the operation of a memory cell using an example of a threshold curve.It is considered to be the most excellent of the magnetic flux quantum memory type Josephson memory cells that have been proposed so far. 1 is a schematic diagram of a representative example; FIG. In the figure, 10 is the Josephson memory cell as a whole, 11 is the superconducting closed loop, 12 is the circuit current line, 13 is the control current line, JO+JI+..., Jl is the Josephson element, [X is the control Current, ty is circuit current, Ic1r
is a permanent current. Designated agent: Agency of Industrial Science and Technology National Institute of Electronics and Technology Long circuit current (Y selection current) Iy Circuit current (Y selection current Hy

Claims (1)

[Claims] A circuit current line is connected to two points of the superconducting closed loop, and the superconducting closed loop is divided into left and right branch circuits using the two points as a boundary, and: where k is an integer of 1 or more, the left and right branch circuits are The k Josephson elements are inserted in series into one branch circuit of; an external control current line is inductively coupled to at least one of the k Josephson elements; m is an integer of 3 or more; A Josephson memory cell characterized in that: the m Josephson elements are inserted in series in the other branch circuit.