JPH04137749A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To realize high integration by arranging a part of wiring, congested in wiring areas, in a peripheral cell area. CONSTITUTION:A wiring 6 connecting between an R/L(random logic) section 1 and the part lower than the upper side of an MUC section 2 and a wiring 6 connecting between the MCU section 2 and the part upper than the lower side of the R/L(random logic) section 1 are congested in a wiring area 4 where the R/L section 1, the MCU section 2 and peripheral cell area 3 are located closely each other. Peripheral cells 5 are dislocated to an empty area 3 located closely to the congested wiring 6 and a part of the wiring 6 in the congested wiring area 4 is arranged in an empty area provided in the peripheral cell area 3 by dislocating the peripheral cells 5. According to the constitution, wiring density is increased in the wiring area and overall chip size is reduced resulting in high integration.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit.

[Conventional technology]

FIG. 2 is a layout diagram of a conventional semiconductor integrated circuit.

In Figure 2, (1) is the R/L (random logic) section, (2) is the MCU section, (3) is the peripheral cell area, and (4) is the MCU section.
) is a wiring area, (5) is a peripheral cell, and (6) is a wiring. Here, the R/L (random logic) section (1) and the peripheral cell (5) and the MCU section (2) and the peripheral cell (5) are connected, respectively, and the R/L (random logic section (1) and the MCU section (2) are connected via peripheral cells (5).

As shown, R/L (random logic) part (1) and M
The CU unit (2) is not directly connected and must be connected to the peripheral cell (5).
), the peripheral cells (5) from the R/L (random logic) unit (1) to the MCU unit (2)
) from the wiring (6) connected to the MCU section (2), the R/
L (Random logic) part (1), MCU part (2), and peripheral cell area (3) where the wiring (6) connected to the peripheral cell (5) on the random logic part (1) side gathers
In the wiring area (4) where the wirings (6) are close to each other, the wirings (6) are densely arranged.

Next, the operation will be explained. R/L random logic)
The R/L (random logic) section (1) and the MCU section (2) are connected to the peripheral cell (5), respectively.
The wiring connecting the CU section (2) is routed through the peripheral cell (5), so the R/L (random logic) section (
1) Wiring is densely arranged in the wiring region (4) of the MCU section (2) 9 in the vicinity of the peripheral cell region (3).

[Problem to be solved by the invention]

Since the conventional semiconductor integrated circuit is configured as described above, the width of the wiring area (4) is the same as that of the R/L (dumb logic) part (1) and the MCU part (2).

The peripheral cell area (3) is determined by the width of the adjacent wiring area (4), resulting in R/L (random logic)
There is a problem in that there is a vacant area where no wiring or layout is laid out in the wiring area other than the wiring area (4) to which the peripheral cell area (3) of the MCU unit (2) and the peripheral cell area (3) is adjacent.

This invention was made to solve the above problems, and includes an R/L (random logic) section (1),
It is possible to eliminate the empty area that occurs in the wiring area other than the area adjacent to the MCU section (2) 1 and the peripheral cell area (3), and it is also possible to increase the wiring density in the wiring area, reducing the overall size of the chip. The aim is to increase the degree of integration of semiconductor integrated circuits.

[Means to solve the problem]

The semiconductor integrated circuit according to the present invention has dense wiring (6) in a wiring area (4) adjacent to an R/L (random logic) part (1), an MCU part (2), and a peripheral cell region (3).
R
/L (random logic) section (1), MCU section (2) 9
It is possible to eliminate empty areas that have occurred in the wiring area (4) other than the peripheral cell area (3) or the adjacent wiring area (4).

[Effect]

The semiconductor integrated circuit according to the present invention eliminates the vacant area that has occurred in the wiring area (4).
) can improve the wiring density.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a layout diagram of a semiconductor integrated circuit according to an embodiment of the present invention. In the figure, (1) to (6) are the same as the conventional one, so explanations are omitted. In Figure 1, R
A peripheral cell region (3) is provided in which a /L (random logic) section (1) and an MCU section (2) are arranged, and peripheral cells (5) are arranged around them. The peripheral cell (5) has an R/L (random logic) section (1) and an MCU section (2).
) is connected by a wiring (6). Furthermore, a wiring region (4) is provided between the R/L (random logic) section (1), the MCU section (2), and the peripheral cell region (3) where the wiring (6) is arranged.

Wiring (6) is R/L (random logic) section (1)
It is used to connect the peripheral cell (5) and the MCU section (2) to the peripheral cell (5), and the R/L (random logic) section (1) and MCU section (2) are not directly connected. They are not overlapped and are connected using wiring (6) via peripheral cells (5).

Next, the operation will be explained. The R/L (random logic) section (1) is connected to the lower side of the upper side (the side on the R/L (random logic) section side) of the MCU section (2). wiring(
6) and the wiring (6) connecting from the MCU section (2) to the upper side of the R/L (random logic) section (1) (the side on the MCU section (2) side) is the R/L (random logic) section. (1) The peripheral cell region (3) of the MCU section (2) 9 is densely packed in the adjacent wiring region (4). The peripheral cells (5) in the peripheral cell area (3) that are close to this dense wiring (6) are moved and placed in the empty area in the peripheral cell area (3), and the dense wiring area is (4)
A part of the wiring (6) inside is arranged in a vacant area in the peripheral cell area (3) newly created by moving the peripheral cell (5).

〔Effect of the invention〕

As described above, according to the present invention, by arranging a part of the densely packed wiring (6) in the wiring area (4) in the peripheral cell area (3), Vacant areas (wiring areas where wiring (6) is not placed) can be eliminated.

Therefore, the wiring density in the wiring area (6) increases. Furthermore, since the peripheral cell (5) in the peripheral cell area (3) has only moved, the area of the peripheral cell area (3) does not change, and the area of the wiring area (4) that is no longer available is the same as that of the chip. The overall area is also reduced, which has the effect of enabling a highly integrated layout.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a layout diagram of a conventional semiconductor integrated circuit. In the figure, (1) is the R/L (random logic) section, (2) is the MC0 section, (3) is the peripheral cell area, (4) is the wiring area, (5) is the peripheral cell, and (6) is the peripheral cell area. It's the wiring. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Consists of a first functional block and a second functional block,
providing a peripheral cell placement area in which a plurality of peripheral cells surrounding the first functional block and the second functional block are placed;
A wiring area is provided between the peripheral cell placement area, the first functional block, and the second functional block, and the upper side of the first functional block and the lower side of the second functional block are connected to the wiring area. wires arranged adjacent to each other with the two functional blocks in between, and connected from the first functional block to the upper side of the lower side of the second functional block, or from the second functional block to the lower side of the upper side of the first functional block. A semiconductor integrated circuit characterized in that a portion of the wiring is arranged between the peripheral cells in the peripheral cell arrangement region.