JPH02306659A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02306659A
JPH02306659A JP12812589A JP12812589A JPH02306659A JP H02306659 A JPH02306659 A JP H02306659A JP 12812589 A JP12812589 A JP 12812589A JP 12812589 A JP12812589 A JP 12812589A JP H02306659 A JPH02306659 A JP H02306659A
Authority
JP
Japan
Prior art keywords
cell
data bus
cells
sides
macro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12812589A
Other languages
Japanese (ja)
Inventor
Koji Aono
青野 宏二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP12812589A priority Critical patent/JPH02306659A/en
Publication of JPH02306659A publication Critical patent/JPH02306659A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the degree of freedoms of wiring a data bus and disposing a cell and to perform an optimum layout by providing data bus input/output terminals on two opposed sides of a computer function cell and a macro functional cell. CONSTITUTION:In a standard cell type integrated circuit, input/output terminals 14-29 of data bus 10 of a computer functional cell 3 and macro functional cells 4-8, 12 are disposed at a predetermined internal from cell reference coordinates 13 on one sides of the outer peripheries of the cells and also symmetrically disposed on the opposed sides. That is, since the terminals 14-29 of the cells 3 and 4-8 are disposed on the opposed two sides, the cells 4-8 are disposed at both sides with the bus 10 as a center, and the macro functional cell having a small height is vertically connected with the data bus. Thus, it is not necessary to bend the data bus wirings complicatedly to optimally dispose and wire them.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、標準セル方式集積回路におけるコンピュータ
機能セル及びマクロ機能セルのデータバス端子の配置に
・関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the arrangement of data bus terminals of computer function cells and macro function cells in standard cellular integrated circuits.

〔従来の技術1 従来の標準セル方式集積回路のコンピュータ機能セル及
びマクロ機能セルのデータバス端子は、セル外周の一辺
にあるか、対辺にもデータバス端子が存在しても全ての
端子が対象には配置されていなかった。
[Conventional technology 1] The data bus terminals of computer function cells and macro function cells of conventional standard cell type integrated circuits are located on one side of the outer periphery of the cell, or all terminals are targeted even if there are data bus terminals on the opposite side. was not placed.

[発明が解決しようとする課題] しかし、前述の従来技術ではコンピュータ機能セル及び
マクロ機能セルの配置は集積回路チップ内のデータバス
の配置によりレイアウト効率が大きく影響されていた。
[Problems to be Solved by the Invention] However, in the prior art described above, the layout efficiency of the arrangement of computer function cells and macro function cells was greatly affected by the arrangement of data buses within the integrated circuit chip.

すなわち集積回路チップの中央部に直線にデータバスを
配置し、その両側にコンピュータ機能セル及びマクロ(
幾能セルを配置していた。
In other words, a data bus is arranged in a straight line in the center of the integrated circuit chip, and computer function cells and macros (
Ikuno cells were placed.

このためマクロ機能セルの数が多くなるとデータバスを
コの字に曲げて配置する必要が生じ集積回路チップ内に
占めるデータバス配線領域が増大するとともにレイアウ
トの自由度が制限されるという問題点を有していた。そ
こで本発明はこのような問題点を解決するもので、その
目的とするところは効率の良い集積回路チップのレイア
ウトを行なえるコンピュータ機能セル及びマクロ機能セ
ルを提供することにある。
For this reason, when the number of macro function cells increases, the data bus must be arranged in a U-shape, which increases the data bus wiring area within the integrated circuit chip and limits the freedom of layout. had. SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a computer function cell and a macro function cell that enable efficient integrated circuit chip layout.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、 a)標準セル方式集積回路において、 b)構成されるセルとして、基本ゲートセルとコンピュ
ータ機能セルとコンピュータ機能セルのデータバスを入
出力信号とするマクロ機能セルを有し、 C)該コンピュータ機能セルとマクロ機能セルのデータ
バスの入出力端子はセルの外周の一辺に、セル基準座標
より一定間隔で配置され向い合う対辺にも対象に配置さ
れることを特徴とする。
The semiconductor device of the present invention includes: a) a standard cell type integrated circuit; b) comprising a basic gate cell, a computer function cell, and a macro function cell whose input/output signals are a computer function cell and a data bus of the computer function cell; C) The input/output terminals of the data buses of the computer function cell and the macro function cell are arranged on one side of the outer periphery of the cell at regular intervals from the cell reference coordinates, and are also arranged symmetrically on the opposite sides.

[実 施 例] 以下、本発明の一実施例について説明する。[Example] An embodiment of the present invention will be described below.

第1図は、標準セル方式集積回路チップの平面図である
6 lは集積回路チップ、2はパッド領域、3はコンピ
ュータ機能セル、4〜8は□マクロ機能セル、9は基本
ゲートセル領域、10.11はデータバスである。第2
図は、第1図におけるマクロ機能セルの拡大図である。
FIG. 1 is a plan view of a standard cell type integrated circuit chip. 6 l is an integrated circuit chip, 2 is a pad area, 3 is a computer function cell, 4 to 8 are □ macro function cells, 9 is a basic gate cell area, 10 .11 is a data bus. Second
The figure is an enlarged view of the macro functional cell in FIG. 1.

12はマクロ機能セル、13はセル基準座標点、14〜
29はデータバス入出力端子である。
12 is a macro function cell, 13 is a cell reference coordinate point, 14-
29 is a data bus input/output terminal.

データバス入出力端子は14と22.15と23、以下
同様に21と29までマクロ機能セルの上辺と下辺との
間は同一信号端子となっており、セル高さの小さいマク
ロ機能セルは、4.6のようにマクロ機能セルの上辺下
辺の入出力端子を利用して縦方向のデータバスを構成す
ることができる。データバス入出力端子をコンピュータ
機能セル及びマクロ機能セルの相対する二辺上に設ける
ことによりデータバス配線及びセルの配置に自由度が増
し最適レイアウトができる。
The data bus input/output terminals are 14, 22, 15, and 23, and similarly, the same signal terminal is used between the upper and lower sides of the macro functional cell up to 21 and 29. As shown in 4.6, a vertical data bus can be constructed using the input/output terminals on the upper and lower sides of the macro function cell. By providing the data bus input/output terminals on two opposing sides of the computer function cell and the macro function cell, the degree of freedom in the arrangement of the data bus wiring and cells increases and an optimal layout can be achieved.

[発明の効果〕 以上述べたようにこの発明によれば、コンピュータ機能
セル及びマクロ機能セルのデータバス端子は相対する二
辺上に存在するためデータバスを中心に両側にマクロ機
能セルを配置し、セル高さの小さいマクロ機能セルは縦
方向に容易にデータバスを接続することができデータバ
ス配線を複雑に折り曲げる必要がな(なり配線領域を有
効に使用でき最適な配置・配線が可能となる。
[Effects of the Invention] As described above, according to the present invention, since the data bus terminals of the computer function cell and the macro function cell exist on two opposing sides, the macro function cell can be arranged on both sides with the data bus at the center. , macro function cells with small cell heights can easily connect data buses in the vertical direction, eliminating the need for complicated bending of data bus wiring (this allows for effective use of wiring area and allows for optimal placement and wiring. Become.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、標準セル方式集積回路チップの平面図である
。第2図は、マクロ機能セルの拡大図である。 1・・・・・・集積回路チップ 2・・・・・・パッド領域 3・・・・・・コンピュータ機能セル 4〜8・・・・マクロ機能セル 9・・・・・・基本ゲートセル領域 10.11・・・データバス 12・・・・・・マクロ機能セル 13・・・・・・セル基準座標点 14〜29・・・データバス入出力端予め11囚 821量
FIG. 1 is a plan view of a standard cellular integrated circuit chip. FIG. 2 is an enlarged view of the macro functional cell. 1...Integrated circuit chip 2...Pad area 3...Computer function cells 4-8...Macro function cell 9...Basic gate cell area 10 .11...Data bus 12...Macro function cell 13...Cell reference coordinate points 14-29...Data bus input/output terminal 11 cells 821 quantity in advance

Claims (1)

【特許請求の範囲】 a)標準セル方式集積回路において、 b)構成されるセルとして、基本ゲートセルとコンピュ
ータ機能セルとコンピュータ機能セルのデータバスを入
出力信号とするマクロ機能セルを有c)該コンピュータ
機能セルとマクロ機能セルのデータバスの入出力端子は
セルの外周の一辺に、セル基準座標より一定間隔で配置
され向い合う対辺にも対象に配置されることを特徴とす
る半導体装置。
[Scope of Claims] a) A standard cell type integrated circuit, b) The constituent cells include a basic gate cell, a computer function cell, and a macro function cell whose input/output signals are a data bus of the computer function cell. A semiconductor device characterized in that input/output terminals of data buses of a computer function cell and a macro function cell are arranged on one side of the outer periphery of the cell at regular intervals from the cell reference coordinates, and are also arranged symmetrically on opposite sides.
JP12812589A 1989-05-22 1989-05-22 Semiconductor device Pending JPH02306659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12812589A JPH02306659A (en) 1989-05-22 1989-05-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12812589A JPH02306659A (en) 1989-05-22 1989-05-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02306659A true JPH02306659A (en) 1990-12-20

Family

ID=14977014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12812589A Pending JPH02306659A (en) 1989-05-22 1989-05-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02306659A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745709A (en) * 1993-07-30 1995-02-14 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0745709A (en) * 1993-07-30 1995-02-14 Nec Corp Semiconductor device

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