JPH041372B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character information storage device for an electronic translator or the like.

In recent years, character information storage devices such as electronic translators have been developed, and these devices are equipped with a ROM (read only memory) that stores words such as Japanese and English. For example, in the case of English words, each word is represented by 26 alphanumeric characters, but conventionally each alphanumeric character is associated with one code, and in Japanese, each kana is also associated with one code. Therefore, different codes each consisting of 8 bits are set for alphabets and kana. That is, each word is stored in the ROM as data having a capacity of 8 bits per character.

By the way, for example, English words such as CA, LE, RY, etc.
There are combinations of multiple characters that are often used, and it is not possible to encode such combination characters one character at a time and store them in ROM.
This unnecessarily increases the memory capacity of the computer.

This invention was made in view of the above-mentioned circumstances, and its purpose is to associate a code with the same number of bits as the code for one character to the above-mentioned combination character consisting of a plurality of characters. To provide a character information storage device capable of storing a large amount of character information with a small storage capacity by associating numerical values of specific bits with specific characters.

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 show an embodiment in which the present invention is applied to an electronic translator having an English and Japanese translation function. In FIG. 1, the key input unit 1 includes various keys such as a Japanese input mode instruction key, an English input mode instruction key, a translation instruction key, and an alphanumeric key or kana key for inputting English or Japanese. It is provided. The key operation signals of each key of the key input section 1 are given to the control section 2 to execute various control operations necessary for translation, and the English or Japanese input data output from the key input section 1 is sent to the register 2. is entered and temporarily stored. The data stored in this register 3 is applied to an address designation circuit 4, a comparison circuit 5, and a display section 6, respectively. The address designation circuit 4 is a circuit that designates the address of the ROM 7 based on the data input into the register 3.

Here, to explain the configuration of ROM7, ROM
7 is roughly divided into an English area and a Japanese area. In the English area, the English word and the address data in the Japanese area where the translation of this English word is stored are stored as a pair of data. The address data in the English area where the translated word is stored are stored as a pair of data. In the case of English words, character codas are associated with one character or two characters, as shown in FIG. That is, each character code is represented by 8-bit data, and the numerical values of the upper 4 bits and lower 4 bits are associated with each character with regularity, as shown in FIG. As shown in the figure, the upper 4 bits of the character code are "0000" (decimal 0),
For the character code "0001" (decimal number 1), one code corresponds to one character, and the upper 4 bits correspond to characters "0010" (decimal number 2) to "0111" (decimal number 7). One code corresponds to two characters. In the case of a 2-character character code, the upper 4 bits are "0010" ~
The character codes of "0111" are BA~TA, respectively.
BI~TI, BU~TU, BE~TE, BO~TO, BY
~TY, where the second letter is A, I,
It has two characters corresponding to U, E, O, and Y.
Character codes whose lower 4 bits are "0000" to "1111" (15 in decimal) are BA to BY, respectively.
CA~CY, DA~DY, FA~FY, GA~GY,
HA~HY, JA~JY, KA~KY, LA~LY,
MA~MY, NA~NY, PA~PY, QA~QY,
RA~RY, SA~SY, TA~TY, where the first letter is B, C, D, F, G, H, J, respectively.
There are two characters corresponding to K, L, M, N, P, Q, R, S, and T.

In the case of the Japanese word kana, as in the case of the English word above, both the 1-character and 2-character characters are expressed by 8-bit character codes, and are correlated with regularity, but the details are explained below. omitted.

Each word read from ROM 7 is input to conversion circuit 8. The details of this conversion circuit 8 will be described later, but characters such as "CA" that are a combination of two characters and correspond to one code "00100001 (33)" are "C" and "A", that is, the code "00000010".
This circuit converts each character into a code such as "(2)" and "00000000(0)" and supplies it to the register 9, which is a static shift register. The data input to register 9 is sent to comparator circuit 5.
is given to register 3 by this comparator circuit 5.
A match or mismatch with the data in the data is compared and detected.
The detection signal is given to the control section 2, which in turn outputs a control command to the addressing circuit 4. This control section 2 controls the entire system and outputs various control signals including timing signals φ ₁ and φ ₂ , but illustration of these control signals is omitted.

Each data in registers 3 and 9 is sent to display section 6 and displayed. This display section 6 is, for example, a 20-digit 5
It consists of a ×7 liquid crystal dot matrix display device.

Next, the specific configuration of the conversion circuit 8 will be explained with reference to FIG. Words read from the ROM 7 are input to a register 11 constituted by a static shift register. This register 11 is driven by clocks φ ₁ and φ ₂ inputted through AND gates 12 and 13, respectively, and reads data when clock φ ₁ is output, and outputs the read data to the next stage when clock φ ₂ is output. do. The data output from the register 11 has a capacity for one character and is input to a buffer 14 driven by clocks φ ₁ and φ ₂ . The data in this buffer 14 is provided to a detection circuit 15 and an AND gate 16. The above detection circuit 15 is shown in FIG.
This circuit detects codes of 32 or more, that is, codes in which two characters are compressed into one character, and the detection signal is given to the AND gate 16 and one shot circuit 18 via the inverter 17, as well as to the buffer 20, AND gate 21, and delay circuit. The circuits 22 are each provided directly. The one-shot circuit 18 is a circuit that generates a "0" output during one cycle time of φ ₁ and φ ₂ when the detection output "1" is obtained from the detection circuit 15, and its output is sent to the AND gate 12, 13 as gate control signals.

Decoder 19 is detected by detection circuit 15
In this circuit, when a code of 32 or more is input, a code decomposed into each character is generated for 2 characters, and is fed to the buffer 20. For example, if the code ``33'' of ``CA'' is input, the code of ``C'' is input. The code "2" is output to the upper digit 20A of the buffer 20, and the code "0" of "A" is output to the lower digit 20B. Batsuhua 20
reads the code from the decoder 19 according to the detection signal from the detection circuit 15, and executes the read operation using the clock _φ1 . Further, the delay circuit 22 is driven by the clock φ ₂ and executes a delay operation for one character. The delayed output is used as a gate control signal for the AND gate 23.

On the other hand, upper digit 20A of buffer 20, lower digit 2
The codes read from 0B are input to register 9 via AND gates 21 and 23, respectively. The code output from the AND gate 16 is also input to the register 9. Note that register 9 is a static shift register driven by clocks φ ₁ and φ ₂ .

FIG. 4 shows a specific configuration of the decoder 19. That is, as explained with reference to FIG.
Lower 4 character codes for 2 characters
Bits are decimal numbers 0 to 15 (i.e., "0000" to
"1111"), the first character of each code is B to T.
is associated with. Therefore, the decoder 19A for the lower 4 bits detects whether or not the lower 4 bits of data represent characters B to T. That is, the decoder 19A inputs the data of the lower 4 bits of the character code,
The decoded output is the upper digit 2 of the buffer 20 above.
Give it to 0A. On the other hand, the top 4 character codes
Bits are decimal numbers 2 to 7 (i.e. "0010" to
"0111"), the second character of each code is A to Y.
is associated with. Therefore, this code is detected by the decoder 19B for the upper 4 bits. That is, the decoder 19B inputs the data of the upper 4 bits of the character coder, and provides its decoded output to the lower digit 20B of the buffer 20. Note that each matrix 1 shown in the decoder 19
Among 9 _A1 , 19 _A2 , 19 _B1 , and 19 _B2 , matrices 19 _A1 and 19 _B1 are AND gates with multiple inputs (horizontal direction) and 1 output (vertical direction), and matrices 19 _A2 and 19 _B2 are 1-input (vertical direction) and multiple output (horizontal direction) OR gate group.

Next, the operation of the above embodiment will be explained. For example, assume that you input the English word "AREA" and get its Japanese translation "chiiki". In this case, operate the English input mode instruction key on the key input unit 1, then input the above English word "AREA" using the alphanumeric key,
Next, operate the translation instruction key. By operating the above keys, the English word "AREA" will be changed to the code "0, 17, 4,
The signal is inputted to the register 3 as input data consisting of "0", and is applied to the address designation circuit 4, the comparison circuit 5, and the display section 6, respectively. Therefore, the address designation circuit 4 starts executing the address designation operation sequentially from the first address of the English area of the ROM 7. Furthermore, the English word "AREA" is displayed on the display section 6. ROM7
Then, according to the addressing operation described above, the English word at the first address is read out sequentially, written into the register 9 via the conversion circuit 8, and supplied to the comparison circuit 5. For this reason, the comparison circuit 5 sequentially compares the English word "AREA" in the register 3 with the English word in the register 9, and continues to output a detection signal of "0" at a binary logic level until a match is detected. Part 2
Therefore, the control section 2 causes the addressing circuit 4 to continue the addressing operation in response to this.

When the address where the English word "AREA" is stored in ROM7 is specified, "A" is written in register 11.
"RE", "A" each code "00000000",
“01011101” and “00000000” are input in this order. First, "A" is output from the register 11, read into the buffer 14 at the timing of clock _φ1 , and then read out at the timing of clock _φ2 and applied to the detection circuit 15 and the AND gate 16. The detection signal of the detection circuit 15 is "0" because "A" is not a code of 32 or more. Therefore, the output of the inverter 17 is "1", and the AND gate 16 is opened, and the above "A" is
6 into register 9, then “RE”
When the code "93" indicating "RE" is read into the buffer 14, the detection circuit 15 detects that "RE" is a code of 32 or more and outputs a detection signal "1".
Therefore, the output of the inverter 17 is inverted to "0", the AND gate 16 is closed, and the one-shot circuit 18 detects this state and outputs a "0" signal for a shift operation period of one character. Then, the AND gates 12 and 13 are closed, and the shift operation for one character is stopped. Further, the detection circuit 15 gives the code "01011101" to the decoder 19, and in response, the decoder 19 sends "R",
The codes "00010001" and "00000100" of "E" are output in parallel, and the upper digit 20A of buffer 20,
It is given to each lower digit 20B. Then, when the code "0010001" is read from the upper digit 20A at the timing of clock φ ₁ , the AND gate 21 which is currently being opened by the detection signal "1" of the detection circuit 15 is read out from the upper digit 20A.
The code "00010001", that is, the character "R" is applied to the register 9 and read therein. Next, the detection signal "1" is output as "1" from the delay circuit 22 at the timing of clock _φ2 , and
AND gate 23 is opened. Therefore, the code "00000100" in the lower digit 20B of the buffer 20, that is, the character "E" is applied to the register 9 via the AND gate 23 and read. Also, immediately after the timing of this clock _φ2 , the AND gate 1
2 and 13 are opened again, register 11 is driven by clock φ ₁ and "A" is input to buffer 14. Since this "A" does not correspond to the code "32 or more", the detection signal of the detection circuit 15 is output as "0", and in response, the AND gate 16 is opened again, and the above "A" is output as an AND gate. It is input to register 9 via 16.

When the four codes of the English word "AREA" are input into register 9 as described above,
Comparison circuit 5 detects a match between the codes of each English word in register 3 and register 9, and outputs a detection signal "1" to be applied to control section 2. As a result, the addressing operation stopped and the searched English word "AREA"
An addressing operation based on the address data of the translated word "Chiiki" read out together with the code is started, and the Japanese word "Chiiki" is read into the register 9 and displayed on the display section 6.

With the above configuration, taking the word "CALENDAR" as an example, a conventional storage device that represents one character with an 8-bit code would require a capacity as shown in FIG. As in the example, one character is represented by an 8-bit code, and a predetermined combination of characters is represented by one
In a storage device that is compatible with one code, the capacity of the shaded area can be saved, as shown in FIG. Figure 6 shows some of the words stored in the ROM 7, and it is possible to save 30 characters (240 bits) by comparing only 10 words. be.

FIG. 7 shows a modification of the character code shown in FIG. That is, in the character code corresponding to two characters, the character code in Figure 7 is the one in which the first and second characters of the two characters corresponding to the character code in Figure 2 are exchanged, and in this case For this purpose, the configuration of the decoder 19 may be modified accordingly, that is, the configuration may be such that 19A and 19B of the decoder 19 shown in FIG. 4 are replaced. Therefore, the present invention can be implemented in the same manner in the case of a character code structure as shown in FIG.

Note that in the above embodiment, the data is read from the ROM that stores words in compressed form, converted to normal form, and then compared with the input word. After converting
You can also compare it with compressed words stored in ROM.

Also, it is not limited to 2 characters, for example, "EST",
Three or more words, such as "ILY", may be used as one character code. Furthermore, it is of course possible to use other languages other than Japanese or English, and it can also be used not as a translator but also as a storage device that simply stores input words, such as an electronic memo. Further, other methods may be used to maintain regularity in character code correspondence.

As described above, according to the present invention, character information can be stored efficiently, so the memory capacity can be saved, and a large number of words can be stored in the storage device.

In addition, since regularity is provided in the correspondence of character codes, the structure of the code conversion circuit (for example, a decoder) is simplified, and the processing is also simplified.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment in which the present invention is applied to an electronic translator, FIG. 2 is a diagram showing English character codes, and FIG. 3 is a specific circuit configuration diagram of the conversion circuit 8. FIG. 4 is a detailed configuration diagram of the decoder 19, FIGS. 5A and 5B are diagrams showing an example of word encoding in the conventional method and in this embodiment, respectively, and FIG. 6 is a diagram showing word encoding in the conventional method and in this embodiment, respectively. FIG. 7 is a diagram showing a modification of the character code. DESCRIPTION OF SYMBOLS 1... Key input section, 2... Control section, 3... Register, 4... Address designation circuit, 5... Comparison circuit, 6... Display section, 7... ROM, 8... Conversion circuit, 9... ...Register, 11...Register, 14...
...Buffer, 15...Detection circuit, 19...Decoder, 20...Buffer, 22...Delay circuit.

Claims (1)

[Claims] 1 Character code is n (however, n is a positive even number)
One character is represented by the number of bits, and in a two-character code, the upper n/2 bits represent one character and the lower n/2 bits represent another character. means for specifying an address; means for reading a character code stored at the address of the memory specified by the specifying means; and an n-bit character code read by the reading means, a code or a two-character code, and a means for determining whether the character code to be determined is a two-character code, and
Upper n/2 bits of character code, lower n/2 bits
1. A character information storage device comprising: decoding means for converting 2 bits into one character code of corresponding n bits.