JPH04137266A - Clock signal replating circuit - Google Patents

Abstract

PURPOSE:To surely replace a clock signal by making a change-over with the use of a basic clock signal forming a frequency dividing clock signal, to replace the frequency dividing clock signal having uncertain phase difference. CONSTITUTION:Control selection signals (f),(g) are obtained by two or more frequency dividing clock selection signals (b),(c) sent from a higher rank circuit and also basic clock selection signals (j),(k) then held in signal holding circuits 3,4 by the frequency dividing clock signals (d),(e). Change-over selection signals (h),(i) from the signal holding circuits 3,4 actuate and output signal producing circuit 7, and are held in basic signal holding circuits 5,6 by the basic clock signal (a). The basic clock selection signals (j),(k) obtained by being held in basic signal holding circuits 5,6 are supplied to the gate circuits 2,1 other than their signal system. Thus, the replacement of clock signal can be surely performed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a clock signal transfer circuit used in a magnetic disk drive, and in particular, to a clock signal transfer circuit used in a magnetic disk drive. The present invention relates to a clock signal switching circuit that performs switching using a clock signal.

[Conventional technology]

Generally, a magnetic disk drive is provided with a clock signal transfer circuit, and this clock signal transfer circuit transfers a predetermined clock signal to another clock signal. This clock signal transfer circuit transfers a predetermined clock signal to another clock signal in the following manner. In other words, when the divided clock selection signal sent from the upper circuit is switched, the clock signal switching circuit performs frequency division using the currently selected divided clock signal (hereinafter referred to as the first divided clock signal). Capture the clock selection signal.

Then, when the clock signal switching circuit finishes capturing this frequency-divided clock selection signal, it stops outputting the first frequency-divided clock signal that has been selected and output, and at the same time outputs the first frequency-divided clock signal that is selected and output. The acquisition of the selection signal on the signal (hereinafter referred to as the second frequency-divided clock signal) side is started. Next, this clock signal transfer circuit outputs a second frequency-divided clock signal at the time when the acquisition of this selection signal is completed.

In this way, the conventional clock signal transfer circuit described above takes in the divided clock selection signal synchronized with the first divided clock signal with the second divided clock signal having a different phase. The frequency-divided clock selection signal synchronized with the frequency-divided clock signal is taken in by the first frequency-divided clock signal having a different phase.

[Problem to be solved by the invention]

Therefore, in this clock signal transfer circuit, the phase difference between the first frequency-divided clock signal and the second frequency-divided clock signal is not sufficient, and the hold time and set-up time required when capturing the frequency-divided clock selection signal are not satisfied. Otherwise, there would be a problem that the clock signal output from the clock signal transfer circuit would be disturbed. Further, this clock signal transfer circuit has the problem that the output clock signal is disturbed as described above even when the phase difference changes due to temperature, power supply voltage fluctuations, etc.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock signal switching circuit that can solve the above problems and output an accurate lock signal.

[Means to solve the problem]

The clock signal transfer circuit of the present invention includes a plurality of gate circuits that form a control selection signal based on a divided clock selection signal that selects a divided clock signal and a basic clock selection signal, and a control output from the gate circuit. a plurality of signal holding circuits that hold selection signals using the divided clock signals; a basic signal holding circuit that holds switching selection signals from the signal holding circuits using basic clock signals and outputs basic clock selection signals; and an output signal generation circuit that outputs a frequency-divided clock signal as the output clock signal in response to a switching selection signal from the circuit, the gate circuits each having a frequency-divided clock selection signal active. a control selection signal is activated only when the basic clock selection signal is active, and the signal holding circuit holds the divided clock signal and outputs a switching selection signal only when the control selection signal is active; The basic signal holding circuit holds the basic clock signal and outputs the basic clock selection signal only when the switching selection signal is active.

The present invention provides two or more divided clock selection signals sent from the upper circuit in order to select two or more divided clock signals obtained by dividing a basic clock signal generated in the upper circuit. , the control selection signal is obtained using the basic clock selection signal. The control selection signal is held by a frequency-divided clock signal in a signal holding circuit. The switching selection signal from the signal holding circuit operates the output signal generation circuit and is held by the basic clock signal in the basic signal holding circuit.

The basic clock selection signal held by the basic signal holding circuit is supplied to gate circuits other than the signal system. In this way, in the present invention, in order to switch the frequency division clock signal with an uncertain phase difference, the basic 20-channel signal that generates the frequency division clock signal is used for switching.
It is possible to reliably transfer clock signals.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the clock signal transfer circuit of the present invention.

In the embodiment shown in FIG. 1, an example will be described in which two clock signals are switched.

In FIG. 1, a gate circuit 1 receives a divided clock selection signal from an upper circuit (not shown). The gate circuit 2 receives a divided clock selection signal C from an upper circuit (not shown).

The output of the gate circuit 1 is connected to a signal holding circuit 3, and a control selection signal f from the gate circuit 1 is supplied to the signal holding circuit 3. The output of the gate circuit 2 is sent to the signal holding circuit 4
is connected to the control selection signal g from the gate circuit 2.
is supplied to the signal holding circuit 4. The output of the signal holding circuit 3 is connected to a basic signal holding circuit 5, and a switching selection signal from the signal holding circuit 3 is supplied to the basic signal holding circuit 5.

The output of the signal holding circuit 4 is connected to the basic signal holding circuit 6, and the switching selection signal 1 from the signal holding circuit 4 is supplied to the basic signal holding circuit 6. The switching selection signal 1 from the signal holding circuit 3 and the switching selection signal 1 from the signal holding circuit 4 are input to the output signal generation circuit 7. The output signal generation circuit 7 is configured to receive a frequency-divided clock signal d and a frequency-divided clock signal e. The basic clock signal a is input to the basic signal holding circuit 5 and the basic signal holding circuit 6. The output of the basic signal holding circuit 5 is connected to the other input terminal of the gate circuit 2, and the basic clock selection signal j from the basic signal holding circuit 5 is connected to the other input terminal of the gate circuit 2.
is supplied to the gate circuit 2. The output of the basic signal holding circuit 6 is connected to another input terminal of the gate circuit 1, and the basic clock selection signal k from the basic signal holding circuit 6 is supplied to the gate circuit 1. Further, an output clock signal β is outputted from an output terminal of the output signal generation circuit 7.

The gate circuit 1 sets both the divided clock selection signal and the basic clock selection signal to active (for example, “1”).
), the circuit configuration is such that the control selection signal f is set to "1". Gate circuit 2 receives divided clock selection signal C
The circuit configuration is such that the control selection signal g is set to "1" when both of the control selection signal g and the basic clock selection signal j are "1". The signal holding circuit 3 has a circuit configuration that can take in the control selection signal f at the timing of the frequency-divided clock signal d and output it as a selection signal. The signal holding circuit 4 has a circuit configuration that can take in the control selection signal g at the timing of the frequency-divided clock signal e and output it as the selection signal l. The basic signal holding circuit 5 captures the selection signal at the timing of the basic clock signal a, inverts the signal, holds it with respect to the divided clock signal e, and delays it by an amount that satisfies the time, and then outputs it as the basic clock selection signal j. It has a circuit configuration that can output. The basic signal holding circuit 6 takes in the selection signal ] at the timing of the basic clock signal a, inverts the signal, delays it by an amount that satisfies the hold time for the divided clock signal d, and then outputs it as the basic clock selection signal. The circuit configuration is such that it can be used.

The output signal generation circuit 7 outputs the frequency-divided clock signal d as the output clock signal β when the selection signal is “1”, or outputs the frequency-divided clock signal e as the output clock signal l when the selection signal is “1”. The circuit configuration is to output as .

Next, the operation of the embodiment configured as described above will be explained below.

Divided clock selection signal is active (e.g. “1”)
, the frequency-divided clock selection signal C is inactive (
For example, when the frequency-divided clock selection signal C is “0”), the divided clock selection signal C is “0”.
0", so the control selection signal g from the gate circuit 2 is "
0”, and the selection signal 1 from the signal holding circuit 4 also becomes “0”.
Therefore, the basic clock selection signal k, which is the output of the basic signal holding circuit 6, becomes "1".

At this time, since the divided clock signal selection signal input to the gate circuit 1 and the basic clock selection signal are "1", the control selection signal f from the signal holding circuit 3 becomes "1". As a result, the switching selection signal J from the signal holding circuit 3 becomes "1", and the basic clock selection signal J from the basic signal holding circuit 5 becomes "0".

Therefore, the switching selection signal from the signal holding circuit 3 is “
Since the switching selection signal 1 from the signal holding circuit 4 is "0", the output clock signal l from the output signal generation circuit 7 is the frequency-divided clock signal d.

On the other hand, when the frequency-divided clock selection signal S is "0" and the frequency-divided clock selection signal C becomes "1", the control selection signal f from the gate circuit 1 becomes "0". However, since the switching selection signal from the signal holding circuit 3 remains at "0" until the divided clock signal d changes, the output basic clock selection signal J from the basic signal holding circuit 5 also remains at "0". . Since the basic clock selection signal J is "0", the control selection signal g from the gate circuit 2 also remains at "0".

The selection signal becomes “0” in synchronization with the next divided clock signal d.
However, since the switching selection signal 1 output from the signal holding circuit 4 also remains "0", the output clock signal l
becomes inactive.

When the basic signal holding circuit 5 operates in synchronization with the basic clock signal a after the switching selection signal of the output of the signal holding circuit 3 becomes "0", the basic clock selection signal output from the basic signal holding circuit 5 j becomes "1" after the hold time for the divided clock signal e.

When the basic clock selection signal J becomes "1", the divided clock selection signal C is already "1", so the control selection signal g becomes "1".
As a result, the signal holding circuit 4 operates in synchronization with the change in the frequency-divided clock signal e, and sets the switching selection signal 1 to "1".

When the switching selection signal l becomes "1", the basic signal holding circuit 6 operates in synchronization with the next change in the basic clock signal a, and the basic clock selection signal k, which is the output of the basic signal holding circuit 6, is activated.
becomes “1”.

That is, when the switching selection signal 1 is "0", the switching selection signal 1 is "0".
becomes "1", the output clock signal l outputs the frequency-divided clock signal e.

Similarly, even if the frequency-divided clock selection signal S changes to "1" and the frequency-divided clock selection signal C changes to "O", the same operation will occur; first, the switching selection signal ] changes to "0", Since the switching selection signal remains at "0", the output clock signal β becomes inactive. After that, the switching selection signal becomes “1”
Since the switching selection signal l remains at "0", the output clock signal β becomes the frequency-divided clock signal d.

Since the change of the basic clock selection signal j from "0" to "1" satisfies the hold time condition of the divided clock signal e, the signal holding circuit 4 operates reliably, and the change in the basic clock selection signal Since the change from "0" to "1" satisfies the hold time condition of the divided clock signal d, the signal holding circuit 3 also operates reliably.

〔Effect of the invention〕

As explained above, in the present invention, in order to transfer a divided clock signal with an uncertain phase difference, the basic clock signal that generates the divided clock signal is used for switching. This has the effect of being able to reliably perform the following.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1.2... Gate circuit, 3.4... Signal holding circuit, 5.6... Basic signal holding circuit, 7... Output signal generation circuit, a... Basic clock signal, b, c ...divided clock selection signal, d, e...divided clock signal, f, g...control selection signal, h, i...selection signal, J, k... basic clock selection signal, β...Output clock signal.

Claims (1)

[Claims] A plurality of gate circuits that form a control selection signal based on a divided clock selection signal that selects a divided clock signal and a basic clock selection signal, and a control selection signal that is output from the gate circuit. a plurality of signal holding circuits that hold the frequency-divided clock signal; a basic signal holding circuit that holds the switching selection signal from the signal holding circuit using the basic clock signal and outputs the basic clock selection signal; and an output signal generation circuit that outputs a frequency-divided clock signal as the output clock signal in response to a switching selection signal, wherein each of the gate circuits is activated when the frequency-divided clock selection signal is active. The control selection signal is activated only when the clock selection signal is active, and the signal holding circuit holds the divided clock signal and outputs the switching selection signal only when the control selection signal is active, A clock signal transfer circuit characterized in that the holding circuit holds the switching selection signal using the basic clock signal only when the switching selection signal is active and outputs the basic clock selection signal.