JPH02219318A - Integrated circuit - Google Patents

Abstract

PURPOSE:To adjust delay time in time unit almost equivalent to the delay time of an internal element without attaching an external circuit for a delay element, etc., by delaying to the outside by providing an input buffer and an output buffer, and delaying a clock after connecting them. CONSTITUTION:The clock inputted from a clock terminal 3 is supplied to an internal circuit 2, and also, is outputted from a terminal 10 via the output buffer 4, and is inputted and outputted sequentially via the input buffer 7, the output buffer 8, and the input buffer 6. And it goes to a delay clock (b) having the delay time (e), and a selector 9 selects the clock (b) and supplies it to the circuit 2 by setting a control terminal 14 at a high level. At such a case, the adjustment of the delay time is performed by changing the connection of the terminals 10-13. For example, the delay time can be reduced by a time passing the buffers 7 and 8 by connecting the terminals 10 to 13. Also, when no delay is required, an original clock (a) is selected by a selector 15 by setting the terminal 14 at a low level, and it is supplied to the circuit 2. Therefore, the delay time can be adjusted in time unit almost equivalent to the delay time of the internal element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit that operates in synchronization with a clock and includes a portion that operates at a timing equal to or less than the clock cycle.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional integrated circuit.
1) is an integrated circuit, (2) is an internal circuit built into the integrated circuit (1), (3) is a clock terminal that supplies a clock to the internal circuit (2), and (4) is a clock terminal that supplies a clock to the integrated circuit (1).
), (5) a delay element that delays the clock output from the output buffer (4), and (6) an input buffer that inputs the delayed clock to the internal circuit (2). .

1 is a timing diagram showing the clocks supplied to the integrated circuit, (8) is the original clock supplied from the above clock terminal (3), (b) is the delayed clock, lcl , (d) Each original clock (
8), rising edge of delayed clock (1)), (θ
) is the delay time between the two clocks fa) (b), (f)
indicates the clock period.

Next, the operation will be explained. Normally, the internal circuit (2) operates in synchronization with the original clock (bl) supplied from the clock terminal (3).

That is, the state of the internal circuit (2) changes at the rising edge (C) of the original clock (b). However, there are times in the internal circuit (2) that there are parts that may operate in a shorter time than the clock cycle ff).

In such a case, a delay element (
5) and output the original clock +b) to the buffer (4)
, delay element 15) and input buffer (6), a delayed clock (b) f having a delay time (8) less than the clock period is generated, and its rising error 2(
dl operates part of the internal circuit (2).

[Problem to be solved by the invention]

Since conventional integrated circuits are configured as described above, it is necessary to provide an external delay element.

Since delay elements have a longer delay time than elements inside integrated circuits, it is difficult to finely adjust the delay time.When making adjustments, prepare multiple types of delay elements, remove them one by one, and attach them to the delay time. This invention requires work such as measuring time, and even when delay elements of the same type are used, the delay time varies depending on the individual delay elements. This invention solves the above-mentioned problems. The purpose is to obtain an integrated circuit that can adjust the delay time in units of time comparable to the delay time of internal elements without adding any external delay elements or other circuits. .

[Friendly means of solving problems]

The integrated circuit of the present invention includes a set of an input buffer whose input is empty and an output buffer whose output is input, and a layout that connects the terminals of these input buffers and output buffers, and an original clock input from the outside and a delay. It also has a selector that selects the clock and inputs it to the internal circuit.

[Effect]

In this invention, a pair of input buffer and output buffer delays the original clock, a selector selects the delayed clock and inputs it to the internal circuit, and when changing the connection between the terminals of the input buffer and output buffer, the delay time is increased. adjust.

〔Example〕

FIG. 1 shows an embodiment of the invention.

In the figure, j11 to f41. +61 is the above conventional example,
64 ivy (same), (7) is a hippo sofa,
(8) An output buffer that takes the output of the input buffer (7) as an input; (9) an internal one that selects the clock input from the female terminal (3) and the clock input from the input buffer (6); Selector input to path (2), H,'+1
B are respectively output buffers +41. (8) Output terminal, 112. Q31 manual buffer (71,
+61 input terminal, a41 is the control @ terminal of the selector (9), and wiring connecting f15 terminal f11.02.

+te indicates a wiring connecting terminals +11+II3.

Next, the operation of the above real '@ column will be explained. The clock input from the clock terminals +a)l)h is supplied to the internal circuit and also passes through the output buffer (4) to the terminal (11).
is output from. Here terminals III and U, aa and 113
1 is connected, the clock output from terminal i11 passes through input buffer (7), output buffer (8), and input buffer (6), thereby increasing the delay time tel.
The delay clock (b) becomes a delay clock (b) having a delay clock (b), and if the control terminal 11 is set high, the selector (19 selects the delay clock +b) and supplies it to the internal circuit (2). To adjust the delay time, change the connections between terminals 111 to C1 (for example, if you connect terminals !11 and 0J, the delay time will be shortened by the time it takes to go through the manual buffer (7) and output buffer (8)). (
Become. Also.

If there is no need to delay the original clock (a).

Terminal (set 14 low and use selector θ9 to turn 1 east clock (
a) 'i is selected and supplied to the internal circuit.

In the above embodiment, only one set of input buffer (7) and output sofa (8) is provided, but a plurality of sets may be provided to obtain a longer delay time.

It is also possible to connect a delay element to the terminal H, 031 and use it in the same manner as in the conventional example.

〔Effect of the invention〕

As described above, according to the present invention, a set of an input buffer and an output buffer is provided in an integrated circuit, and the clock is delayed by connecting these, so there is no need to add an external circuit such as a delay element. A delayed clock can be generated, and the delay time can be adjusted in units of one hour, which is about the same as the delay time of internal elements, simply by changing the wiring between the terminals.

4.: Brief explanation of page 121 Figure 1 is a block diagram of an embodiment of an integrated circuit according to the present invention, Figure 2 is a block diagram showing a conventional integrated circuit, and Figure 3 shows a clock supplied to the integrated circuit. FIG.

In the figure, (1) is an integrated circuit, (2) is an internal circuit, and (3) is an internal circuit.
) is a clock terminal, 14) is an output buffer that outputs the clock to the outside, (7) is an input buffer with an empty input, (8) is an output buffer that receives the output of this person's cover sofa, 63 is a delay clock terminal, (F9. tie is the wiring that connects the terminals, and (9) is the selector.

Note that in FIG. 1, the same or corresponding parts are designated by the same reference numerals.

Claims (1)

[Claims] A clock terminal that inputs an external clock, an internal circuit that operates in synchronization with the input clock, an output buffer that outputs the clock externally, an input buffer that has an empty input, and an output that receives the output of this input buffer as input. The buffer and the delay clock terminal provided separately from the above clock terminal, the wiring connecting these input buffers, output buffers and delay clock terminals, and the input of the above clock terminal and the input of the delay clock terminal are selected to create an internal circuit. an integrated circuit with a selector and an input to the input circuit.