JPH04134865A - Solid-state image sensing element - Google Patents

Abstract

PURPOSE:To eliminate a capacity of a wiring layer with a semiconductor substrate almost entirely by providing an electrode wiring layer connected to an output end of a buffer amplifier on a semiconductor substrate and by providing a wiring layer for connecting a stray diffusion layer and an input end of a buffer amplifier through an insulating film on an electrode Wiring layer. CONSTITUTION:An output wiring layer 11 is formed of a second layer aluminum film. A second layer Al electrode 26 is provided through an insulating film in an upper part of an Al wiring layer 13 in addition to an electrode wiring layer 21 of a first layer polysilicon film which is connected to the output wiring layer 11 through the contact hole 24. The second layer Al electrode 26 is connected to a source region 17 in a contact hole 25, and at the same time, it is continued to an output wiring layer 11. A capacity of a wiring part which connects a stray diffusion layer 8 and a driving transistor gate electrode 16 is further reduced. It is constituted of an MOS type source follower type buffer amplifier; the more a gain of the buffer amplifier approaches one, the more it affects.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state image sensor, and particularly to the structure of a charge detection section.

[Conventional technology]

In a charge transfer type solid-state image sensor, the output charge detection section is generally an amplifier using a floating diffusion layer from the viewpoint of S/N ratio, linearity, etc. FIG. 3(b) is a cross-sectional view showing an example of a charge detection section, in which the signal charge transferred through the horizontal CCD passes under the final stage transfer electrode 5 and output gate electrode 6, and enters the floating diffusion layer 8. flows in and is converted into voltage,
It is detected by a source follower amplifier (buffer amplifier) having a drive transistor 9 and a load transistor 10.

FIG. 3(a) is a plan view of the charge detection section. Figure 3 (b
) is a sectional view taken along the line X-X of FIG. 3(a, ). 8 is a floating diffusion layer, 16 is a gate electrode of the drive transistor 9 of the source follower amplifier, 13 is an Aρ wiring layer connecting the floating diffusion layer 8 and the gate electrode 9 of the drive transistor, and 15 is a train connected to the drain voltage terminal VDD. area, 17
is a source region connected to the load transistor 10, and this portion provides the output voltage.

The charge product ratio is calculated according to the change in the amount of charge Q transferred to the floating diffusion layer 8, based on the relational expression Q = CFJ''×■. Due to the reset operation of the transistor, the potential changes from the set field-through potential to ■.Here, CFJ' is the capacitance CF of the floating diffusion layer 8.

In addition, the capacitance Ca between the reset gate electrode 7, the capacitance Cb between the horizontal output gate electrode 6, and the A and R wiring layers 13 connecting the floating diffusion layer 8 and the gate electrode 16 of the drive transistor are connected to the semiconductor substrate. Capacitance Cc between the drive transistor gate electrode 16 and the semiconductor substrate
d, the capacitance Ce that the gate electrode 16 of the drive transistor has with its source region 15, and the capacitance Cf that the gate electrode 16 of the drive transistor has with its source region 16, expressed as the sum of the parasitic capacitances. can.

Therefore, the signal charge is the capacitance CFJ attached to the floating diffusion layer 8.
The smaller `` is, the higher the voltage conversion efficiency is, and the sensitivity of the element is improved. Conventionally, in order to reduce these parasitic capacitances as much as possible, for Ca and Cb, the area of the floating diffusion layer itself is reduced, and Cc.

Regarding Cd, measures have been taken to shorten or thin the AI2 wiring layer 13 that connects the floating diffusion layer 8 and the gate electrode 16 of the drive transistor, and the gate electrode 16 of the drive transistor.

[Problem to be solved by the invention]

However, due to the layout, extremely short wiring is impossible for the A (wiring layer) that connects the floating diffusion layer of the conventional charge detection unit and the gate electrode of the drive transistor, which poses a major obstacle to improvement. There was a point.

[Means to solve the problem]

The present invention provides a solid-state imaging device in which a charge transfer section, a floating diffusion layer that receives signal charges from the charge transfer section, and a buffer amplifier that detects a potential of the floating diffusion layer are integrated on a semiconductor substrate. An electrode wiring layer connected to an output end of the amplifier is provided on the semiconductor substrate, and a wiring layer connecting the floating diffusion layer and the input end of the buffer amplifier is provided on the electrode wiring layer via an insulating film. It is said that it is being carried out.

〔Example〕

Next, examples of the present invention will be described.

FIG. 1(a) is a plan view showing a first embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line Y--Y in FIG. 1(a).

Differences from the conventional example will be explained.

It is connected to the floating diffusion layer 8 through the contact hole 18-1, and is connected to the gate voltage [16 (second
A connected to the contact hole 19 (layer polysilicon film)
An insulating film 22 (with a thickness of 200 nm) is formed under the ffl wiring layer 13 (
An electrode wiring layer 21 (first layer polysilicon film) is provided via a silicon oxide layer (M). The electrode wiring layer 21 is connected to the output wiring layer 11 (Af film) through a contact hole 23.

Since the potential of the electrode wiring layer 21 changes with the potential of the Aρ wiring layer 13, there is almost no change in potential difference (, AJ wiring layer 1
The parasitic capacitance that No. 3 had between it and the semiconductor substrate can be reduced.

FIG. 2 is a plan view of a charge detection section according to a second embodiment of the present invention.

In this embodiment, an output wiring layer 11 is formed of a second layer aluminum film, and an electrode wiring layer 2 of a first layer polysilicon film is connected to this output wiring layer 11 through a contact hole 24.
1, an additional Af wiring layer 13 (in this example, the first
A second layer AJ electrode 24 is provided on top of the aluminum layer (aluminum film) via an insulating film (not shown). The second layer Aβ electrode 24 is connected to the source region 25 through the contact hole 25 and is continuous with the output wiring layer 11 .

Although the above embodiments, which can further reduce the capacitance of the wiring connecting the floating diffusion layer 8 and the drive transistor gate electrode 16, are constructed using an MO3 source follower type buffer amplifier, it is also possible to use a bipolar amplifier or the like. ,
It goes without saying that it is configurable, and the closer the gain of the buffer amplifier is to 1, the greater the effect.

〔Effect of the invention〕

As explained above, the present invention provides an electrode wiring layer that provides the output potential of the buffer amplifier through an insulating film on the wiring layer that connects the floating diffusion layer and the input end of the buffer amplifier. By almost eliminating the capacitance between the floating diffusion layer and the semiconductor substrate, the total capacitance of the floating diffusion layer can be reduced, and the conversion efficiency into voltage can be increased. In addition, since the S/N of the same output section is dominated by reset noise, the subsequent signal processing (correlated double sampling, etc.)
Since this can be removed, it has the effect of increasing sensitivity.

Electrode 5.6... Output gate electrode, 7... Reset gate electrode, 8... Floating diffusion layer, 9... Drive transistor, 10... Load transistor, 11... Output wiring layer, 12 ...gate bias power supply, 13.14...
- AII wiring layer, 15... drain region, 16...
Gate electrode, 17... Source region, 18-1.18-
2゜19.20... Contact hole, 21... Electrode wiring layer, 22... Insulating film, 23.24.25... Contact hole, 26... Second layer A, & electrode.

Claims (1)

[Claims] In a solid-state imaging device in which a charge transfer section, a floating diffusion layer that receives signal charges from the charge transfer section, and a buffer amplifier that detects the potential of the floating diffusion layer are integrated on a semiconductor substrate, an output terminal of the buffer amplifier An electrode wiring layer connected to the semiconductor substrate is provided on the semiconductor substrate, and a wiring layer connecting the floating diffusion layer and the input end of the buffer amplifier via an insulating film is provided on the electrode wiring layer. A solid-state image sensor featuring: