JPH04134818A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reliability and yield of a semiconductor device by using gaseous-phase etching through hydrofluoric acid vapor as a pretreatment for the formation of a wiring metal film. CONSTITUTION:A diffusion layer 12, field oxide film 13, gate oxide film 14 and polysilicon layer 15 for forming wiring and gate electrode are formed in a semiconductor substrate 11, then CVD oxide film 16, SOG layer 17 by application method and CVD oxide film 18 are formed on the whole surface and connection holes 20 are formed thereafter. Subsequently, a natural oxide film on the diffusion layer 12 or polysilicon layer 15 is removed by hydro-fluoric acid vapor. The flow rate of N2 and that of anhydrous hydrogen fluoride gas are regulated so that etching rate is controlled. Then, aluminum wiring 19 is attached for the purpose of completing the title device. At the time of etching where no abnormal etching part is formed in the SOG layer, O3 gas may be used because of removing the natural oxide film. In addition to the natural oxide film, organic contaminants of a substrate surface brought from a preceding process can be also removed by the introduction of the O3 gas so that the connection of the title device is stabilized further.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact hole in an interlayer insulating film including an insulating film by a coating method.

[Conventional technology]

Methods for flattening the glabellar insulating film under the wiring include a reflow method in which a phosphorus-containing silicate glass (PSG) layer is heat-treated at high temperature and reflowed, and a coating method in which an alcohol solution of a silicate compound is spin-coated and then baked. is common. Particularly in the future manufacturing of LSIs with fine patterns, the reflow method has a limit in planarization, so the coating method can be said to be the most promising planarization method.

Next, the process of forming contact holes in the glabella insulating film by the coating method will be explained using FIG.

First, as shown in FIG. 3(a), a diffusion layer 12, a gate oxide film 14, and a field oxide film 13 are formed on a semiconductor substrate 11, and then a polysilicon layer 15 for forming gate electrodes and wiring is formed. Next, a silicon oxide film (hereinafter referred to as a CVD oxide film) 16 is formed on the entire surface by the CVD method.

Next, as shown in FIG. 3(b), a silicon compound alcohol solution 2, for example 0CD-Type 2 (Tokyo Ohka Department)
A silicon oxide film (hereinafter referred to as SO
17 (referred to as G layer) is formed. Next, CVD oxide M18 is grown again on the entire surface.

Next, as shown in FIG. 3(c), a contact hole 20 is selectively opened to establish electrical connection between the diffusion layer 12 or the polycrystalline silicon wiring and the upper layer aluminum wiring to be formed in a subsequent step.

Next, as shown in FIG. 3(d), in order to remove, for example, the native oxide film on the diffusion layer 12, etching is performed for 60 seconds using, for example, 1:50 buffered hydrofluoric acid. Thereafter, layers A and & are formed by sputtering and then patterned to form aluminum wiring.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, the etching rate of the 300 layer 17 formed by the coating method using buffered hydrofluoric acid is about 1.
5 to 2 times larger. However, the time required for wet etching is usually about 100A in terms of thermal oxide film, and with this amount of etching, 300 layers 17 and C
There should be almost no problem with the difference in etching rate of the VD oxide film.

However, due to the capillary phenomenon, the etching solution permeates the interface between the SOG/117 and the upper and lower CVD oxide films, remains in the 300 layer 17 even after the etching process, and forms the contact hole 20.
There is a problem in that the adjacent 300 layer 17 is etched, resulting in an abnormally etched portion 21, which lowers the reliability and yield of the semiconductor device.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes a step of forming a contact hole in an interlayer insulating film including an insulating film formed on a semiconductor substrate by a coating method, and etching the contact hole by vapor phase etching using hydrogen fluoride vapor. The method includes a step of removing a natural oxide film on the bottom surface.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 2 is a configuration diagram of an oxide film removal apparatus used in the embodiment.

First, as shown in FIG. 1(a), a diffusion layer 12, a field oxidation M
13. Gate oxide film 14. A polysilicon layer 15 for forming wiring and gate electrodes is formed. Next, a CVD oxide film 16 constituting an insulating film between the eyebrows, a 300 layer 17 by a coating method, and a CVD oxide film 18 are formed on the entire surface, and then a 2° contact hole is formed. Next, the native oxide film on the diffusion layer 12 or the polysilicon layer 15 is removed using hydrofluoric acid vapor using the oxidized M removal apparatus shown in FIG.

As shown in Figure 2, the oxide film removal equipment is connected to the gas line l.
Water vapor is mixed into the N2 supplied by the paper chamber 3, and the mixture is introduced into the process chamber 4. Anhydrous hydrofluoric acid gas is introduced into the gas line 2. The semiconductor substrate 11 is placed on the rotary table 5 in the process chamber 4 and etching is performed.At this time, the etching speed can be controlled by adjusting the flow rate of N2 and the flow rate of anhydrous hydrofluoric acid gas. Here, the processing is performed for a period of time to etch the thermal oxide film by about 100%.

Next, as shown in FIG. 1(b), wiring A, & are formed into films by sputtering, patterned, and aluminum wiring 1
form one.

As described above, according to this embodiment, since the natural oxide film is removed by hydrogen fluoride vapor, abnormally etched portions are not formed in the SOG layer as in the conventional case.

Although N2 gas was used for etching with hydrofluoric acid vapor, 03 gas may also be used. By introducing the 03 gas, not only the natural oxide film but also the organic contaminants on the substrate surface brought in from the previous process can be removed, and the contact properties are further stabilized.

In the above embodiment, sputtering pretreatment of Aρ was taken as an example, but the present invention is not limited to this, and the same can be used as sputtering pretreatment of TiN, TiW, WSi, etc., or pretreatment of CVD growth of W. Needless to say, it is effective.

〔Effect of the invention〕

As explained above, the present invention uses vapor phase etching using hydrofluoric acid vapor as a pretreatment for forming a metal film for wiring, thereby eliminating the problem caused by penetration and residual etching solution that occurs in conventional wet processing. Since there is no need to worry about abnormal etching of the insulating film caused by the coating method, the reliability and yield of semiconductor devices can be improved.

hole, 1...Abnormal etching area.

Claims (1)

[Claims] A step of forming a contact hole in an interlayer insulating film including an insulating film formed on a semiconductor substrate by a coating method, and a step of removing a natural oxide film on the bottom surface of the contact hole by vapor phase etching using hydrogen fluoride vapor. A method for manufacturing a semiconductor device, comprising: