JPH04133412A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to manufacture a semiconductor integrated circuit device having the chip size of 15mm square or larger by a method wherein the mask pattern of two or more photomasks having different magnification against the design size are combined when a wafer is processed. CONSTITUTION:Two or more photomask patterns, having the different magnification against design dimensions, are combined when a wafer is processed. For example, a 1M-bit SRAM 1 of 15X6mm, a 4M-bit mask ROM 2 of 8X10mm and a CPU 4 of 3X8mm are provided as the part where a reticle mask, which is a quintuple photomask against the design dimensions having the design rule of 0.8mum, is used. A wiring region 4, which is used to connect between an I/O part of 19X20mm, an SRAM 1 of 1Mbit, a mask ROM 2 of 4Mbit, a CPU 3 and an I/O port, is provided as the part where photomask will be used against the design dimensions of the design rule of 3mum.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same.

[Summary of the Invention] The present invention realizes a semiconductor integrated circuit device with a chip size of 15 mm square or more by using a mask that is 1 times the design size and a mask that is 5 times the design size during wafer processing. .

[Prior Art] Although not shown, semiconductor integrated circuit devices with a design rule of 2 μm or less in the prior art are manufactured using a reticle mask, which is a photomask five times larger than the design size.

[Problems to be Solved by the Invention] However, the reticle mask, which is a photomask five times larger than the design size, has the problem that it is not possible to realize a chip size of 15 mm square or more due to restrictions on the exposure equipment of the reticle mask. .

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a method for manufacturing a semiconductor integrated circuit device having a chip size of 15 mm square or more.

[Means for Solving the Problems] The method for manufacturing a semiconductor integrated circuit device of the present invention is characterized in that mask patterns of two or more photomasks having different magnifications with respect to design dimensions are synthesized during wafer processing. .

[Example] As an example of the present invention, FIG. 1 shows a layout on a semiconductor integrated circuit device.

1, 2, and 3 are parts that use a reticle mask with a design rule of 0°8 μm and a photomask 5 times the design size, and 1 is 15 mm x 6 mm.
IMbit SRAM, 2 is 1010mm x 8 4Mbit SRAM, 3 is 3mm x 8tnm
There is a CPtJT.

4 is a part where the design rule is 3 μm and uses a photomask that is 1 times larger than the design size, and is 19 mm x 20 mm.
■/○ boat and IMbitSRAMl・4 Mb
It is a wiring area for connecting between the IT mask ROM2, CPU3, and the engineering/○ boat.

In addition, as an embodiment of the present invention, SRAMI, mask, RO
M2, CPU3, engineering 10 boats and wiring area 4 19m
Although a semiconductor integrated circuit device with a chip size of m x 20 mm was used, multiple circuits with various functions may be used as a single semiconductor integrated circuit device.
Mask ROM2/CPU3 design rule is 0°8μ
The design rule for the board and wiring area 4 is not limited to 3 μm.

[Effects of the Invention] As described above, according to the present invention, the chip size of semiconductor integrated circuit devices was conventionally limited by the exposure device of the reticle mask, but when processing the wafer, the chip size of the semiconductor integrated circuit device is limited by the exposure device of the reticle mask. 15mm by using a reticle mask that is 5 times the size of the photomask.
This has the effect that a chip size larger than square can be realized.

Furthermore, by preparing in advance a reticle mask, which is a photomask 5 times larger than the design dimensions of multiple circuits with various functions, and changing the wiring in the wiring area of the photomask, which is 1 times larger than the design dimensions, Applications such as the realization of semiconductor integrated circuit devices with various functions are possible.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a layout on a semiconductor integrated circuit device according to an embodiment of the present invention. 1. ・IMbit SRAM 2..4Mbit Mask ROM 3. ..CPU 4..I10 board and wiring area and above Applicant: Seiko Epson Corporation

Claims (1)

[Scope of Claims] 1) A method for manufacturing a semiconductor integrated circuit device, characterized in that mask patterns of two or more photomasks having different magnifications with respect to design dimensions are synthesized during wafer processing. 2) A semiconductor integrated circuit device manufactured using the manufacturing method according to claim 1. 3) A method for manufacturing a semiconductor integrated circuit device, wherein the photomask according to claim 1 is a photomask for positive resist. 4) A method for manufacturing a semiconductor integrated circuit device, wherein the photomask according to claim 1 is a photomask for negative resist. 5) A method for manufacturing a semiconductor integrated circuit device, wherein the photomask according to claim 1 is a photomask having a size 5 times larger than the design size and a photomask having a size 1x larger than the design size. 6) A method for manufacturing a semiconductor integrated circuit device, characterized in that the photomask with a design size of 5 times as claimed in claim 4 is smaller than the design rule of a photomask with a design size of 1 times.