JPH04131040U - delay circuit - Google Patents

Abstract

(57) [Summary] [Purpose] A delay circuit that can obtain a large delay time with an inexpensive circuit configuration. [Structure] A clock generator, a clock selector that arbitrarily selects and outputs a clock signal from the clock generator each time a switching signal is input to a control terminal, and a clock selector that arbitrarily selects and outputs a clock signal from the clock generator each time a switching signal is input to a control terminal; a first counter that counts time; a second counter that is counted up by the count output of the first counter and outputs a switching signal to a control terminal up to a preset count setting value; and a control circuit that delays based on a carry-out signal output when the second counter reaches a count set value.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This invention is based on delay of trigger signal to obtain data arbitrarily from digital filter. Regarding the circuit, in more detail, the trigger signal is synchronized with the data delay of the digital filter. This invention relates to a delay circuit that delays signals.

0002

[Conventional technology]

FFT analyzers etc. can measure specific frequency ranges with high frequency resolution. Digital filters are used in preprocessing for Fourier transform (FFT) zooming. I am using router. FIG. 3 is a configuration block showing an example of a digital filter to which the delay circuit of the present invention is applied. It is a lock diagram. A digital filter 10 that processes N pieces of data is connected serially. It is a connected multi-stage system, and can be accessed from any stage via a switch. The system is configured so that data can be obtained by In order to obtain such data, Each filter 10 requires a trigger signal synchronized with the amount of data delay. figure Among them, 10 is a filter that processes N pieces of data. Data is one filter 10 (1 stage), the data rate D slows down by 1/2. , after passing through the k-th filter 10, there will be a time delay as shown in the following equation.

[Math 1] Note that here, N indicates the time required to process the data N necessary for one stage of calculation, and k indicates the number of stages (set magnification) from which data is obtained. .

0003 Figure 4 shows how the trigger signal is synchronized with the data delay of the digital filter shown in Figure 3. FIG. 2 is a configuration block diagram of a conventional delay circuit for delaying. In the figure, 11 is a counter, 1 2 is a control circuit that enables the counter 11 based on the input trigger signal Tr0. to The counter 11 receives the clock signal CLK0 at the clock terminal (CK). The clock signal CLK0 is counterclocked by the enable signal S5 of the control circuit 12. starts, and outputs a carry-out signal S6 to the control circuit 12 at the set magnification k. Strengthen.

0004 The control circuit 12 receives data based on the carry-out signal S6 of the counter 11. A delayed trigger signal Tr1 is output in synchronization with the delay. Furthermore, the enable signal S5 is , are output based on the trigger signal Tr0 input to the control circuit 12.

[0005]

[Problem that the idea aims to solve]

In such a conventional delay circuit, as the number of filters, that is, n, increases, the number of filters decreases. The value counted by the counter increases, and the counter must be increased accordingly. This increases the circuit size and costs. It had the disadvantage that it would cause problems.

[0006] This invention was made in view of these points, and in response to the increase in the number of stages, This is designed to extend the period of the clock signal that counts the delay time, and meets the circuit regulations. A delay circuit that can obtain a large delay time with an inexpensive circuit configuration without increasing the size of the circuit. The purpose is to provide a route.

[0007]

[Means to solve the problem]

In order to achieve this purpose, the present invention a clock generator that generates a clock signal; Every time a switching signal is input to the control terminal, a clock is generated arbitrarily from the clock generator. a clock selector that selects and outputs a clock signal; A predetermined time is counted based on the clock signal input from this clock selector. a first counter to count; The count output of this first counter is used to count up and a second counter that outputs the switching signal to the control terminal up to a predetermined count setting value; and Enable the first and second counters based on the input trigger signal. , based on the carry-out signal output when the second counter reaches the count set value. a control circuit for delaying the trigger signal; and setting a trigger signal input to the control circuit to the second counter. for the time counted by the first counter based on the set count value set. It is characterized by a delay.

[0008]

[Effect]

Each component of the present invention operates as shown below. The clock generator generates a plurality of clock periods based on the reference first clock signal. generates a signal. The clock selector selects the clock signal of the clock generator and outputs the clock signal to the first counter. Output to data. The first counter counts the time required for the filter to operate on N pieces of data. After counting the number N of processed data, the carry-out signal is sent to the second counter. output to the printer 23.

[0009] The second counter is activated by the carry-out signal of the first counter. outputs a switching signal from the output terminal (D terminal) to the clock selector 21, A carry-out signal is output to the control circuit when the counted up value is the set magnification k. Strengthen. The control circuit enables the first and second counters based on the input trigger signal. a delayed trigger signal based on the carry-out signal of the second counter. Output.

0010

【Example】

Hereinafter, one embodiment of the present invention will be described in detail using the drawings. Figure 1 shows one part of the present invention. FIG. 2 is a configuration block diagram of a delay circuit showing an example. In the figure, 20 is a free run buy A clock generator for a numeric counter, which consists of K bits and has n clocks with different periods. A lock signal CLKn is generated. That is, the clock generator 20 clock signals CLKn (n=1 to k) with the same number of periods as the number of stages (number of stages). can occur.

[0011] 21 is a clock selector for selecting the clock CLKn of the clock generator 20; , first outputs the basic first clock signal CLK1 to the first counter 22 and controls it. Every time the switching signal S1 is input to the control terminal (CTL), the clock signal with twice the period CLK2, 3, . . . are output to the first counter 22.

0012 The first counter 22 receives the clock CLKn input from the clock generator 20. Count the time required for the filter to calculate N pieces of data based on the data When the number N of data processed is counted, the carry-out signal S2 is sent to the carry-out terminal. (CO) to the second counter 23.

[0013] The second counter 23 measures the number of stages from which data is taken, that is, the set magnification k. It is counted up by the carry-out signal S2, and the output terminal A switching signal S1 is output from the child (D terminal) to the clock selector 21. Also, settings Based on the magnification k, the control circuit 24 receives a carrier from the carry-out terminal (CO). Outputs an output signal S3.

[0014] The control circuit 24 controls the first and second counters based on the input trigger signal Tr0. 22 and 23, and also outputs the enable signal S4 to the second counter 23. A trigger signal obtained by delaying the trigger signal Tr0 by a certain period of time based on the carry-out signal S3 Outputs Tr1.

[0015] FIG. 2 is a time chart illustrating the operation of the delay circuit of the present invention, and (a) is the first delay circuit. clock signal CLK1, (b) is the second clock signal CLK2, (c) is the third clock signal The clock signal CLK3, (d) is the trigger signal Tr0, (e ) is the enable signal S4, (f) is the setting magnification k, and (g) is the counter of the first counter. The count value N, (h) is the carry-out signal S2 of the first counter, and (i) is the carry-out signal S2 of the second counter. The count value K, (j) of the counter is the carry-out signal S3 of the second counter, (k) is the delayed trigger signal Tr1. In addition, here, when the setting magnification k=3 The fourth clock signal CLK4 and subsequent ones are omitted. Ru.

[0016] (1) The clock selector 21 receives the first clock CLK1 from the clock generator 20. is selected and output to the first counter 22. (2) The first counter 22 receives an input signal obtained by the control circuit 24 based on the trigger signal Tr0. - Enabled by enable signal S4 and input from clock selector 21 The first clock signal CLK1 is counted.

[0017] (3) When the first counter 22 counts the clock signal CLK1 up to N, A carry-out signal S2 is output to the second counter 23. (4) The second counter 23 receives the carry-out signal input from the first counter. The count is increased from “1” to “2” by S2, and the output terminal (D terminal outputs the switching signal S1 from the clock selector 21 to the control terminal (CTL) of the clock selector 21. .

[0018] (5) When the clock selector 21 receives the switching signal S1, the clock selector 21 selects the second clock with twice the period. The clock signal CLK2 is outputted to the first counter 22. (6) Hereafter, the same process as (3) to (4) is repeated, and the first counter 22 receives the 3 clock signal CLK3 is output. (7) The first counter 22 counts this third clock signal CLK3 up to N. Then, a carry-out signal S2 is output to the second counter 23.

[0019] (8) The second counter 23 receives the carry-out input from the first counter 21. The carry-out signal S3 is counted up by the signal S2 and sent to the control circuit 24. Output to. (9) Based on the carry-out signal S3 of the second counter 23, the control circuit 24 A delayed trigger signal Tr1 is output. In this example, the trigger signal is delayed in synchronization with the data delay of the digital filter. As mentioned above, if you choose N and k arbitrarily, you can freely set the delay time. can be determined.

[0020]

[Effect of the idea]

As explained in detail above, the delay circuit of the present invention is a digital filter stage. As the number of clocks increases, it is possible to count using a clock signal with a large period. As a result, large delay times can be achieved without increasing the circuit scale and with an inexpensive circuit configuration. Obtainable.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of a delay circuit showing an embodiment of the present invention.

FIG. 2 is a time chart illustrating the operation of the delay circuit of the present invention.

FIG. 3 is an explanatory diagram of a multi-stage system in which digital filters are connected in series.

FIG. 4 is a configuration block diagram of a conventional delay circuit.

[Explanation of symbols]

20 Clock generator 21 Clock selector 22 First counter 23 Second counter 24 Control circuit

Claims (1)

[Scope of utility model registration request] 1. A clock generator that generates a clock signal; a clock selector that arbitrarily selects and outputs a clock signal from the clock generator each time a switching signal is input to a control terminal; A first device that counts a predetermined time based on an input clock signal.
and a second counter that is counted up by the count output of the first counter and outputs the switching signal to the control terminal up to a preset count setting value.
a counter, and the first and second counters are enabled based on an input trigger signal, and the trigger signal is enabled based on a carry-out signal output when the second counter reaches a count set value. and a control circuit that delays the trigger signal input to the control circuit by the time counted by the first counter based on the count setting value set in the second counter. Featured delay circuit.