JPH04131014U - Bias circuit for operational amplifiers - Google Patents

Bias circuit for operational amplifiers

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Publication number
JPH04131014U
JPH04131014U JP3597091U JP3597091U JPH04131014U JP H04131014 U JPH04131014 U JP H04131014U JP 3597091 U JP3597091 U JP 3597091U JP 3597091 U JP3597091 U JP 3597091U JP H04131014 U JPH04131014 U JP H04131014U
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JP
Japan
Prior art keywords
resistor
operational amplifier
capacitor
power
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3597091U
Other languages
Japanese (ja)
Inventor
常男 酒井
Original Assignee
富士通テン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通テン株式会社 filed Critical 富士通テン株式会社
Priority to JP3597091U priority Critical patent/JPH04131014U/en
Publication of JPH04131014U publication Critical patent/JPH04131014U/en
Withdrawn legal-status Critical Current

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Abstract

(57)【要約】 【目的】 本考案はアナログ信号を増幅する演算増幅器
への入力信号をバイアスせしめる演算増幅器用バイアス
回路に関し、演算増幅器へ電源投入時に生ずる雑音発生
防止を目的とする。 【構成】 演算増幅器(1)の一方の入力端子に直流バ
イアス電圧を供給するために、その一方が前記入力端子
に接続されかつその他方が接地される第1の抵抗(2)
と、その一方が該第1の抵抗(2)に接続されかつその
他方が直流電源に接続される第2の抵抗(3)と、前記
第1の抵抗(2)に並列接続される第1のコンデンサと
を有する演算増幅器用バイアス回路に、前記第2の抵抗
(3)に並列接続されかつ第1のコンデンサ(4)の容
量と実質に同一である第2のコンデンサ(5)を設け
る。
(57) [Summary] [Purpose] The present invention relates to a bias circuit for an operational amplifier that biases an input signal to an operational amplifier that amplifies an analog signal, and its purpose is to prevent the generation of noise that occurs when power is turned on to the operational amplifier. [Structure] In order to supply a DC bias voltage to one input terminal of the operational amplifier (1), a first resistor (2) whose one end is connected to the input terminal and whose other end is grounded.
a second resistor (3), one of which is connected to the first resistor (2) and the other to a DC power supply, and a first resistor (3) connected in parallel to the first resistor (2). A second capacitor (5) connected in parallel to the second resistor (3) and having substantially the same capacitance as the first capacitor (4) is provided in the operational amplifier bias circuit having a capacitor.

Description

【考案の詳細な説明】[Detailed explanation of the idea]

【0001】0001

【産業上の利用分野】[Industrial application field]

本考案はアナログ信号を増幅する演算増幅器への入力信号をバイアスせしめる 演算増幅器用バイアス回路に関する。 本考案では、特に、演算増幅器への電源投入時に生ずる雑音発生防止を目的と する。 This invention biases the input signal to an operational amplifier that amplifies analog signals. The present invention relates to a bias circuit for an operational amplifier. The purpose of this invention is to prevent the noise that occurs when power is turned on to the operational amplifier. do.

【0002】0002

【従来の技術】[Conventional technology]

図5は従来の演算増幅器用バイアス回路を示す図である。なお、全図を通じて 同様の構成要素については同一参照符号又は記号をもって表す。本図の構成には 、演算増幅器1と、その一方が該演算増幅器1の非反転端子に接続されかつその 他方が接地される第1の抵抗2と、その一方が該第1の抵抗2に接続されかつそ の他方が直流電圧電源に接続される第2の抵抗3と、前記第1の抵抗2に並列接 続される第1のコンデンサ4と、その一方が信号を受けかつその他方が前記演算 増幅器1の反転入力端子に接続される抵抗6と、その一方が該演算増幅器1の出 力に、その他方がその反転入力端子に接続される帰還用の抵抗7とが含まれる。 FIG. 5 is a diagram showing a conventional bias circuit for an operational amplifier. In addition, throughout the diagram Similar components are represented by the same reference numerals or symbols. The structure of this diagram is , an operational amplifier 1, one of which is connected to the non-inverting terminal of the operational amplifier 1 and whose a first resistor 2, the other of which is grounded, and one of which is connected to and connected to the first resistor 2; A second resistor 3, the other of which is connected to a DC voltage power supply, and a second resistor 3 connected in parallel to the first resistor 2. a first capacitor 4 connected to the circuit, one of which receives the signal and the other of which receives the signal; A resistor 6 is connected to the inverting input terminal of the amplifier 1, and one of the resistors is connected to the output terminal of the operational amplifier 1. The input voltage includes a feedback resistor 7, the other side of which is connected to its inverting input terminal.

【0003】 ここで、第1の抵抗2、第2の抵抗3、抵抗6、抵抗7の抵抗値をそれぞれR 1 ,R2 ,R3 及びR4 とし、第1のコンデンサ4の容量をC1 とする。 次に動作を説明する。図6は演算増幅器の各部の信号波形を示す図である。本 図(a)は演算増幅器1の反転端子における抵抗6に入力する信号である。この 信号は0Vの基線に対して正負の交流信号である。本図(b)は、バイアス回路 として第1および第2抵抗2及び3がないとした場合に演算増幅器1の出力に現 われる信号を示し、演算増幅器1、抵抗6及び7は反転増幅回路を構成するので その閉ループ利得GがG=−R4 /R1 になる。本図(c)は上記増幅された交 流信号に第1及び第2の抵抗で分圧された電圧VB =VCC・R1 /(R1 +R2) が重ねられてバイアスされた交流信号を示される。ここでVCCは直流電圧電源で ある。このようにしてバイアスされた信号はその後種々の処理がなされ最終的に はスピーカで再生される。0003 Here, the resistance values of the first resistor 2, second resistor 3, resistor 6, and resistor 7 are respectively set to R. 1 ,R2,R3and RFourand the capacitance of the first capacitor 4 is C1shall be. Next, the operation will be explained. FIG. 6 is a diagram showing signal waveforms at each part of the operational amplifier. Book Figure (a) shows a signal input to the resistor 6 at the inverting terminal of the operational amplifier 1. this The signal is an alternating current signal that is positive or negative with respect to the base line of 0V. This diagram (b) shows the bias circuit Assuming that the first and second resistors 2 and 3 are not present, the output of the operational amplifier 1 is Since operational amplifier 1 and resistors 6 and 7 constitute an inverting amplifier circuit, Its closed loop gain G is G=-RFour/R1become. This figure (c) shows the amplified intersection described above. A voltage V obtained by dividing the current signal by the first and second resistorsB=VCC・R1/(R1+R2) are shown superimposed to show the biased AC signal. Here VCCis a DC voltage power supply be. The biased signal is then subjected to various processing and finally is played on the speaker.

【0004】0004

【考案が解決しようとする課題】[Problem that the idea aims to solve]

しかしながら従来の演算増幅器用バイアス回路では電源投入時に下記理由によ り雑音が発生するという問題があった。図7は電源投入時のバイアス電圧VB の 変化を示す図である。電源が投入されると、電源から第2の抵抗3を介して時定 数R2C1で第1のコンデンサ4へ充電がされるが、同時に第1の抵抗2を介して時 定数R1C1で放電がされる。このため図7に示すようにバイアス電圧が所定値VB になるまで長時間Tを要す。図8は電源投入時の演算増幅器の出力信号を示す図 である。本図に示すように演算増幅器1の出力信号は電源投入からT時間、バイ アス電圧が過渡変化状態にあるので、入力信号に対して正常にバイアスされてい ないので、この間における後段の信号処理では正常処理されず雑音として形成さ れてしまう。一方、この間の信号処理を停止すれば雑音は生じないが、応答性が 劣化するという別の問題が生じる。However, the conventional bias circuit for an operational amplifier has a problem in that noise is generated when the power is turned on for the following reason. FIG. 7 is a diagram showing changes in bias voltage V B when power is turned on. When the power is turned on, the first capacitor 4 is charged from the power supply via the second resistor 3 with a time constant R 2 C 1 , but at the same time, the first capacitor 4 is charged via the first resistor 2 with a time constant R 1 C 1 , a discharge occurs. Therefore, as shown in FIG. 7, it takes a long time T until the bias voltage reaches the predetermined value VB . FIG. 8 is a diagram showing the output signal of the operational amplifier when the power is turned on. As shown in this figure, the bias voltage of the output signal of operational amplifier 1 is in a transient state for time T after the power is turned on, so it is not normally biased with respect to the input signal, so the subsequent signal processing during this period is normal. It is not processed and is formed as noise. On the other hand, if signal processing is stopped during this time, noise will not be generated, but another problem will arise in that the responsiveness will deteriorate.

【0005】 したがって本考案は上記問題点に鑑みて電源投入時に容易にバイアス電圧の過 渡変化を防止できる演算増幅器バイアス回路を提供することを目的とする。[0005] Therefore, in view of the above-mentioned problems, the present invention is designed to easily prevent overloading of the bias voltage when the power is turned on. An object of the present invention is to provide an operational amplifier bias circuit that can prevent transient changes.

【0006】[0006]

【課題を解決するための手段】[Means to solve the problem]

本考案は前記問題点を解決するために演算増幅器の一方の入力端子に直流バイ アス電圧を供給するべく、その一方が前記入力端子に接続されかつその他方が接 地される第1の抵抗と、その一方が該第1の抵抗に接続されかつその他方が直流 電源に接続される第2の抵抗と、前記第1の抵抗に並列接続される第1のコンデ ンサとを有する演算増幅器用バイアス回路に前記第2の抵抗に並列接続されかつ 第1のコンデンサの容量と実質に同一である第2のコンデンサを設ける。 In order to solve the above-mentioned problems, the present invention provides a direct current bias to one input terminal of the operational amplifier. One of them is connected to the input terminal and the other is connected to supply the ground voltage. a first resistor connected to the ground, one of which is connected to the first resistor, and the other is connected to the DC a second resistor connected to a power supply; and a first capacitor connected in parallel to the first resistor. an operational amplifier bias circuit having a resistor connected in parallel to the second resistor; A second capacitor is provided that is substantially the same in capacity as the first capacitor.

【0007】[0007]

【作用】[Effect]

本考案の演算増幅器用バイアス回路によれば、第1及び第2のコンデンサの容 量を実質的同一にすることによって第2のコンデンサによって形成されるバイア ス電圧の電源投入時過渡状態が第1のコンデンサによって形成されるバイアス電 圧の過渡状態を相殺するので、バイアス電圧は電源投入により即立上がり、出力 信号が直流電圧変動を受けなくなる。 According to the operational amplifier bias circuit of the present invention, the capacitance of the first and second capacitors is the vias formed by the second capacitor by making the quantities substantially the same; The power-up transient of the bias voltage is caused by the bias voltage formed by the first capacitor. Since the voltage transient state is canceled out, the bias voltage rises immediately when the power is turned on, and the output The signal is no longer subject to DC voltage fluctuations.

【0008】[0008]

【実施例】【Example】

以下本考案の実施例について図面を参照して説明する。図1は本発明の実施例 に係る演算増幅器用バイアス回路を示す図である。本図の構成において、図5に 示すものと異なるもは、第2の抵抗3に並列接続されかつ第1のコンデンサ4の 容量C1 と実質的に同一である容量C2 を有する第2のコンデンサ5である。図 2は電源投入時の第1及び第2のコンデンサ4及び5によるバイアス電圧を示す 図である。図中の第1のコンデンサ4によるバイアス電圧は第2のコンデンサ5 がない場合のもので図7の説明と同様に形成される。一方、第2のコンデンサ5 のバイアス電圧は第1のコンデンサ4がない場合のもので、電源が投入されると 、当初充電がされてないが第1のコンデンサ2を介して時定数R1C2で充電され、 これと同時に第2の抵抗R2 を介して時定数R2C2で放電し、このため電源投入後 T時間経過後には第1及び第2の抵抗2及び3で定まる一定電圧VB になる。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an operational amplifier bias circuit according to an embodiment of the present invention. The configuration in this figure is different from that shown in FIG. This is capacitor 5. FIG. 2 is a diagram showing the bias voltages generated by the first and second capacitors 4 and 5 when the power is turned on. The bias voltage generated by the first capacitor 4 in the figure is the one without the second capacitor 5, and is formed in the same manner as described in FIG. On the other hand, the bias voltage of the second capacitor 5 is the one without the first capacitor 4, and when the power is turned on, although it is not initially charged, the time constant R 1 C is applied via the first capacitor 2. 2 , and at the same time, it is discharged via the second resistor R2 with a time constant R2C2 . Therefore, after the time T has elapsed after the power is turned on, a constant voltage determined by the first and second resistors 2 and 3 is discharged. The voltage becomes V B.

【0009】 図3は図2におけるバイアス電圧の合成を示す図である。本図に示すように第 1のコンデンサ4に対して第2のコンデンサ5を設け、それぞれの容量をC1 ≒ C2 とすることによって、図2におけるそれぞれのバイアス電圧の過渡状態が相 殺され、その合成バイアスは電源投入後に即立上がり、第1及び第2の抵抗2及 び3で定まるバイアス電圧になり従来のような長期の過渡状態が生じることはな い。FIG. 3 is a diagram showing the composition of the bias voltages in FIG. 2. As shown in this figure, by providing the second capacitor 5 for the first capacitor 4 and setting the respective capacitances to C 1 ≒ C 2 , the transient states of the respective bias voltages in FIG. 2 are canceled out, The composite bias rises immediately after the power is turned on, and becomes the bias voltage determined by the first and second resistors 2 and 3, so that no long-term transient state occurs as in the conventional case.

【0010】 図4は電源投入時の演算増幅器の出力信号を示す図である。本図に示すように 電源投入時直後のバイアス電圧に過渡状態がなくなったので、演算増幅器1の出 力信号にも当初から正常バイアスが与えられるので、この信号かつ後段の処理回 路に送出されても、従来のように雑音としてでなく、正常の信号処理が行われる 。このため、電源投入時の発生が防止される。0010 FIG. 4 is a diagram showing the output signal of the operational amplifier when the power is turned on. As shown in this figure Since there is no longer a transient state in the bias voltage immediately after the power is turned on, the output of operational amplifier 1 Since the normal bias is also given to the force signal from the beginning, this signal and the subsequent processing circuit Even if the signal is sent out to the road, normal signal processing is performed instead of generating noise as in the case of conventional methods. . This prevents the occurrence of this problem when the power is turned on.

【0011】 以上、演算増幅器に用いられるバイアス回路として説明したが、フィルタ回路 等においても同じことがいえる。[0011] The above was explained as a bias circuit used in an operational amplifier, but a filter circuit The same can be said for etc.

【0012】0012

【考案の効果】[Effect of the idea]

以上説明したように、本考案によれば、演算増幅器のバイアス回路である電圧 分圧抵抗にそれぞれ並列に容量が同一のコンデンサを設けたので、電源投入時に バイアス電圧に過渡状態がなくなり即一定のバイアス電圧になり、雑音発生が防 止できる。 As explained above, according to the present invention, the voltage that is the bias circuit of the operational amplifier is Since capacitors with the same capacity are placed in parallel with each voltage dividing resistor, when the power is turned on, The bias voltage no longer has a transient state and becomes a constant bias voltage, preventing noise generation. Can be stopped.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の実施例に係る演算増幅器用バイアス回
路を示す図である。
FIG. 1 is a diagram showing an operational amplifier bias circuit according to an embodiment of the present invention.

【図2】電源投入時の第1及び第2のコンデンサによる
バイアス電圧を示す図である。
FIG. 2 is a diagram showing bias voltages due to first and second capacitors when power is turned on.

【図3】図2におけるバイアス電圧の合成を示す図であ
る。
FIG. 3 is a diagram showing a synthesis of bias voltages in FIG. 2;

【図4】電源投入時の演算増幅器の出力信号を示す図で
ある。
FIG. 4 is a diagram showing the output signal of the operational amplifier when the power is turned on.

【図5】従来の演算増幅器用バイアス回路を示す図であ
る。
FIG. 5 is a diagram showing a conventional operational amplifier bias circuit.

【図6】演算増幅器の各部の信号波形を示す図である。FIG. 6 is a diagram showing signal waveforms of each part of the operational amplifier.

【図7】電源投入時のバイアス電圧変化を示す図であ
る。
FIG. 7 is a diagram showing changes in bias voltage when power is turned on.

【図8】電源投入時の演算増幅器の出力信号を示す図で
ある。
FIG. 8 is a diagram showing the output signal of the operational amplifier when the power is turned on.

【符号の説明】[Explanation of symbols]

1…演算増幅器 2,3…抵抗 4,5…コンデンサ 1...Operation amplifier 2, 3...Resistance 4, 5...Capacitor

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 演算増幅器(1)の一方の入力端子に直
流バイアス電圧を供給するために、その一方が前記入力
端子に接続されかつその他方が接地される第1の抵抗
(2)と、その一方が該第1の抵抗(2)に接続されか
つその他方が直流電源に接続される第2の抵抗(3)
と、前記第1の抵抗(2)に並列接続される第1のコン
デンサとを有する演算増幅器用バイアス回路において、
前記第2の抵抗(3)に並列接続されかつ第1のコンデ
ンサ(4)の容量と実質に同一である第2のコンデンサ
(5)を備えることを特徴とする演算増幅器用バイアス
回路。
1. A first resistor (2), one of which is connected to the input terminal and the other of which is grounded, in order to supply a DC bias voltage to one input terminal of the operational amplifier (1); a second resistor (3), one of which is connected to the first resistor (2) and the other connected to the DC power supply;
and a first capacitor connected in parallel to the first resistor (2),
A bias circuit for an operational amplifier, characterized in that it comprises a second capacitor (5) connected in parallel to the second resistor (3) and having substantially the same capacity as the first capacitor (4).
JP3597091U 1991-05-21 1991-05-21 Bias circuit for operational amplifiers Withdrawn JPH04131014U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3597091U JPH04131014U (en) 1991-05-21 1991-05-21 Bias circuit for operational amplifiers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3597091U JPH04131014U (en) 1991-05-21 1991-05-21 Bias circuit for operational amplifiers

Publications (1)

Publication Number Publication Date
JPH04131014U true JPH04131014U (en) 1992-12-01

Family

ID=31918018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3597091U Withdrawn JPH04131014U (en) 1991-05-21 1991-05-21 Bias circuit for operational amplifiers

Country Status (1)

Country Link
JP (1) JPH04131014U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09135132A (en) * 1995-11-10 1997-05-20 Fujitsu Ltd Amplifier circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09135132A (en) * 1995-11-10 1997-05-20 Fujitsu Ltd Amplifier circuit

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