JPH04130638A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the allowable range of aligning accuracy when connecting and facilitate integration by independently forming a wiring pattern without providing a pad and connecting at least two wiring patterns with internal wiring. CONSTITUTION:Wiring patterns 211-21n are formed in an area close to the one side of an LSI 1 at the same intervals in the vertical direction to the side. Internal wiring 201-20m is connected with the patterns 211-21n from an internal circuit 12. The patterns 211-21n are conductive and are formed by polysilicon wiring, aluminum wiring, etc. The width and the intervals of the patterns 211-21n are permitted to be the minimum pattern width and interval that can be formed by the LSI production, and when the width of the internal wiring is wide enough, the wiring patterns are formed by the pattern width and intervals which permit the wiring pattern to be in the wiring width.

Description

[Detailed Description of the Invention] [Summary] As a method for reducing the pad formation area in semiconductor integrated circuit circuits, especially in the configuration of external terminals for transmitting signals with the outside of an LSI, it is possible to improve alignment accuracy without using pads. The purpose of the present invention is to provide a semiconductor integrated circuit device having a connection method for external wiring and internal wiring that has a large tolerance range and is more suitable for integration than when using pads, and in an area on the semiconductor chip 1 and near the chip side.
It has a plurality of mutually independent wiring patterns 211 to 2In formed at equal intervals in a direction substantially perpendicular to the chip side,
The wiring pattern is formed by connecting at least two wiring patterns to internal wiring 20 inside the chip which is connected to the wiring pattern.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit (LSI), particularly an LSI
The present invention relates to the configuration of an external terminal for transmitting signals to the outside.

In recent years, the circuit scale of LSIs has increased year by year, and the integration density has also improved. However, there is a limit to the chip size. Under these circumstances, in order to increase the scale of the internal circuit, it is necessary to minimize areas that are not directly involved in internal circuit operations, such as pad formation areas.

[Conventional technology]

FIGS. 7(a) and 7(b) are diagrams showing conventional general LSI configurations. As shown in FIG. 7(a), the conventional LS
II uses a plurality of pads 3 arranged in a row around the LSII as external terminals. This pad 3 is connected to the internal lead 5 of the package 2, for example, via a wire 4 by wire bonding or by forming a bump.
Since it is connected via AB mounting leads, LSI
A very large area is required for each part within. That is, as shown in FIG. 7(b), taking the pad 3 with wire bonding as an example, the diameter of the wire 4 is approximately 35 μm.
The crimp portion 14 is 80 to 90 .mu.m thick, and if positioning errors at the time of bonding are taken into account, the usable area of the pad 3 is approximately 100 .mu.m.times.100 .mu.m.

It can be seen that this area is quite large since the transistor is several μm square.

[Problem to be solved by the invention]

By the way, due to the large-scale internal circuits of LSIs in recent years,
There is a limit to the advancement of miniaturization of internal circuits, and there is a demand for reducing areas unrelated to internal circuit operation, especially pad formation areas, and using them for internal circuits. However, conventionally, since pads are indispensable, consideration must be given to reducing the pad size. It would be possible to simply reduce the diameter of the wire (and thereby reduce the area of the crimped part), but this requires devising devices such as precision bonding and machinery that can handle the diameter of the wire, and we will wait for the advancement of these peripheral technologies. Regarding bumps, we must also wait for advances in technology to reduce lead width and spacing, bumps, and mounting accuracy.

Therefore, an object of the present invention is to propose a method for connecting external wiring and internal wiring that does not use pads, rather than reducing the size of the currently used components in order to reduce the pad formation area. However, it is an object of the present invention to provide a semiconductor integrated circuit device which can widen the tolerance range of positioning accuracy during connection and is more suitable for integration than when using pads.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention. In the figure, 1 is a semiconductor integrated circuit device (LSI chip), 12 is an internal circuit, and 20
is an internal wiring, 211 to 21n are wiring patterns, and 31 is an external wiring.

The semiconductor integrated circuit device of the present invention has a plurality of mutually independent wiring patterns 211 to 2In formed on the chip 1 and at equal intervals in a direction substantially perpendicular to the chip side in a region near the chip side. However, the wiring pattern has at least two wiring patterns connected to the internal wiring 20 inside the chip which is connected to the wiring pattern.

[Effect]

In the semiconductor integrated circuit device of the present invention, a wiring pattern is used and no pads are provided. The wiring pattern is formed independently, and at least two wiring patterns are formed for the internal wiring inside the chip.
The wiring pattern of the book is connected. Therefore, when an external wiring is connected to a wiring pattern to which an internal wiring is connected, an electrical connection can be obtained if the external wiring can be connected to the wiring pattern that is connected furthest from the center of the internal wiring width. A large margin can be obtained against misalignment with wiring. Also, when the sum of the external wiring and internal wiring widths is smaller than the pad width, the external wiring and internal wiring can be connected with a width smaller than the pad width even if positional deviation is taken into account, resulting in greater integration than when using pads. becomes possible.

[Embodiment] FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, 201~
20m is internal wiring. Note that the same components as those in FIG. 1 are given the same reference numerals.

In this embodiment, as shown in the top view of the LSI chip in FIG. 2(a), wiring patterns 211 to 2In are formed in a region near one side of the LSII at regular intervals in the direction perpendicular to the -side. There is. Then, from the internal circuit 12 to the internal wiring 2
01-20m are connected to wiring patterns 211-21n.

The wiring patterns 211 to 21n are conductors, and can be formed using conductors used when manufacturing this LSI, such as polysilicon wiring or aluminum wiring. In addition, the width and spacing of the wiring patterns 211 to 2In are as follows:
They are formed with the minimum pattern width and spacing that can be formed in LSI manufacturing, or when the internal wiring width is sufficiently wide, the pattern width and spacing are such that at least the wiring pattern is always included within the internal wiring width.

FIG. 2(b) shows the wiring pattern 211 of FIG. 2(a).
The area where .about.21n is formed is shown to be formed all around the sides of LSll.

FIG. 2(c) shows a wiring pattern in which the wiring patterns 211 to 21n are not parallel and not equally spaced.

FIG. 2(d) shows an example of application to a polygonal chip.

FIG. 3 is a partially enlarged sectional view taken along line A-B in FIG. In the figure, the wiring pattern 21 is formed on a silicon oxide film 7 formed on the surface of a P-type silicon substrate 6 with a low concentration of impurity. One end of the wiring pattern 21 on the internal circuit side is covered with an insulating protective film 24 such as PSG, and is connected to an internal wiring 20j extending from above the insulating protective film 24. After the chip is connected to external wiring, the entire chip is covered with a protective film.

Next, the operation of this embodiment will be specifically explained using FIGS. 4 and 5. 4 and 5 are partially enlarged views of region Z in FIG. 2.

Below, it will be explained that this embodiment has a large margin against positional deviation.

In FIG. 4, in order to simplify the explanation of the operation of this embodiment, all wiring patterns have a wiring pattern width of ltIm,
The wiring pattern spacing is also 1 μm.

It is assumed that all internal wirings have an internal wiring interval of μm, and all external wirings have an external wiring interval of 10am.

The internal wiring 201 has wiring patterns 218 to 2 as shown in the figure.
110 are connected, and the center of the wiring pattern 219 coincides with the center of the internal wiring 201. On the other hand, the external wiring 311 has wiring patterns 217 to 217 as shown in the figure.
Five wires of 2111 are connected. Assuming that the internal wiring 201 is manufactured at the same time as the wiring pattern, there will be almost no positional deviation and it can be ignored. Therefore, in a state where the internal wiring 201 and the external wiring 311 are electrically connected, the range indicated by the dashed line X is the allowable positional deviation range for the external wiring 311. In other words, the positional deviation with respect to the upper side of the drawing (-W direction) is as follows for wiring patterns 204 to 208,
The +W force direction is from 2010 to 2014. As a result, the permissible positional deviation range for the external wiring is approximately twice the sum of the internal wiring and external wiring, specifically, the wiring pattern 208.
Regarding 201O, it can be considered that the thickness is about 22 μm, excluding the connecting portion where the internal wiring and external wiring are connected together.

In the above case, there is one external wiring 311, but when multiple external wirings 311, 312...31m are arranged at equal intervals, the distance between the two external wirings must be equal to or greater than the internal wiring width. be. This is because when the maximum allowable positional deviation occurs, adjacent external wiring or internal wiring will be connected via the wiring pattern.

Next, using FIG. 5, the wiring patterns have the same width and spacing of 1 μm, and the internal wiring width, internal wiring spacing,
A case where the internal wiring width and external wiring interval are arbitrary will be described.

In FIG. 5, the external wiring widths 311, 312, and 313 are respectively 10 μm, 6 μm, and 8 μm, and the internal wiring widths 201,
Suppose that 202 and 203 are 8 μm, 4 μm, and 6 μm, respectively. Then, external wiring 311... and internal wiring 2
It is assumed that the wiring patterns 01, . . . constitute a pair, and their center positions coincide.

In this case, the positional deviation tolerance range is the value of the minimum pair of internal wiring width and external wiring width. In other words, the external wiring 31
2 and the internal wiring 202, and the range shown by Y between broken lines is 11 μm. Internal wiring at that time,
Regarding the spacing between external wires, the distance between adjacent internal wires and external wires in the drawing ±W force direction must be at least the above-mentioned positional deviation tolerance range of 11 μm or more.

In the above explanation, the following is an actual example. This example is similar to the effect shown in FIG. 4 above.

Assume that conductor wirings are formed on a printed circuit board at equal intervals with a radius of 50 μm and a conductor wiring interval of 50tIm. It is assumed that within the LSI chip, the wiring pattern width and interval are 1 μm, and the internal wiring width is 2.5 μm. The conductor wiring and the internal wiring are arranged in pairs with their centers aligned. In this case, the allowable range of positional deviation of external wiring is 10
It becomes 3 μm. As described in the explanation of FIG. 4, the external wiring interval is 50 μm, with the internal wiring width being 2.5 μm or more, and connection with adjacent wires can be sufficiently prevented.

From this result, the allowable range of positional deviation for external wiring is 103μ.
m, which is extremely large, and the maximum width in the ±W force direction when connecting the external wiring and internal wiring is only the sum of the external wiring width and the internal wiring width.

The above effects are more obvious than when using conventional pads. In this embodiment, the allowable range of positional deviation is 103 μm, whereas in the conventional case it is 10 μm to 20 μm, and the allowable range of positional deviation is approximately 10 times larger than that of the conventional case. On the other hand, in this embodiment, the distance for providing external wiring is the sum of the conductor wiring width of 50 μm and the conductor wiring interval of 50 μm, which is 100 μm, which is shorter than the conventional distance of 120 μm, so that wiring can be provided at high density. In the future, if either the conductor wiring width or the conductor wiring spacing on a printed circuit board becomes narrower, the distance for providing external wiring can be further reduced, and higher density can be achieved.

As shown in FIG. 6, the LSI of this embodiment is connected to, for example, a printed circuit board with its circuit configuration side facing.

In this embodiment, the wiring patterns are provided in parallel and at equal intervals, but the wiring patterns are not limited to this.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit device of the present invention does not use pads and has a larger tolerance for alignment accuracy during connection, making it more suitable for integration than when pads are used. Contributes to the integration of circuit devices.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the invention, and FIG. 3 is a partial sectional view taken along line A-B in FIG. 4 and 5 are partially enlarged sectional views of the area Z in FIG. 2, FIG. 6 is a diagram of the mounting state of the LSI of the present invention, and FIG. 7 is a configuration diagram of a conventional general LSI. . In the figure, 1 is a semiconductor integrated circuit device (LSI chip)
, 2 is a package, 3 is a pad, 4 is a wire, 5 is an external lead, 6 is a p-substrate, 7 is a silicon oxide film, 8 is an n-
well region, 9 is the first aluminum pattern, 1o
is the second aluminum pad, 11.24 is an insulating protective film, 41 is a crimp part of the pad, 12 is an internal circuit, 201
-201 are internal wirings, 211-21n are wiring patterns, and 311-31m are external wirings. (α) Heart 2 group (b) (C) Foil 2 group (rL> Chrysanthemum 6 zu%, <Route name 4-group/He 'E t> Bll ll-') 2 nr,;4
．． ? @Fig.

Claims (1)

[Scope of Claims] A plurality of mutually independent wiring patterns 211 to 21n formed on the semiconductor chip 1 and at equal intervals in a direction substantially perpendicular to the chip side in a region near the side of the chip, A semiconductor integrated circuit device characterized in that the wiring pattern has at least two wiring patterns connected to an internal wiring 20 inside a chip connected to the wiring pattern.