JPH0645386A - Semiconductor circuit device - Google Patents

Semiconductor circuit device

Info

Publication number
JPH0645386A
JPH0645386A JP4218572A JP21857292A JPH0645386A JP H0645386 A JPH0645386 A JP H0645386A JP 4218572 A JP4218572 A JP 4218572A JP 21857292 A JP21857292 A JP 21857292A JP H0645386 A JPH0645386 A JP H0645386A
Authority
JP
Japan
Prior art keywords
pad
pads
semiconductor circuit
bonding
circuit element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4218572A
Other languages
Japanese (ja)
Inventor
Takuya Konno
卓哉 今野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Chemi Con Corp
Original Assignee
Nippon Chemi Con Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Chemi Con Corp filed Critical Nippon Chemi Con Corp
Priority to JP4218572A priority Critical patent/JPH0645386A/en
Publication of JPH0645386A publication Critical patent/JPH0645386A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/4905—Shape
    • H01L2224/49051—Connectors having different shapes
    • H01L2224/49052—Different loop heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To provide a semiconductor circuit device in which a semiconductor circuit element is mounted in a compact structure. CONSTITUTION:Second pads are disposed in two rows to connect a semiconductor circuit element 11 to semiconductor patterns 16, the two conductor patterns 16 are disposed between the second pads 13 of a region farther from the element 1, and second pads 14 are provided continuously to the patterns 16. The patterns 16 to be connected to second pads 14 are so connected by deviating from a center line of the pads 14 that one side of the pad 14 and one side of the pattern 16 become linear, and so disposed that one side of the pad 14 in a wide direction is directed toward a direction of the adjacent pads 13.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】この発明は、ＩＣチップ等の半導
体回路素子で電極と導体パターン側の電極をワイヤボン
ディング法で接続した半導体回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit device in which an electrode and a conductor pattern side electrode of a semiconductor circuit element such as an IC chip are connected by a wire bonding method.

【０００２】[0002]

【従来の技術】従来より用いられているＩＣチップ等の
半導体回路素子と導体パターンの接続方法には様々なも
のがあるが、その中で最も一般的に使われているワイヤ
ボンディング法による接続は次のようになる。2. Description of the Related Art There are various conventional methods for connecting a semiconductor circuit element such as an IC chip to a conductor pattern. Among them, the most commonly used method is the wire bonding method. It looks like this:

【０００３】図５に示すように、セラミック等の絶縁材
料からなるプリント配線板（図示せず）の上に導体パタ
ーン４６をフォトエッチング等の手段により形成する。
この導体パターン４６と連続してダイボンディング領域
４７を設け、このダイボンディング領域４７の上に半導
体回路素子４１を接着固定する。そして前述のダイボイ
ンディング領域４７の外周に導体パターン４６の先端、
すなわちセカンドパット４３を配置する。この際のセカ
ンドパット４３の配置は、半導体回路素子４１とセカン
ドパット４３との間の距離をできるだけ短くできるよう
にダイボンディング領域４７の外周に整列させて配置す
る。このように配置したセカンドパット４３と半導体回
路素子４１の側の電極、すなわちファーストパット４２
を電気的に接続するために、ファーストパット４２とセ
カンドパット４３とをそれぞれ金あるいはアルミニウム
の細線よりなるボンディングワイヤで超音波ボンディン
グ等の方法により電気的に接続を行う。As shown in FIG. 5, a conductor pattern 46 is formed on a printed wiring board (not shown) made of an insulating material such as ceramics by means of photoetching or the like.
A die bonding region 47 is provided continuously with the conductor pattern 46, and the semiconductor circuit element 41 is bonded and fixed onto the die bonding region 47. Then, the tip of the conductor pattern 46 is formed on the outer periphery of the die boding area 47,
That is, the second pad 43 is arranged. At this time, the second pads 43 are arranged in alignment with the outer periphery of the die bonding region 47 so that the distance between the semiconductor circuit element 41 and the second pads 43 can be made as short as possible. The second pad 43 thus arranged and the electrode on the side of the semiconductor circuit element 41, that is, the first pad 42.
In order to electrically connect to each other, the first pad 42 and the second pad 43 are electrically connected to each other by a bonding wire made of a thin wire of gold or aluminum by ultrasonic bonding or the like.

【０００４】このようにして行うワイヤボンディング法
では、その作業性や信頼性を考慮するとセカンドパット
の幅は０．１５ｍｍ程度の幅を必要とし、また、隣接す
る各導体パターンの幅も０．０５ｍｍ程度の幅を必要と
する。また、セカンドパット同士の距離も０．０５ｍｍ
程度の距離を必要とする。In the wire bonding method thus performed, the width of the second pad needs to be about 0.15 mm in consideration of workability and reliability, and the width of each adjacent conductor pattern is 0.05 mm. It needs some width. Also, the distance between the second pads is 0.05mm.
Need some distance.

【０００５】ところで、ＬＳＩのように多数の回路素子
を有しボンディングワイヤも多数必要とするような場合
には従来の実装手段では極めて不都合である。すなわち
ボンディングパットが多数になるとセカンドパットを配
列した長さが半導体回路素子の大きさに比べ大きなもの
となってしまい、半導体回路素子を実装する面積が、全
体として大きなものとなる。そしてそれは電子機器の小
型化を阻害する原因の一つとなっていた。By the way, the conventional mounting means is extremely inconvenient when a large number of circuit elements are required and a large number of bonding wires are required as in an LSI. That is, when the number of bonding pads is large, the length of the second pads arranged becomes larger than the size of the semiconductor circuit element, and the area for mounting the semiconductor circuit element becomes large as a whole. And that was one of the causes that hinder the miniaturization of electronic devices.

【０００６】また、図６に示すように、セカンドパット
４３を配列の長さが長くなると、最も端部にあるセカン
ドパット４３と接続するボンディングワイヤ４８は、フ
ァーストパット４２付近で、ボンディングワイヤ４８同
士が非常に接近して配置されるようになる。このように
近接して配置するためには、製造の際に高度な精度が求
められ、製造コストの上昇を引き起こすことになる。ま
た、ボンディングワイヤ同士の接触等も発生しやすくな
り、半導体回路装置の品質の低下や、歩留りの低下等の
問題を引き起こすことになる。Further, as shown in FIG. 6, when the array length of the second pads 43 becomes long, the bonding wires 48 connecting to the second pads 43 at the end are the bonding wires 48 in the vicinity of the first pads 42. Will be placed very close together. In order to arrange them in such a close proximity, a high degree of accuracy is required in manufacturing, which causes an increase in manufacturing cost. In addition, the bonding wires are likely to come into contact with each other, which causes problems such as deterioration of the quality of the semiconductor circuit device and reduction of the yield.

【０００７】そこで、セカンドパットの配列の長さを短
縮し、半導体回路素子全体の小型化を図るため、例えば
特公昭５４−２０３１５号に示されたようにセカンドパ
ットを千鳥型に配置することが提案されている。このよ
うにセカンドパットを千鳥型に配置することによって、
セカンドパットと導体パターンが隣合って配置されるこ
とになり、全体としてセカンドパットの配列の幅が短縮
されるようになる。Therefore, in order to reduce the length of the arrangement of the second pads and downsize the entire semiconductor circuit element, for example, the second pads may be arranged in a staggered pattern as shown in Japanese Patent Publication No. 54-20315. Proposed. By arranging the second pads in a staggered pattern in this way,
Since the second pad and the conductor pattern are arranged adjacent to each other, the width of the arrangement of the second pad can be shortened as a whole.

【０００８】[0008]

【発明が解決しようとする課題】しかし、最近では電子
機器の小型化の要求はさらに高まり、それに伴い電子部
品の小型化や、電子部品のさらなる高密度実装が要求さ
れている。そして、半導体回路素子の分野でもよりコン
パクトな実装が要求されている。そこでこの発明では、
半導体回路素子をコンパクトに実装することを目的とす
る。However, recently, the demand for miniaturization of electronic equipment has further increased, and accordingly, miniaturization of electronic components and higher-density mounting of electronic components have been demanded. In the field of semiconductor circuit elements, more compact mounting is required. So in this invention,
The purpose is to compactly mount a semiconductor circuit element.

【０００９】[0009]

【課題を解決するための手段】そこでこの発明では、半
導体回路素子側の電極であるファーストパットとプリン
ト配線板上に設けられたセカンドパットをボンディング
ワイヤで電気的に接続するものにおいて、セカンドパッ
トを複数の列に配置するもので、半導体回路素子よりも
っとも離れた位置に一列に配列された第１のセカンドパ
ットを構成するセカンドパットのうちの任意のセカンド
パットの間に複数の導体パターンを配設するとともに、
該導体パターンとそれぞれ連続してセカンドパットを形
成し、順次半導体回路素子に近づくように第２、第３、
・・・、第Ｎのセカンドパットを形成した。さらに第
２、第３、・・・、第Ｎのセカンドパットと接続する導
体パターンはそれぞれのセカンドパットの中心線よりも
ずれた位置に接続するとともに、それぞれのセカンドパ
ットの幅広となった方向の端面が、隣接するセカンドパ
ットでより外周に位置するセカンドパットの方向に向く
ように配設したことを特徴とする。Therefore, in the present invention, the second pad is electrically connected by a bonding wire between the first pad which is the electrode on the semiconductor circuit element side and the second pad provided on the printed wiring board. It is arranged in a plurality of rows, and a plurality of conductor patterns are arranged between arbitrary second pads of the second pads forming the first second pad arranged in a row at a position farthest from the semiconductor circuit element. Along with
A second pad is formed continuously with each of the conductor patterns, and the second, third, and
..., the Nth second pad was formed. Further, the conductor patterns connected to the second, third, ..., Nth second pads are connected at positions deviated from the center line of the respective second pads, and in the direction in which the respective second pads are widened. It is characterized in that the end faces are arranged so as to face the direction of the second pad which is located on the outer periphery of the adjacent second pads.

【００１０】また、それぞれのセカンドパットと半導体
回路素子とを電気的に接続するワイヤボンディング法と
して、半導体回路素子により近い領域に位置するセカン
ドパットと接続するボンディングワイヤは、より遠い領
域に位置するセカンドパットと接続するボンディングワ
イヤよりも低い軌道を描くようにボンディングしたこと
を第２の特徴とする。Further, as a wire bonding method for electrically connecting the respective second pads and the semiconductor circuit element, the bonding wire connected to the second pad located in the area closer to the semiconductor circuit element is located in the farther area. The second feature is that the bonding is performed so as to draw a trajectory lower than the bonding wire connected to the pad.

【００１１】[0011]

【作用】以上のように、半導体回路装置のセカンドパッ
トを配列したことにより、例えばセカンドパットを２列
に配列した場合では、第１のセカンドパットのセカンド
パットの両脇に第２のセカンドパットに連続する導電パ
ターンが存在する。そして第２のセカンドパットは、隣
接する第１のセカンドパットがある方向に第２のセカン
ドパットの幅広部分が向くようになる。従って、第２の
セカンドパットのうち任意の２つのセカンドパットと、
その２つのセカンドパットの間に挟まれた第１のセカン
ドパットをみると、第２のセカンドパットの幅広の部分
が、第１のセカンドパットと重なるように配置され、３
つのセカンドパットは全体として小さく配置されるよう
になる。このような３つのセカンドパットが連続して配
置される半導体回路装置では従来よりもセカンドパット
をより高密度に配設できるようになる。As described above, by arranging the second pads of the semiconductor circuit device, for example, when the second pads are arranged in two rows, the second pads are provided on both sides of the second pad of the first second pad. There is a continuous conductive pattern. Then, in the second second pad, the wide portion of the second second pad is oriented in the direction in which the adjacent first second pad is present. Therefore, any two second pads of the second second pad,
Looking at the first second pad sandwiched between the two second pads, the wide portion of the second second pad is arranged so as to overlap with the first second pad.
The two second pads will be placed smaller as a whole. In the semiconductor circuit device in which such three second pads are continuously arranged, the second pads can be arranged at a higher density than in the conventional case.

【００１２】また、半導体回路素子に近い領域に位置す
るセカンドパットとのボンディングでは、ボンディンク
ワイヤがより低い軌道を描くようにボンディングしたこ
とにより、半導体回路素子に近い領域に位置するセカン
ドパットと接続するボンディングワイヤの上に半導体回
路素子に遠い領域に位置するセカンドパットと接続する
ボンディングワイヤが位置するようになる。従って、ボ
ンディングワイヤ同士の距離を充分にとることができる
ようになり、ボンディングワイヤが互いに接触すること
がなくなる。Further, in the bonding with the second pad located in the region close to the semiconductor circuit element, the bonding is performed so that the bonding wire draws a lower trajectory, so that it is connected to the second pad located in the region close to the semiconductor circuit element. The bonding wire, which is connected to the second pad located in a region far from the semiconductor circuit element, is located on the bonding wire. Therefore, it becomes possible to secure a sufficient distance between the bonding wires, and the bonding wires do not come into contact with each other.

【００１３】[0013]

【実施例】次にこの発明の実施例を説明する。図１はこ
の発明の半導体回路装置のセカンドパットの配列の第１
の実施例を示す図面であり、図２は第１の実施例の半導
体回路素子とセカンドパットの間をワイヤボンディング
した状態を示す斜視図である。また図３はこの発明の第
２の実施例を示す図面である。Embodiments of the present invention will be described below. FIG. 1 is a first arrangement of a second pad of a semiconductor circuit device according to the present invention.
2 is a perspective view showing a state in which the semiconductor circuit element of the first embodiment and the second pad are wire-bonded. FIG. 3 is a drawing showing a second embodiment of the present invention.

【００１４】図１に示すように、セラミック等の絶縁材
料からなるプリント配線板（図示せず）の上には導体パ
ターン１６をフォトエッチング等の手段により形成して
ある。そして、このプリント配線板には半導体回路素子
１１を接続するためのダイボンディング領域１７が導体
パターン１６と連続して形成してあり、ダイボンディン
グ領域１７に半導体回路素子１１を接着固定する。ま
た、前述のダイボンディング領域１７の外周には半導体
回路素子１１と導体パターン１６を電気的に接合するた
めに、導体パターン１６と連続したセカンドパットを配
置する。配設するセカンドパットは例えば幅が０．１５
ｍｍ、長さが０．４２ｍｍの大きさで設け、ワイヤボン
ディングに必要な面積を確保する。また、導体パターン
１６は０．０５ｍｍの幅で設けるとともに、セカンドパ
ット同士、あるいはセカンドパットと導体パターン１６
の距離は０．０５ｍｍの距離をあけて配設するようにし
た。セカンドパットの配置としてはセカンドパットを２
列に配置し、半導体回路素子より遠い領域に第１のセカ
ンドパット１３を配置した。そしてそれぞれの第１のセ
カンドパット１３の間に２本の導体パターン１６を配設
し、それぞれの導体パターン１６と連続して第２のセカ
ンドパット１４を設けた。第２のセカンドパット１４と
導体パターン１６の接続はセカンドパットの一辺と導体
パターン１６の一方の辺が一直線となるように、第２の
セカンドパット１４のそれぞれの中心線とはずらして配
設した。さらに第２のセカンドパット１４と連続した導
体パターン１６からみて第２のセカンドパット１４の中
心線方向、すなわち第２のセカンドパット１４の幅広と
なった方向の辺が、隣接する第１のセカンドパット１３
のある方向を向いて配設するようにした。このようにセ
カンドパットを配列することにより、１．２ｍｍの間に
９個のセカンドパットを配設することができる。As shown in FIG. 1, a conductor pattern 16 is formed on a printed wiring board (not shown) made of an insulating material such as ceramics by means of photoetching or the like. A die bonding region 17 for connecting the semiconductor circuit element 11 is formed continuously with the conductor pattern 16 on the printed wiring board, and the semiconductor circuit element 11 is bonded and fixed to the die bonding region 17. In addition, a second pad continuous with the conductor pattern 16 is arranged on the outer periphery of the die bonding region 17 in order to electrically bond the semiconductor circuit element 11 and the conductor pattern 16. The second pad to be arranged has a width of 0.15, for example.
mm and the length is 0.42 mm, and an area necessary for wire bonding is secured. Further, the conductor pattern 16 is provided with a width of 0.05 mm, and the second pads are connected to each other or the second pad and the conductor pattern 16 are connected to each other.
The distance was set to be 0.05 mm. As for the placement of the second pat, the second pat is 2
The first second pads 13 are arranged in a row and are arranged in a region farther from the semiconductor circuit element. Then, the two conductor patterns 16 were arranged between the respective first second pads 13, and the second second pads 14 were provided continuously to the respective conductor patterns 16. The connection between the second second pad 14 and the conductor pattern 16 is arranged so as to be offset from the respective center lines of the second second pad 14 so that one side of the second pad and one side of the conductor pattern 16 are aligned. . Furthermore, when viewed from the conductor pattern 16 continuous with the second second pad 14, the side in the center line direction of the second second pad 14, that is, the side in the direction in which the second second pad 14 becomes wider is adjacent to the first second pad 14. Thirteen
It is arranged so as to face in a certain direction. By arranging the second pads in this manner, nine second pads can be arranged within 1.2 mm.

【００１５】そして、図２に示すように、半導体回路素
子のファーストパット１２とセカンドパットをワイヤボ
ンディングを行って電気的に接続する。ワイヤボンディ
ングに用いるボンディングワイヤ１８は例えば直径が２
５μｍ程度の金線を用いる。ワイヤボンディングは超音
波ボンディング法等の従来より知られている方法によっ
てボンディングを行うが、第１のセカンドパット１３と
接続するボンディングワイヤ１８は、第２のセカンドパ
ット１４と接続するボンディングワイヤ１８よりも高い
軌道を描くようにボンディングを行った。Then, as shown in FIG. 2, the first pad 12 and the second pad of the semiconductor circuit element are electrically connected by wire bonding. The bonding wire 18 used for wire bonding has, for example, a diameter of 2
A gold wire of about 5 μm is used. Although wire bonding is performed by a conventionally known method such as an ultrasonic bonding method, the bonding wire 18 connected to the first second pad 13 is more than the bonding wire 18 connected to the second second pad 14. Bonding was performed so as to draw a high trajectory.

【００１６】セカンドパットの配置の設計仕様によって
は、半導体回路素子の直上から見ると、例えば最端部に
位置する第２のセカンドパットと接続するボンデンィグ
ワイヤと、その隣の第１のセカンドパットとの接続する
ボンディングワイヤは極めて近接して、場合によっては
交差しているようになる。しかし、第１のセカンドパッ
トと接続するボンディングワイヤは、第２のセカンドパ
ットと接続するボンディングワイヤよりも高い軌道を描
いているので、実際にはボンディングワイヤ同士は離れ
て配置されるようになり、ボンディングワイヤ同士が接
触することはない。Depending on the design specifications of the layout of the second pad, when viewed from directly above the semiconductor circuit element, for example, the bonding wire connected to the second second pad located at the end and the first second wire next to the bonding wire. The bonding wires that connect to the pads are in close proximity and may even intersect. However, since the bonding wire connecting to the first second pad has a higher trajectory than the bonding wire connecting to the second second pad, the bonding wires are actually arranged apart from each other. The bonding wires do not touch each other.

【００１７】また、ワイヤボンディングに用いるボンデ
ィングワイヤとして絶縁被覆したボンディングワイヤを
用いることにより、ボンディングワイヤ同士が接触した
場合でも電気的に短絡することはなく、さらに信頼性の
向上を図ることができる。Further, by using an insulating coated bonding wire as the bonding wire used for wire bonding, even if the bonding wires come into contact with each other, there is no electrical short circuit, and the reliability can be further improved.

【００１８】その後に、半導体回路素子の周辺に樹脂を
充填してチップコートを行い、半導体回路素子及びボン
ディングしたボンディングワイヤを汚染から保護すると
ともに機械的にも保護する。またこのチップコートによ
って耐湿性の向上の向上も図ることができる。After that, resin is filled in the periphery of the semiconductor circuit element and chip coating is performed to protect the semiconductor circuit element and the bonded bonding wire from contamination and mechanically. Further, the chip coat can also improve the moisture resistance.

【００１９】次に、この発明の第２の実施例について説
明する。プリント配線板への導体パターンの形成方法や
ダイボンディングについては第１の実施例と全く同様の
方法で行った。さらに、セカンドパットや導体パターン
の幅、セカンドパットと導体パターンの距離も全く同じ
条件で行った。セカンドパットの配列方法としては、図
３に示すように、それぞれの第１のセカンドパット２３
の間に４本の導体パターン２６を配設し、それぞれの導
体パターン２６と連続してセカンドパットを設けた。そ
のセカンドパットは４本の導体パターン２６のうち第１
のセカンドパット２３に隣接する導体パターン２６と連
続したセカンドパットを第２のセカンドパット２４と
し、第２のセカンドパット２４に連続した導体パターン
２６に挟まれる２本の導体パターン２６と連続するセカ
ンドパットを第３のセカンドパット２５とするようにし
た。導電パターン２６との接続は第２のセカンドパット
２４、第３のセカンドパット２５ともにそれぞれに接続
されるセカンドパットの中心線よりずらして、セカンド
パットの一辺と導体パターン２６の一辺が一直線となる
ように接続した。さらに第２のセカンドパット２４の導
体パターンからみて中心線の方向、すなわち、第２のセ
カンドパット２４の幅広となった方向の辺が、隣接する
第１のセカンドパット２３をある方向を向くように、第
３のセカンドパット２５の幅広となった方向の辺が、前
述の隣接する第２のセカンドパット２４がある方向を向
くように配設した。このようにセカンドパットを配列す
ることにより１．２ｍｍの間に１０個のセカンドパット
を配列することができるようになる。Next, a second embodiment of the present invention will be described. The method for forming the conductor pattern on the printed wiring board and the die bonding were the same as those in the first embodiment. Furthermore, the width of the second pad and the conductor pattern and the distance between the second pad and the conductor pattern were also set to be exactly the same. As a method for arranging the second pads, as shown in FIG.
Four conductor patterns 26 were arranged between the two, and a second pad was provided continuously with each conductor pattern 26. The second pad is the first of the four conductor patterns 26.
The second pad that is continuous with the conductor pattern 26 adjacent to the second pad 23 is the second second pad 24, and the second pad that is continuous with the two conductor patterns 26 sandwiched by the conductor pattern 26 that is continuous with the second second pad 24. As the third second pad 25. The connection with the conductive pattern 26 is displaced from the center line of the second pad connected to each of the second and third second pads 24 and 25 so that one side of the second pad and one side of the conductor pattern 26 are aligned with each other. Connected to. Further, the direction of the center line when viewed from the conductor pattern of the second second pad 24, that is, the side in the direction in which the second second pad 24 becomes wider faces the adjacent first second pad 23 in a certain direction. The side of the third second pad 25 in the widened direction is arranged so as to face the direction in which the adjacent second second pad 24 is located. By arranging the second pads in this way, it becomes possible to arrange 10 second pads within 1.2 mm.

【００２０】その後のワイヤボンディングは第１の実施
例と同様に、半導体回路素子に近い領域のセカンドパッ
トと接続するボンデンィグワイヤは、より遠い領域のセ
カンドパットと接続するボンデンィグワイヤよりも低い
軌道を描くようにワイヤボンディングを行った。また、
その後のチップコート等の処理は第１の実施例と全く同
様の方法で行った。In the subsequent wire bonding, as in the first embodiment, the bonding wire connected to the second pad in the region close to the semiconductor circuit element is more than the bonding wire connected to the second pad in the farther region. Wire bonding was performed so as to draw a low trajectory. Also,
Subsequent treatments such as chip coating were performed in the same manner as in the first embodiment.

【００２１】図４に示すように、比較例として従来の千
鳥型配置によりセカンドパットを形成してみる。セカン
ドパットの幅、導体パターンの幅、セカンドパット同士
や、セカンドパットと導体パターンの距離は前述の実施
例と同じ条件で行った。従来の千鳥型配置では、１．２
ｍｍの間にセカンドパットを８個形成することができ
る。As a comparative example, as shown in FIG. 4, a second pad is formed by a conventional staggered arrangement. The width of the second pad, the width of the conductor pattern, the second pads, and the distance between the second pad and the conductor pattern were set under the same conditions as those in the above-described examples. 1.2 in the conventional staggered arrangement
Eight second pads can be formed in mm.

【００２２】以上説明したように、この発明によると従
来の千鳥型配置に比べ、セカンドパットを高密度に実装
することができるようになる。しかも、半導体回路素子
と接続するボンディングワイヤ同士も充分な距離をとる
ことができるために、ボンディングワイヤ同士が接触す
ることがない。As described above, according to the present invention, the second pads can be mounted at a higher density than the conventional staggered arrangement. Moreover, since the bonding wires connected to the semiconductor circuit element can also have a sufficient distance, the bonding wires do not come into contact with each other.

【００２３】[0023]

【発明の効果】この発明の半導体回路装置では、従来の
セカンドパットの配置よりも高密度にセカンドパットを
配置することができるようになり、半導体回路装置全体
の小型化を図ることができるようになる。また、セカン
ドパットの配置が短くなることにより、最端部のセカン
ドパット接続するボンデンィングワイヤと、隣接するセ
カンドパットと接続するボンディングワイヤ同士の距離
も充分にとることができるようになる。また、半導体回
路素子に近い領域に位置するセカンドパットとのボンデ
ィングでは、ボンディンクワイヤがより低い軌道を描く
ようにボンディングしたことにより、半導体回路素子に
近い領域に位置するセカンドパットと接続するボンディ
ングワイヤの上に半導体回路素子に遠い領域に位置する
セカンドパットと接続するボンディングワイヤが位置す
るようになる。従ってボンディングワイヤ同士の距離を
充分にとることができるようになり、ボンディングワイ
ヤ同士が接触することがなくなり、半導体回路装置の信
頼性の向上を図ることができる。According to the semiconductor circuit device of the present invention, the second pads can be arranged at a higher density than the conventional arrangement of the second pads, and the overall size of the semiconductor circuit device can be reduced. Become. Further, since the second pads are arranged in a shorter length, it is possible to ensure a sufficient distance between the bonding wire at the end of the second pad, which is connected to the second pad, and the bonding wires, which are connected to the adjacent second pads. Also, in bonding with the second pad located in the region close to the semiconductor circuit element, the bonding wire connecting with the second pad located in the region close to the semiconductor circuit element is used by bonding so that the bonding wire draws a lower trajectory. A bonding wire for connecting to a second pad located in a region distant from the semiconductor circuit element is located on the upper side. Therefore, it becomes possible to secure a sufficient distance between the bonding wires, the bonding wires do not come into contact with each other, and the reliability of the semiconductor circuit device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の半導体回路装置のセカンドパットの
配列の第１の実施例を示す図面である。FIG. 1 is a diagram showing a first embodiment of an arrangement of second pads of a semiconductor circuit device according to the present invention.

【図２】この発明の半導体回路装置の第１の実施例でワ
イヤボンディングした状態を示す斜視図である。FIG. 2 is a perspective view showing a state of wire bonding in the first embodiment of the semiconductor circuit device of the present invention.

【図３】この発明の半導体回路装置のセカンドパットの
配列の第２の実施例を示す図面である。FIG. 3 is a view showing a second embodiment of the arrangement of the second pads of the semiconductor circuit device of the present invention.

【図４】この発明の比較例で従来の半導体回路装置のセ
カンドパットの配列を示す図面である。FIG. 4 is a view showing an arrangement of second pads of a conventional semiconductor circuit device in a comparative example of the present invention.

【図５】従来の半導体回路装置のセカンドパットの配列
を示す図面である。FIG. 5 is a view showing an arrangement of second pads of a conventional semiconductor circuit device.

【図６】従来の半導体回路装置の要部を示す図面であ
る。FIG. 6 is a view showing a main part of a conventional semiconductor circuit device.

【符号の説明】[Explanation of symbols]

１１、２１、３１、４１ 半導体回路素子 １２、２２、３２、４２ ファーストパット ３３、４３ セカンドパット １３、２３ 第１のセカンドパット １４、２４ 第２のセカンドパット ２５ 第３のセカンドパット １６、２６、３６、４６ 導体パターン １７、２７、３７、４７ ダイボンディング領域 １８、４８ ボンディングワイヤ 11, 21, 31, 41 Semiconductor circuit element 12, 22, 32, 42 First pad 33, 43 Second pad 13, 23 First second pad 14, 24 Second second pad 25 Third second pad 16, 26, 36, 46 Conductor pattern 17, 27, 37, 47 Die bonding area 18, 48 Bonding wire

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】半導体回路素子の電極であるファーストパ
ットとプリント配線板に設けたセカンドパットをボンデ
ィングワイヤで電気的に接続するものにおいて、セカン
ドパットが複数の列に配置されるセカンドパットの配置
方法として、半導体回路素子より最も離れた位置に一列
に配置された第１のセカンドパットのうちの任意のセカ
ンドパットの間に複数の導体パターンを配設するととも
に、該導体パターンとそれぞれ連続してセカンドパット
を形成し、順次半導体回路素子に近づくように第２、第
３、・・・、第Ｎのセカンドパットを配設するものであ
って、前記第２、第３、・・・、第Ｎのセカンドパット
と接続する導体パターンはそれぞれが接続されるセカン
ドパットの中心線よりも一方にずれた位置に接続すると
ともに、それぞれのセカンドパットの幅広となった方向
の一辺が、隣接するセカンドパットでより外周に位置す
るセカンドパットの方向を向くように配設したことを特
徴とする半導体回路装置。1. A method of arranging a second pad in which a first pad, which is an electrode of a semiconductor circuit element, and a second pad provided on a printed wiring board are electrically connected by a bonding wire. As a plurality of conductor patterns are arranged between arbitrary second pads of the first second pads arranged in a line at a position farthest from the semiconductor circuit element, and the conductor patterns are continuously connected to the second patterns. A pad is formed, and second, third, ..., Nth second pads are arranged so as to sequentially approach the semiconductor circuit element, and the second, third ,. The conductor pattern to be connected to the second pad of is connected to the position shifted to one side from the center line of the second pad to be connected, and each The semiconductor circuit device in which the direction of one side became wider second pad, characterized in that arranged so as to face the direction of the second pad located on more outer peripheral in the adjacent second pads. 【請求項２】第１のセカンドパットと接続するボンディ
ングワイヤが最も高い軌道を描き、半導体回路素子に近
づくほどボンディングワイヤの軌道が低くなるようにワ
イヤボンディングした請求項１記載の半導体回路装置。2. The semiconductor circuit device according to claim 1, wherein the bonding wire connected to the first second pad draws the highest trajectory, and the bonding wire has a lower trajectory as it approaches the semiconductor circuit element.
JP4218572A 1992-07-24 1992-07-24 Semiconductor circuit device Pending JPH0645386A (en)

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JP4218572A JPH0645386A (en) 1992-07-24 1992-07-24 Semiconductor circuit device

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JP4218572A JPH0645386A (en) 1992-07-24 1992-07-24 Semiconductor circuit device

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JPH0645386A true JPH0645386A (en) 1994-02-18

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484551B1 (en) * 1997-07-07 2005-08-12 프리스케일 세미컨덕터, 인크. Semiconductor package bond post configuration and method of manufacturing therof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100484551B1 (en) * 1997-07-07 2005-08-12 프리스케일 세미컨덕터, 인크. Semiconductor package bond post configuration and method of manufacturing therof

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