JPH04129086A - Stuff circuit - Google Patents

Abstract

PURPOSE:To enable making a circuit scale small by providing a FIFO outputting a half flag, a PG circuit inputting a read-out clock and half flag of FIFO to output a gate signal, and an AND circuit taking and AND of gate signal and clock to output the read-out clock of FIFO. CONSTITUTION:When the data quantity remained in the FIFO 3 is larger than the half of the storage capacity, the active period of the gate signal (f) is made larger than the average read-out time slot by the PG circuit 4 to increase the data quantity to be read out from the FIFO 3. On the contrary, when the data quantity amount remained in the FIFO 3 is smaller than a half of the storage capacity, the active period of the read-out gate signal (f) is made shorter than the average read-out time slot by the PG circuit 4 to reduce the data quantity to be read out from the FIFO 3. In the AND circuit 5, the AND of the read-out gate signal (f) and read-out clock (g) inputted from a read-out clock input terminal 7 is taken to output the read-out clock (d) of FIFO to the FIFO 3. By this procedure, a count circuit for read/write data quantity is unnecessitated and the circuit scale can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a stuffing circuit for stuffing and transmitting asynchronous data onto a transmission path.

BACKGROUND OF THE INVENTION A conventional stuff circuit will be explained with reference to FIG. Input data h input from the data input terminal 8 is written to the FIFOIO at the timing of the write clock i input from the write clock input terminal 9. FIFOIO
outputs the output transmission line data j to the data output terminal 13 at the timing of the FIFO read clock. The read/write data amount counting circuit 15 uses the write clock i and the FI
Data amount difference J that represents the difference between the written data amount and the read data amount by counting the FO read clock k
Output. When the data amount difference ρ indicates that the amount of data written is larger than the amount read, the PG circuit 11 makes the active section of the gate signal m longer than the average read time slot, and increases the amount of data read from the FIFOIO. On the other hand, when the difference in data amount, 1, indicates that the write amount of data is less than the read amount, the PG0 circuit 1 shortens the fuction section of the gate signal m by the average read time slot J, and the FIFOI
Reduce the amount of data read from O. AND circuit 12
is the AND of the gate signal m and the readout ttsukn.
Set the IFO read clock k. In this way F
The read amount of IFOIO data is controlled so that the average write amount and read amount equal 2.

Problems to be Solved by the Invention However, in the conventional system, in addition to FIFO, FIFO0
It requires a circuit to count read and write data, which has the disadvantage of increasing the circuit scale.

The present invention was made in view of the above-mentioned conventional circumstances, and
Accordingly, an object of the present invention is to provide a novel stuffing circuit which eliminates the above-mentioned drawbacks existing in the prior art and makes it possible to reduce the circuit scale.

Means for Solving the Problems In order to achieve the above object, the stuffing circuit according to the present invention includes a FIFO that outputs a half flag indicating whether the amount of data inside the FIFO is above or below half of the storage capacity, a clock and A PG that inputs the half flag and outputs a gate signal that controls the amount of output data read from the FIFO.
and an AND circuit that performs an AND operation on the gate signal and the clock, and outputs a tally signal based on the reading of the FIFO, and when the amount of data inside the FIFO is more than half of the storage capacity, It is characterized in that a stuffing operation is performed by reading more data than the average amount of data read, and when the amount of data inside the FIFO is less than half of the storage capacity, reading less than the average amount of data read.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram thereof.

Referring to FIGS. 1 and 2, input data a input from data input terminal 1 is transferred to FIFO 3 at the timing of write clock b input from write clock input terminal 2.
will be written to. FIFO3 outputs output data C to data output terminal 6 at the timing of FIFO read clock d.
At the same time, it also outputs a half flag e indicating whether the remaining amount of data inside PIFO3 is above or below half of the storage capacity.When the amount of data remaining inside PIFO3 is above half of the storage capacity, The PG0 circuit makes the active section of the gate signal f longer than the average read time slot to increase the amount of data read from FIFO3.4On the contrary, when the amount of data remaining inside PIFO3 is less than half of the storage capacity, the PG0 circuit increases the amount of data read from FIFO3. The active period of the read gate signal f is made shorter than the average read length time slot to reduce the amount of data read from FI and FO3.

In the AND circuit 5, - is the read gate signal and the read clock g input from the read clock input terminal 7.
Take AND with FIFO reading and F
Output to IFO3. In this way, the amount of data read from the FIFO 3 is controlled so that the amount of data written and the amount of data read are equal on average.

As described in detail, the present invention eliminates the need for a read/write data amount counting circuit compared to the conventional system, making it possible to reduce the circuit scale.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is an operation timing diagram of FIG. 1, and FIG. 3 is a block diagram of a conventional circuit. 1...Data input terminal, 2...Write clock input terminal, 3...FIFO14...PG circuit, 5...
・AND circuit, 6... data output terminal, 7... read clock input terminal, 8... data input terminal, 9...
...Write clock input terminal, 10...FIFOl
ll-...PG circuit, 12...AND circuit, 13...
・Data output terminal, 14...Read clock input terminal, 15...Read/write data amount count circuit, a...
・Input data, b...Write clock, C...Output data, d...FIFO read clock, e...
・Half flag, f...gate signal, g...read clock, h...input data, i...write clock, j...output data, k...FIFO read clock, ρ... Difference in data amount, m...gate signal, n...reading ratio clock

Claims (2)

[Claims] (1) A FIF that outputs a half flag indicating whether the amount of data inside the FIFO is “above” or “below” half of the storage capacity.
a PG circuit which inputs the read clock of the FIFO and the half flag and outputs a gate signal for controlling the amount of output data read from the FIFO;
and an AND circuit that outputs a read clock. (2) The PG circuit increases the amount of data read from the FIFO by making the active period of the gate signal longer than the average read time slot when the half flag indicates the "above" state, and increases the amount of data read from the FIFO. represents the "lower", the active period of the gate signal is made shorter than the average read time slot, and the FIF
The flap circuit according to claim 1, further characterized in that the amount of data read from O is reduced.