JPH04123439U - Parity debug circuit - Google Patents

Abstract

(57) [Summary] [Purpose] In the parity circuit, by specifying a specific data bit of a specific address and making it possible to generate an error, it is possible to freely perform parity debugging on any address and data bit. do. [Structure] An address at which an error is to be caused and its data bit are specified in the parity generation address register 2 and the bit inversion specification data register 4, respectively. A matching address is detected by the address comparison circuit 3, and the data set in the data inversion enable circuit 5 is sent out. As a result, the data logic inversion circuit 6 inverts only the designated data bit, and the parity detection circuit 1 detects an error.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention is a circuit with a parity check function, more specifically, a circuit with a parity check function. This invention relates to a parity debug circuit that can debug the normality of a check.

0002

[Conventional technology]

Conventionally, a parity detection circuit detects parity by fixing one bit of data. I was checking to see if I could detect errors.

0003

[Problem that the idea aims to solve]

Therefore, it was difficult to generate an error under certain circumstances. For example, DMA (direct memory access) operations over which the processor does not have control For example, when you want to evaluate by generating an error in the middle or final access of the work. It was impossible for an error to occur at a specific address because the processor could not be involved. The purpose of this invention is to specify specific data bits at specific addresses to prevent errors from occurring. You can freely parse any address and data bits by The aim is to provide a parity debug circuit that can generate parity errors. Ru.

0004

[Means to solve the problem]

In order to achieve the above object, the parity debug circuit according to the present invention has a parity error. A parity generation address setting means for setting an address that generates a parity, and a counter an inversion bit designation means for designating data bits to be inverted; When the address set in the parity generation address setting means matches, the above-mentioned inversion A means for inverting the bit corresponding to the bit specified by the bit specifying means is provided, and a special It is configured so that a parity error can be generated for a specific bit of a fixed address. There is.

[0005]

【Example】

Hereinafter, the present invention will be explained in more detail with reference to the drawings and the like. FIG. 1 is a circuit block diagram showing an embodiment of the parity debug circuit according to the present invention. Ru. An arbitrary parity bit p is added to the n-bit address bus 7 and the m-bit data. An additional data bus 8 is connected to this circuit. Parity generation address to specify the address that generates a parity error. A register 2 is provided. In addition, bit inversion specification is used to specify which bit of data is to be inverted. A data register 4 is provided. The desired address and inverted data bit are stored in the parity generation address register 2. and bit inversion designation data register 4 through data bus 8. It will be done.

[0006] The output of parity generation address register 2 and the address of address bus 7 are The address is input to the address comparison circuit 8, and it is detected whether or not the addresses match. The address comparison circuit 8 includes n exclusive OR circuits and one AND circuit. Each bit of the address bus 7 and the parity generation address register 2 are If all of the set address bits match, a match signal (high level) is output. output). The outputs of the address comparison circuit 3 and the bit inversion specification data register 4 are data inversion signals. The signal is input to the enable circuit 5. The data inversion enable circuit 5 is composed of m AND circuits 5, and the match signal is When input, m bits including the bit specified to be inverted (high level) Outputs a signal.

[0007] This signal consisting of m bits and the data on the data bus 8 are processed by a data logic inversion circuit. 6. The data logic inversion circuit 6 is composed of m exclusive OR circuits, and Of the m data bits sent from the inversion enable circuit 5, the high level Data on data bus 8 passes through exclusive OR circuit where data bits are input Only bits are inverted. The data on the data bus 8 that has passed through the data logic inversion circuit 6 is then sent to a parity detection circuit. 1 and parity detection is performed. For example, consider the case where an error occurs in the second bit of data at address A. In other words, address A is in parity generation address register 2, and bit inversion designation data is stored in parity generation address register 2. The second data bit of data register 4 is set to a high level. This allows the Since only the output of the second bit of data from the data logic inversion circuit 6 is inverted, parity detection is possible. Output circuit 1 detects a parity error for an abnormality in the second bit of data at address A. can.

[0008]

[Effect of the idea]

As explained above, the parity debug circuit according to the present invention can detect parity errors. Specify the address to be generated and the bits of its data, and By inverting the specified data bit, the specified data bit of the specified address is and parity error debugging. Therefore, it is easy to cause an error to occur at an address where you want an error to occur. This makes it easy to evaluate the parity detection circuit. In addition, since the configuration is to invert the bits set in the bit inversion specification means, the original Errors can occur without the person debugging the data being aware of them.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a parity debug circuit according to the present invention.

[Explanation of symbols]

1...Parity detection circuit 2...Parity generation address register 3...Address comparison circuit 4...Bit inversion specification data register 5...Data inversion enable circuit 6...Data logic inversion circuit 7…Address bus 8...Data bus

Claims (1)

[Scope of utility model registration request] 1. A parity generation address setting means for setting an address that causes a parity error, an inversion bit specification means for specifying a data bit to be inverted, and an address and an address set in the parity generation address setting means. A parity debugging circuit characterized in that the parity debugging circuit is provided with means for inverting a bit corresponding to the bit specified by the inversion bit specifying means when the above bits match, thereby making it possible to generate a parity error for a specific bit of a specific address. .