JPH04122051A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize low capacity and high density of an aerial wiring, to improve yield and to enable simplification of a manufacture process by forming a conductor pillar, by using a bridge foundation resist and by forming an upper layer wiring by etching, etc. CONSTITUTION:A conductor pillar 6 is formed on a lower wiring connection part 4a on a semiconductor substrate 1 and bridge foundation resist 7 is applied all over the substrate 1. Then, the resist 7 on the pillar 6 is removed to form a clearance 8 in a periphery of the pillar 6, the resist 7 is baked, and the resist 7 hangs down to fill the clearance 8 and to eliminate a corner 7b thereof. Then, an upper layer wiring metal 9' is formed all over the substrate 1, a resist 10 is applied to the metal 9' and the resist 10 is exposed and developed for patterning. The metal 9' is etched using the patterned resist 10 as a mask, and the patterned resist 10 and the resist 7 are peeled off simultaneously. Thereby, it is possible to simplify a process, to realize low capacity and high density of an aerial wiring and to improve yield.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for manufacturing semiconductor devices such as ICs, and more specifically, to the formation of aerial wiring therein.

(b) Conventional technology Ultra-high-speed operation or low-current digital or analog I
In low Nf high frequency elements such as C1 or high electron mobility transistors, aerial wiring is required to reduce wiring capacitance.

A conventional method for forming aerial wiring will be described below with reference to FIG. FIG. 2(a) shows a cross-linked base resist 17. FIG. 3 is a cross-sectional view of a main part showing a state in which a plating electrode metal 15 is formed. 14.12 is
A lower layer wiring and an insulating film (passivation) are shown respectively, and a contact hole 13 is opened in the insulating film 12, and the lower layer wiring 14 is exposed upward. The bridging base resist 1-17 is formed except on the contact hole 13, and has a surface 15b, a side surface 15a, and a lower electrode 14.
A plating peripheral electrode metal layer 5 is deposited on the exposed portion of the electrode.

FIG. 2(b) shows a state in which the upper layer wiring resist 20 has been formed. The upper layer wiring resist 20 is patterned by photolithography so as to exclude portions where aerial wiring is to be formed.

FIG. 2(C) shows a state in which aerial wiring 19 has been formed by plating. Gold (Au) is mainly used as the plating material.

FIG. 2(d) shows a state in which only the upper layer wiring resist 20 has been removed. Further, unnecessary plating electrode metal 15 is removed by etching [see FIG. 2(e)]. Finally, when the bridging base resist 17 is removed using an organic solvent, the aerial wiring 19 is left floating in the air (see second figure).

(c) Problems to be Solved by the Invention In the above-mentioned conventional method for forming aerial wiring, in order to reduce the capacitance and increase the density of the aerial wiring, it is necessary to form a connecting portion (contact hole) between the lower layer wiring 14 and the upper layer wiring 19. 13 has been made smaller, the upper layer wiring 19 itself has also been made finer, and the upper layer wiring work 9 has also been made smaller.
If the wires are wired adjacent to each other, the distance between the wires must also be reduced. Furthermore, in order to reduce the capacitance at the intersection between the upper layer wiring 19 and the lower layer wiring 14, it is necessary to thicken the bridging base 19a and increase the distance at the intersection between the upper layer wiring 19 and the lower layer wiring 14.

A bridging base resist 17 is used to make the connecting portion 13 between the lower layer wiring 14 and the upper layer wiring 19 smaller and to thicken the bridging base 19a.
If it becomes thicker, it becomes difficult to deposit electrode metal for plating on the side surface 15a of the bridging base resist, and plating defects occur, making it impossible to form aerial wiring with a high yield [Fig. 2 (a)
)reference〕.

In addition, when patterning the upper layer wiring resist 20 is made finer in order to increase the density and lower the capacitance of the aerial wiring, the upper layer wiring resist 20 is formed by plating to form the upper layer wiring 19.
It becomes difficult for the plating solution to enter the pattern, resulting in plating defects.

Furthermore, if the spacing between the upper layer wirings 19 is small, the upper layer wirings will be connected to each other, resulting in a decrease in yield. From this point of view as well, it is difficult to increase the density (miniaturization) and reduce the capacitance of aerial wiring.

In addition, since the aerial wiring is formed by plating, there is a problem in that the wiring material is limited to metals that can be plated.

On the other hand, the process of peeling off the upper layer wiring resist, etching the electrode metal for plating, and peeling off the bridge base resist is complicated, and there is a problem in that it is difficult to form aerial wiring with a high yield.

The present invention has been made in view of the above, and aims to provide a method for manufacturing a semiconductor device that can reduce the capacitance and increase the density of aerial wiring, improve yield, and simplify the manufacturing process.

(d) Means for Solving the Problems The method for manufacturing a semiconductor device of the present invention will be explained with reference to FIG. 1 corresponding to one embodiment. First step of forming the body support 6 [see 111ffl(a) to (d)] ii: Applying a cross-linked base resist 7 to the entire surface of the semiconductor substrate l, exposing and developing the cross-linked base resist 7, The bridging foundation resist on the conductor support column 6 is
2nd process of removing so that a gap 8 is created around the [1st
Refer to Figure (e)] jj Second, the cross-linked base resist 7 is baked at a temperature and for a time that allows it to be dissolved in an organic solvent, and the cross-linked base resist 7 sags to fill the gap 8 and the corners 7b are sloppily lost. Step [See FIG. 1(f)] iv: Fourth step of forming an upper layer wiring metal 9° over the entire surface of the semiconductor substrate vil [See FIG. 1 ((to)) V: Above this upper layer wiring metal 9 The fifth step is to apply a resist 10 to the substrate, expose and develop the resist 10, and pattern the resist 10.
See FIG. 1(h)] ■i: Sixth step of etching the upper layer wiring metal 9' using this patterned resist 10 as a mask [see FIG. 1(5)] vii: The patterned resist 10 10 and a seventh step (see FIG. 1(i)) of simultaneously peeling off the crosslinked base resist 7.

(E) Function In the method for manufacturing a semiconductor device of the present invention, since the upper layer wiring 9 and the lower layer wiring 4 are connected by the conductor pillar 6, in order to reduce the capacitance at the intersection of the upper layer wiring 9 and the lower layer wiring 4, Even if the bridging base resist 7 is made thicker, connection failures such as disconnections are less likely to occur.

The bridge foundation resist 7 on the conductor support 6 is connected to the conductor support 6.
The gap 8 is removed so that a gap 8 is formed around 0, and this gap 8 is filled by applying a cross-linked base resist 7 by baking. At this time, the sagging resist is used to fill the gap 8, and the surface of the resist itself Since the tension does not extend to the top surface of the conductor support column 6, the connection area between the upper layer wiring 9 and the top surface of the conductor support column 6 does not become small, and the connection strength at that part does not decrease. Resistance also does not increase. Therefore, even if the connection portion between the upper layer wiring 9 and the lower layer wiring 4 is miniaturized, connection failures will not occur.
<, it becomes possible to increase the density of wiring.

Further, since the corners 7b of the bridging base resist 7 are removed by baking, defects such as breakage of the upper layer wiring 9 at these parts are less likely to occur.

Furthermore, since the upper layer wiring 9 is formed by etching, even if the spacing between the upper layer wirings is small to increase the wiring density, the upper layer wirings are prevented from connecting to each other, which was a problem with the plating method, and the yield is improved. It is possible to improve the performance of the wiring, and it is also possible to miniaturize the wiring itself. Furthermore, the wiring material is not limited as in the case of plating.

On the other hand, the resist 10 on which the upper layer wiring is patterned and the bridging base resist 7 can be peeled off at the same time, and the deposition and etching of plating electrode metal are not required, so that the process can be simplified.

(F) Embodiment An embodiment of the present invention will be described below with reference to FIG.

FIG. 1(a) shows an insulating film 2 on a semiconductor substrate (wafer) 1.
A contact hole 3 is formed in the connecting portion 4 of the lower layer wiring 4.
It shows a state where a is exposed. Although various semiconductor elements are built into this semiconductor substrate 1, they are not shown in the drawings because they are not essential parts of the present invention.

1(a) to 1(d) are diagrams sequentially illustrating the formation of the conductive support columns 6. FIG. First, a resist 5 is formed on the semiconductor substrate 1 [see FIG. 1(c)]. This resist 5
was exposed and developed by the image reverse method (Az5
200R), the portion above the contact hole 3 has been removed, and the side surface 5a has an overhang shape.

Next, a conductor support metal 6' is deposited by means such as sputtering [see FIG. 1(C)]. This conductor support metal 6° is made of, for example, titanium (T i ), platinum (p
t) and gold (Au) are deposited sequentially from the bottom, but the materials are not limited to these and the design can be changed as appropriate. By depositing this conductor support metal 6゛,
A trapezoidal conductor support column 6 is formed over the contact hole 3 . When this resist 5 is peeled off, the conductor support metal 6' deposited on the resist 5 is also removed (lift-off), leaving only the conductor support 6 [see FIG. 1(d)].

Next, a bridging base resist 7 is formed except for the conductor pillars 6 [see FIG. 1(e)]. A large portion of the resist is removed between the bridging base resist side surface 7a and the conductor pillar 6 so that a gap 8 remains, which can sufficiently absorb the alignment error of the exposure device and which can be filled by baking in the next step. Furthermore, the semiconductor substrate 1 is baked,
The bridging base resist 7 is allowed to sag as shown in Figure 1). This is to eliminate the corner 7b, to make the connection between the conductor support 6 and the upper layer wiring 9 described later smooth, and to prevent disconnection. Even if the bridging base resist 7 sag, the sagging resist is used to fill the gap 8 and because of the surface tension of the resist itself, it will not reach onto the conductor support 6. Note that it is necessary to select a type of resist for the cross-linked base resist 7 that can be easily dissolved with an organic solvent such as acetone even after baking at a temperature that allows the surface to sag sufficiently.

FIG. 1(g) shows a state in which an upper layer wiring metal 9' is deposited on the bridging base resist 7 whose upper surface is sagging. In this embodiment, the upper layer wiring metal 9° is made of titanium (Ti
) and gold (Au) are deposited in this order, but the invention is not limited thereto. The upper layer wiring metal 9° is connected to the upper surface of the conductor support column 6.

An upper layer resist is applied onto this upper layer wiring metal 9', and this single layer resist is exposed and developed to form a pattern. Then, the upper layer wiring metal 9 is dry-etched, for example, by ion milling to remove unnecessary parts, and the upper layer wiring 9 is removed.
(See Figure 1 (h)). 10 indicates this remaining upper layer resist.

Finally, when the bridge base resist 7 and the upper layer resist 10 are simultaneously peeled off using an organic solvent, the upper layer wiring 9 is supported by the conductor pillars 6.6 and left floating in the air.

By optimizing the process, it was possible to form an aerial wiring with a wiring width of 1.5 μm, a spacing between conductor pillars 6.6 of 80 μm, and a spacing between the upper layer wiring 9 and the lower layer wiring 4 of 1.5 μm.

In this embodiment, the height of the conductor support 6 is required to be at least half the distance between the upper layer wiring 9 and the lower layer wiring 4, but in order to further miniaturize the aerial wiring, the height of the conductor support 6 is required. is made high enough to reach the lower surface of the upper layer wiring 9. As a result, the upper layer wiring does not sink into the support metal part, and there is no need to design with a margin for that part.
Even if the upper layer wiring is made finer, the area of the connection portion does not become extremely small, and it is possible to make the upper layer finer. In order to increase the height of the conductor pillars 6, it is necessary to increase the thickness of the resist 5 [see FIGS. 1(b) and 1(C)], so a technique such as a multilayer resist is applied.

(g) As described in detail of the invention, the first step is to form a conductor support on the lower wiring connection portion on the semiconductor substrate, and the step of applying a bridging base resist to the entire surface of the semiconductor substrate. A second step is to expose and develop the cross-linked base resist on the conductive support pillars so as to leave a gap around the conductive support pillars, and to bake the cross-linked base resist at a temperature and time that allows it to be dissolved in an organic solvent. a third step in which the cross-linked base resist sag to fill the gap and eliminate the corners; a fourth step in which an upper layer wiring metal is formed over the entire surface of the semiconductor substrate; a fifth step of applying a resist and patterning the resist by exposing and developing the resist; a sixth step of etching the upper layer wiring metal using the patterned resist as a mask; and a sixth step of etching the upper wiring metal using the patterned resist as a mask. and a seventh step of peeling off the bridging base resist, which has the advantage of simplifying the process, lowering the capacitance and increasing the density of the aerial wiring, and improving the yield. There is. It also has the advantage of widening the selection range of wiring materials.

[Brief explanation of the drawing]

Figure 1(a), Figure 1(b), Figure 1(C), Figure 1(
d), FIG. 1(e), FIG. 1(f), FIG. 1(g), FIG. 1(5), and FIG. 1(i) respectively relate to one embodiment of the present invention. 2(a), 2(b), 2(C), 2(d), 2(e), and 2(f) for explaining the manufacturing process of a semiconductor device. ) are diagrams each sequentially explaining the manufacturing process of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1: Semiconductor substrate, 2: Insulating film, 3: Contact hole, 6: Conductor support, 4: Lower layer wiring, 4a: Connection part, 7: Bridge foundation resist, 7b
: Corner, 8: Gap, 9: Upper layer wiring, IO2 upper layer resist. Patent Applicant ROHM Co., Ltd. Agent Patent Attorney Shigeru Nakamura Nobuo Figure (a) Figure (C) Figure (d) Figure (f) Figure (a) Figure (b) Figure (C) Figure Figure (d) Figure (e)

Claims (1)

[Claims] (1) A first step of forming conductor pillars on the lower wiring connection portions on the semiconductor substrate, applying a cross-linked base resist to the entire surface of the semiconductor substrate, exposing and developing the cross-linked base resist, and A second step is to remove the bridging base resist on the pillars so that a gap is created around the conductor pillar, and baking the bridging base resist at a temperature and time that allows it to be dissolved in an organic solvent, so that the bridging base resist sag and the above-mentioned process is performed. a third step of filling the gaps and making the corners sloppy; a fourth step of forming an upper layer wiring metal over the entire surface of the semiconductor substrate; applying a resist on the upper layer wiring metal and exposing the resist to light. - A fifth step of developing and patterning the resist, a sixth step of etching the upper layer wiring metal using this patterned resist as a mask, and simultaneously peeling off the patterned resist and the bridge base resist. A method for manufacturing a semiconductor device, comprising a seventh step.