JPH0442562A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device which makes it possible to easily for air-bridge wiring without the necessity of precisely controlling various parameters by using the first resist for exposing the upper part of column zone using the second resist for forming a mask pattern for wire of the upper layer. CONSTITUTION:The first resist 16 is coated with the thickness of approximately 2 to 5mum by spin coating. Reactive ion etching with the use of O2 plasma is applied to the first resist 16, so that that upper part of column zone 14 may be exposed with prescribed quantity. Then, a SiN film 18 is formed, as a thin film, on the surface of first resist 16 by the means of plasma making film, which employs electronic cyclotron resonance. After the formation of the SiN film 18, the second resist 19 is applied on the SiN film 18, and a groove 20 for wiring of the upper layer is formed in the region positioned in the upper part of the column zone 14 of the second resist 19. After the groove 20 in reverse tapered condition is formed in this way, the SiN film 18 existing in the groove 20 is removed by etching with the use of hydrofluoric acid, e.g. Then, wire of the upper layer 22 is installed in the groove 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an air bridge in multilayer wiring.

[Prior Art] Conventionally, a multilayer wiring method has been proposed in which wiring in an integrated circuit is multilayered to provide a degree of freedom in coupling between elements arranged in a substrate to form a high-density device. ing.

Such multilayer wiring is achieved by forming an insulating layer between the lower layer wiring and the upper layer wiring, but when such an interlayer insulation layer exists, parasitic capacitance increases at the intersection of the upper layer wiring and the lower layer wiring. Particularly in high-speed digital integrated circuits and the like, delay in signal propagation speed due to this parasitic capacitance becomes a problem.

Therefore, so-called air bridge wiring has been proposed in order to reduce this parasitic capacitance and prevent delay in signal propagation speed.

The following methods are conventionally known as methods for forming this air bridge wiring.

That is, first, a lower layer interconnect is formed on a semiconductor substrate, a resist pattern is created in which a region where the lower layer interconnect and the upper layer interconnect to be formed are exposed is exposed, and then a thin metal layer is formed over the entire surface.

Then, a resist pattern is created again on this metal layer, exposing only the region where the upper layer wiring is to be formed.

Thereafter, a desired upper layer wiring is formed by plating using the metal layer as an electrode, and the resist is removed.

Finally, by removing the resist between the semiconductor substrate and the metal layer, a space is formed between the upper layer wiring and the lower layer wiring where the resist was present.

Further, the applicant of the present application previously proposed the following air bridge forming method in a method of manufacturing a semiconductor device in Japanese Patent Application No. 1-267207.

That is, as shown in FIG. 2, after forming the lower layer wiring 12.13 on the semiconductor substrate 10, the lower layer wiring 12.13 is formed on the semiconductor substrate 10.
A pillar portion 14 is erected on top of the pillar portion 13. Then, lower layer wiring 12.
A resist release layer 16 is applied so as to cover the column parts 13 and the columnar parts 14, and a resist of a certain thickness is applied to the release layer 16 using an image reverse photolithography method or the like so that only the upper surface of the columnar part 14 is exposed. A groove 15 is formed in which the groove remains at the bottom.

Thereafter, an upper wiring metal layer 17 thinner than the depth of the groove 15 is deposited on the entire surface of the peeling layer using vacuum evaporation or the like, and the upper wiring metal layer 17 deposited on the peeling layer and the groove 15 is
By removing the other metal layers, the upper wiring metal layer 17 is supported by the pillar portion 14, and a space is formed below the upper wiring metal layer 17 with a reduced number of steps.

[Problems to be Solved by the Invention] However, in the above-mentioned conventional air bridge wiring formation method using plating, in order to form the upper layer wiring, a chemical method different from the vacuum evaporation method or sputtering method used when forming the lower layer wiring is used. There is a problem in that the process becomes complicated, as a plating method must be used, and the lower and upper resist layers must be sufficiently paved to withstand the plating process.

In addition, when forming grooves in the resist peeling layer so that only the top surface of the pillar part is exposed in a manufacturing method using vacuum evaporation, etc., the image reverse photolithography method described above is used, but the exposure amount for full-surface exposure is In addition to the need to precisely control various parameters, including the above, there was a slight problem in that the thickness of the upper layer wiring metal could not be set to the difference between the thickness of the resist peeling layer and the height of the top surface of the column.

The present invention was made in view of the above-mentioned conventional problems and the problems of the manufacturing method proposed by the applicant, and its purpose is to eliminate the need to use chemical methods such as plating, and to precisely control various parameters. It is an object of the present invention to provide a method for manufacturing a semiconductor device that allows easy formation of air bridge wiring without any problems.

[Means for Solving the Problems] In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention includes arranging a plurality of pillar portions spaced apart from each other on a lower layer wiring formed on a semiconductor substrate. a step of applying a first resist to cover the erected pillars; a step of etching the first resist to expose a predetermined amount of the upper surface of the pillars; A step of forming a thin film on the surface of the resist, a step of applying a second resist on the formed thin film, and a step of forming a groove for an upper layer wiring in a region of the second resist located above the pillar portion. and etching the thin film in the groove, depositing an upper wiring metal thinner than the second resist in the groove, and removing the first and second resists. It is characterized by

[Function] As described above, the method for manufacturing a semiconductor device according to the present invention
and a second resist, the first resist is used to expose the upper part of the pillar part, and the second resist is used to form five mask patterns for upper layer wiring. is formed on the thin film on the first resist layer, and there is no need to leave any resist at the bottom of the groove, so it can be easily formed without precise control of exposure and development conditions. .

[Example] Hereinafter, a preferred example of the method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a partial sectional view for explaining each step of the air bridge wiring forming method of this embodiment.

First, as shown in FIG. 1(a), among the lower layer wirings 12 and 13 formed on the semiconductor substrate 10 such as GaAs,
In order to straddle the lower layer wiring 12 and connect the lower layer wiring 13 to each other using the upper layer wiring, a plurality of metal pillars 14 are provided on the lower layer wiring 13.
(height: 1 to 2 μm). In order to erect the pillar portion 14 in this way, a resist is applied on the lower layer wiring 12.13, the resist is removed in the area where the pillar portion is to be formed, a metal layer is applied, and the resist is removed. A lift-off method can be used.

After the pillar section 14 is erected in this way, a first
A resist 16 of about 2 to 5 μm thick is formed using a spin code.

Next, as shown in FIG. 1(C), the coated first resist 16 is etched onto the pillar portions by reactive ion etching (hereinafter referred to as 02RIE) using 02 plasma.
Etch so that a predetermined amount of the upper part of 4 is exposed. In reactive ion etching, the etching rate can be controlled relatively easily, and control parameters can be set more easily than in the case of using image reverse photolithography.

After exposing the upper part of the pillar part 14 using 02RIE, the solvent in the first resist 16 is removed by baking, and SiN is deposited as a thin film on the surface of the first resist 16 as shown in FIG. 1(d). The film 18 is formed, for example, by a plasma deposition method using electron cyclotron resonance (ECR), which can be deposited at a low temperature. The material of this film is Si.
Instead of an insulator such as an N film, a metal such as Ni may be used.

After forming the SiN film 18 in this way, this SiN film 1
A resist 19 is applied on the film 8 and 2, and then the resist 19 shown in FIG.
As shown in e), the pillar portion 1 of this second resist 19
A groove 20 for an upper layer wiring is formed in a region located above 4.

Hereinafter, as a method for forming the groove 20, an image reverse photolithography method using a special positive type resist will be described as an example.

First, a positive photoresist as the second resist 19 is spin-coated onto the SiN film 8 using a pinner to a predetermined thickness, for example, about 2 to 5 μm. This positive photoresist is a resist to which a photosensitive agent is added which reduces the rate of dissolution in a developer under a certain amount of exposure and reverse baking conditions.

After applying this positive resist, pre-baking is performed,
Initial exposure is performed with weak light from a light source through a photomask. At this time, areas other than the groove 20 to be formed are exposed.

Then, reverse baking is performed to stabilize the initially exposed portion of the positive photoresist.

Next, flood exposure is performed over the entire surface of the positive photoresist to increase the rate of dissolution of the unexposed portions of the resist in the alkaline developer during the initial exposure. This is because the initially exposed portions are difficult to dissolve in an alkaline developer, while the unexposed portions of the positive resist are easily dissolved.

Grooves 20 having a depth reaching the SiN film 18 are then formed by development with an alkaline developer.

At this time, as mentioned above, the initially exposed area has a lower dissolution rate in the developer than the unexposed area, so
The groove 20 formed is the second groove as shown in FIG. 1(e).
The shape becomes an inverted tapered shape in which the width gradually increases from the surface of the resist 19 to the surface of the SiN film 18.

After the reversely tapered groove 20 is formed in this way, S
The iN film 18 is removed by etching using, for example, hydrofluoric acid.

Then, as shown in FIG. 1(g), upper layer wiring metal is deposited over the entire surface by, for example, a vacuum evaporation method, thereby forming grooves.
The upper layer wiring 22 is deposited within 0.

At this time, the thickness of the upper layer wiring 22 deposited in the groove 20 is set to be thinner than the thickness of the second resist 19.

Finally, as shown in FIG. 1(h), the first resist 16 and the second resist 19 are removed using, for example, acetone.

Then, the upper layer wiring 22 is supported by the column part 14, and an air bridge wiring in which a space exists between the upper layer wiring 22 and the lower layer wiring 12 is formed.

In this way, in this example, the upper surface of the pillar part is exposed using reactive ion etching which is easy to control, and the second
By forming grooves for upper layer wiring in the resist, it can be reproduced without using plating and without requiring precise control of various parameters of the image reverse photolithography method used when forming grooves for upper layer wiring. Improves sex.

Further, in this embodiment, the thickness of the upper layer wiring 22 is the second
Since the thickness of the second resist 19 is set to be less than the thickness of the second resist 19, the thickness of the upper layer wiring 22 can also be increased by increasing the thickness of the second resist 19, and it is possible to obtain an air bridge wiring with excellent strength. Become.

[Effects of the Invention] As explained above, according to the method for manufacturing a semiconductor device according to the present invention, an air bridge wiring having excellent strength can be easily formed.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG. 2 is an explanatory diagram of a conventional method for manufacturing a semiconductor device. 10... Semiconductor substrate 12.13... Lower wiring 14... Pillar portion 16... First resist 18... SiN film 19... Second resist 20... Groove 22...・ Upper layer wiring (e) (b) (c) Old (d)

Claims (1)

[Claims] A step of erecting a plurality of pillars at a distance from each other on a lower wiring formed on a semiconductor substrate, a step of applying a first resist to cover the erected pillars, and a step of applying a first resist to cover the erected pillars; a step of etching this first resist to expose a predetermined amount; a step of forming a thin film on the etched surface of the first resist; a step of applying a second resist on the formed thin film; forming a groove for an upper layer wiring in a region of a second resist located above the pillar part;
etching the thin film in the groove; depositing an upper wiring metal thinner than the second resist in the groove; and removing the first and second resists. A method of manufacturing a semiconductor device, comprising forming a space between an upper layer wiring and a lower layer wiring.