JPH0412044U - - Google Patents

Info

Publication number
JPH0412044U
JPH0412044U JP5321690U JP5321690U JPH0412044U JP H0412044 U JPH0412044 U JP H0412044U JP 5321690 U JP5321690 U JP 5321690U JP 5321690 U JP5321690 U JP 5321690U JP H0412044 U JPH0412044 U JP H0412044U
Authority
JP
Japan
Prior art keywords
multiprocessor system
cpu
boot rom
cpus
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5321690U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP5321690U priority Critical patent/JPH0412044U/ja
Publication of JPH0412044U publication Critical patent/JPH0412044U/ja
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の原理的な構成を示すブロツク
図、第2図は本考案のマルチプロセツサシステム
をワークステーシヨンに適用した一実施例のブロ
ツク図、第3図は動的なコンフイグレーシヨンの
変更を説明するための流れ図、第4図は従来のマ
ルチプロセツサシステムの原理的な構成例を示す
ブロツク図である。 1……ローカルバス、2a,2b……CPU、
3……共有メモリ、4a,4b……ローカルメモ
リ、5a,5b……ブートROM、6a,6b…
…ネツトワークインタフエース、7a,7b……
ローカル電源スイツチ、8……デイスプレイ、9
……バスインタフエース、10……標準バス、1
1……デイスク装置、12……ワークステーシヨ
ン本体、13……主電源スイツチ、a,b……C
PUボード。
Figure 1 is a block diagram showing the basic configuration of the present invention, Figure 2 is a block diagram of an embodiment in which the multiprocessor system of the present invention is applied to a workstation, and Figure 3 is a dynamic configuration diagram. FIG. 4 is a block diagram showing an example of the basic configuration of a conventional multiprocessor system. 1...Local bus, 2a, 2b...CPU,
3...Shared memory, 4a, 4b...Local memory, 5a, 5b...Boot ROM, 6a, 6b...
...Network interface, 7a, 7b...
Local power switch, 8...Display, 9
... Bus interface, 10 ... Standard bus, 1
1...Disk device, 12...Workstation body, 13...Main power switch, a, b...C
PU board.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 共有メモリに対して共通にアクセスする複数の
CPUを備えたマルチプロセツサシステムにおい
て、各CPU毎に少なくともローカルメモリ及び
ブートROMを設けたことを特徴とするマルチプ
ロセツサシステム。
A multiprocessor system comprising a plurality of CPUs that commonly access a shared memory, characterized in that each CPU is provided with at least a local memory and a boot ROM.
JP5321690U 1990-05-21 1990-05-21 Pending JPH0412044U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5321690U JPH0412044U (en) 1990-05-21 1990-05-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5321690U JPH0412044U (en) 1990-05-21 1990-05-21

Publications (1)

Publication Number Publication Date
JPH0412044U true JPH0412044U (en) 1992-01-31

Family

ID=31574214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5321690U Pending JPH0412044U (en) 1990-05-21 1990-05-21

Country Status (1)

Country Link
JP (1) JPH0412044U (en)

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