JPH04119721A - Asynchronous signal selection circuit - Google Patents

Abstract

PURPOSE:To prevent a pulse waveform with a narrower width than that of an asynchronous signal at signal switching by selecting the timing of an output selection signal fed to a multiplexer to be a timing when both asynchronous signals before/after switching are logically at a high level. CONSTITUTION:When asynchronous signals 1, 2 are inputted to the selective circuit and the level of a selective signal 3 is changed from a high level to a low level, a falling detection circuit 5 outputs a logic low level synchronously with the rise of the asynchronous signal 2. Since the asynchronous signal 1 is used as the enable signal E of a latch 7, the output signal of the latch 7 is inputted to an R-S latch 9 while the asynchronous signal 1 is at a high logic level, the output of the R-S latch 9 goes to a high logic level and the output of a multiplexer 8 is an input signal 2. When the selective signal 3 is changed from a low logic level to a high level, a rising detection circuit 4 outputs a low logic level synchronously with the rise of the asynchronous input signal and the output of the multiplexer 8 is an input signal 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an asynchronous signal selection circuit that selects and outputs one asynchronous signal from a plurality of asynchronous signals.

Background of the Invention In recent years, digital circuits often select and handle various different asynchronous signals, and the output waveform is an important issue.Hereinafter, a conventional asynchronous signal selection circuit will be explained with reference to the drawings. Fig. 3 is a circuit diagram showing the configuration of a conventional asynchronous signal selection circuit, and Fig. 4 is a timing chart showing its operation.In Fig. 3, the conventional asynchronous signal selection circuit and asynchronous signal 2
and an output selection signal 3, and its output becomes the selected asynchronous signal.

Problems to be Solved by the Invention In such a conventional asynchronous signal selection circuit, as shown in the timing chart of FIG. When the asynchronous signals H and H have different polarities, the multiplexer generates a pulse with a narrower width than the original asynchronous signal, as shown in the figure, which can cause malfunctions in equipment that receives this output. . SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide an asynchronous signal selection circuit that does not output a waveform narrower than the original asynchronous signal when switching.

Means for Solving the Problems In order to achieve the above object, the present invention inputs a plurality of asynchronous signals and a first output selection signal, and selects one of the asynchronous signals with the first output selection signal. an output selection signal forming circuit that forms a second output selection signal; and an output selection signal forming circuit that inputs the plurality of asynchronous signals and the second output selection signal and selects and outputs the asynchronous signal. a multiplexer that selects and outputs one of the output selection signals using the second output selection signal, and the output selection signal forming circuit selects and outputs the switching timing of the second output selection signal according to the currently selected asynchronous signal and the next one. The asynchronous signal selection circuit is configured such that the asynchronous signals to be selected are both at high level. , the currently selected asynchronous signal is at a high level and the next selected asynchronous signal is also at a high level. The signal switches to high level continuously, and a waveform narrower than the width of the original asynchronous signal is not output.

Embodiment Hereinafter, an asynchronous signal selection circuit according to an embodiment of the present invention will be explained with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of an asynchronous signal selection circuit according to an embodiment of the present invention when two asynchronous signals are selected, and FIG. 2 is a timing chart showing its operation. In this embodiment, there are two input asynchronous signals and one output selection signal, and the high level and low level thereof correspond to asynchronous signal 1 and asynchronous signal 2, respectively, and switching is performed. The timing detection circuit is realized by a rising edge detection circuit and a falling edge detection circuit of the output selection signal. In FIG. 1, 1 and 2 are asynchronous input signals, 3 is an output selection signal that selects which of input signal 1 and input signal 2 to output, 4 is a rising detection circuit, 5 is a falling detection circuit, 6 and 7 are latches, 8 is a multiplexer, 9 is an R-S latch for outputting a selection signal for multiplexer 8, 10 is a signal after switching, 1
1 is an inverter. Here, it is assumed that when the output selection signal 3 is at logic level high, input signal 1 is selected, and when output selection signal 3 is at logic level low, input signal 2 is selected.

In the asynchronous signal selection circuit in which the above components are connected as shown in FIG. 1, when asynchronous signals 1 and 2 as shown in FIG. 2 are input, selection signal 3 changes from logic level high to logic level. When the signal changes to low, the falling detection circuit 5 outputs a logic level low in synchronization with the rising edge of the asynchronous input signal 2. latch 7
Since the asynchronous input signal 1 is used as the enable signal E of the latch 7, the output signal of the latch 7 is input to the R-S latch 9 while the asynchronous input signal 1 is at logic level high, and the output signal of the latch 7 is The output becomes logic level high, and the output of multiplexer 8 becomes input signal 2.

Furthermore, when the selection signal 3 changes from logic level low to logic level 11a, the rise detection circuit 4 outputs
Logic level low is output in synchronization with the rise of asynchronous input signal 1, and when the output of latch 6 changes to logic level low, the output of RS latch 9 becomes logic level low, and the output of multiplexer 8 becomes input signal 1. .

Note that when the outputs of latches 5 and 6 both change to logic level low, asynchronous input signals 1 and 2 are both logic level high, so when switching, the output of multiplexer 8 remains at logic level high and does not change. There are no narrow signals.

As described above, according to the asynchronous signal selection circuit of one embodiment of the present invention, a rising edge detection circuit, a falling edge detection circuit, and a latch circuit are provided for the output selection signal, and the timing of the output selection signal supplied to the multiplexer is adjusted before switching. By setting the timing at which both the asynchronous signal and the asynchronous signal after switching are at logic level high, it is possible to obtain an asynchronous signal selection circuit that does not output a pulse waveform narrower in width than the original asynchronous signal during signal switching.

Note that similar effects can be obtained using the same concept in an asynchronous signal selection circuit in which there are two or more asynchronous signals.

Effects of the Invention As is clear from the above embodiments, the present invention inputs a plurality of asynchronous signals and a first output selection signal, and selects one of the asynchronous signals with the first output selection signal. an output selection signal forming circuit that forms a second output selection signal; and an output selection signal forming circuit that inputs the plurality of asynchronous signals and the second output selection signal and outputs one of the asynchronous signals. A multiplexer is provided that selects and outputs one with the second output selection signal, and the output selection signal forming circuit selects the switching timing of the second output selection signal between the currently selected asynchronous signal and the next one. By forming the asynchronous signal selection circuit so that the timing is such that both asynchronous signals are at high level,
It is possible to realize an asynchronous signal selection circuit that does not erroneously output a pulse waveform with a narrower radius than the original asynchronous signal at the time of signal switching.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an asynchronous signal selection circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of an asynchronous signal selection circuit according to an embodiment of the present invention, and FIG. FIG. 4 is a circuit diagram showing the configuration of the asynchronous signal selection circuit, and a timing chart showing the operation of the conventional asynchronous signal selection circuit. 1: Asynchronous signal input, 2: Asynchronous signal input, 3: Output selection signal (first output selection signal), 4: Rise Detection circuit (timing detection circuit), 5...Falling detection circuit (timing detection circuit), 6...Latch circuit, 7...Latch circuit, 8... ...Multiplexer, 10th...Output signal, 12...Output selection signal forming circuit, 13th...Second output selection signal. Name of agent: Patent attorney Haruaki Koyaku. 2 people 4 Standing detection circuits ('9 imminc° each) Circuit 13 Atsushi 2 Reef J Company January Words Figure Figure Figure Figure

Claims (2)

[Claims] (1) In an asynchronous signal selection circuit that receives a plurality of asynchronous signals and a first output selection signal, and selects and outputs one of the asynchronous signals using the first output selection signal,
an output selection signal forming circuit that forms a second output selection signal; an output selection signal forming circuit that inputs the plurality of asynchronous signals and the second output selection signal, and outputs one of the asynchronous signals as the second output selection signal; a multiplexer that selects and outputs the output selection signal, and the output selection signal forming circuit sets the switching timing of the second output selection signal to a timing when both the currently selected asynchronous signal and the next selected asynchronous signal are at a high level. An asynchronous signal selection circuit formed as follows. (2) A timing detection circuit that latches the switching timing of the first output selection signal at the rising edge of the currently selected asynchronous signal, and a latch that latches the output of the timing detection circuit at the rising edge of the next selected asynchronous signal. 2. The asynchronous signal selection circuit according to claim 1, wherein the asynchronous signal selection circuit comprises: an output signal formation circuit, wherein the second output selection signal is formed at the timing of the output of the latch circuit.