JPH04118692A - Artificial gradation generating circuit - Google Patents

Abstract

PURPOSE:To drive a high-resolution LCD at a high frame frequency without using any expensive circuit component which operates fast nor increasing the current consumption by latching input data for each of upper and lower LCD image planes and controlling their ON/OFF states. CONSTITUTION:Input data D0 - D3 are latched in an input latch 1 with a clock CK and then a 1/2 frequency dividing circuit 5 divides the frequency of the clock CK to latch upper and lower data in upper and lower image plane latches 3 and 4. An X/Y counter 6 which receives H and V signals SYNC as trigger inputs counts pixel addresses on the LCD image planes at a specific period and gradation decoders 7 and 8 output turn-on ratio signals corresponding to respective gradations. Selectors 9 and 10 select data corresponding to the data in the latches 3 and 4 from the turn-on ratio data generated by the decoders 7 and 8 and send them to shift registers, and parallel data conversion into the number of data input bits of an LCD panel is performed to display artificial gradations corresponding to the input data on the LCD.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to flat display devices having a vertically divided structure such as liquid crystal display devices (hereinafter referred to as LCDs) used in personal computers, word processors, etc. The present invention relates to a circuit that performs pseudo gradation display by controlling the ratio of lighting and extinction for each frame.

[Prior Art] A conventional pseudo gradation generation circuit operates horizontal and vertical counters and a decoder circuit that generates a lighting ratio for each piece of data corresponding to a pixel that is input alternately to the upper screen and sub screen. , the pseudo gradation signal was selected and output.

[Problem to be solved by the invention 1 However, the above-mentioned conventional technology has the following drawbacks.

That is, in the pseudo gradation display method, it is necessary to suppress the flicker of the LCD, so it is desirable to display the LCD at a higher frame frequency than that of a CRT, and the circuit needs to operate at high speed. In addition, with the increase in display resolution, it has become essential to operate the horizontal and vertical counters, decoder circuits, and grayscale signal selection circuits mentioned above at higher speeds in a timing period corresponding to one pixel of data.

For this reason, it has disadvantages of increased circuit cost and large power consumption.

The present invention solves these conventional problems and provides a means for driving a high-resolution LCD at a high frame frequency without using expensive high-speed circuit components or increasing current consumption. Our goal is to provide the following.

[Means for Solving the Problems] The pseudo gradation generation circuit of the present invention is characterized by having means for latching input data for each of the upper and lower LCD screens and controlling lighting and extinguishing of each of the upper and lower LCD screens.

[Function] According to the configuration of the present invention, the clock for latching input data is divided, and the data of each of the upper and lower screens is latched. The horizontal and vertical counters that count the display position and the decoder that controls turning on and off operate on the above frequency-divided clock, and the switching frequency of the data selection circuit is also %, making these circuits inexpensive. It can be configured with a circuit that is more flexible and consumes less current. Also,
By operating this circuit at high speed, it is possible to operate a higher resolution LCD at high speed.

[Example 1] Hereinafter, the present invention will be explained in detail according to Examples. FIG. 1 shows an embodiment of the present invention, where 1 is an input latch, 3 and 4 are latches for the upper and lower screens, 5 is an input clock division circuit, and 6 is an X that counts the screen position on the LCD. /Y counter, 7.8 is a gradation decoder that generates a gradation signal of the on/off ratio corresponding to each gradation level, 9.10 is a selector that selects a gradation signal corresponding to input data, 11.12 is a In the shift register, 13 is an LCD.

In this embodiment, a case where pseudo 16-gradation display is performed on the LCD will be described as an example.

The 4-bit input data D0 to D3 corresponding to 16 gradations are latched into the input caratchier by the clock CK. Normally, the display data of an LCD divided into two screens is generated by the display controller alternately up and down for each dot. In order to be input to the circuit, the frequency divider circuit 5 divides the clock CK to generate two-phase clocks CK1 and CK2, and the upper and lower data are latched in the upper side latch 3 and lower screen latch 4, respectively.

On the other hand, X with H5YNC and VSYNC as triggers and forces
/Y counter 6 counts the pixel addresses on the LCD screen in predetermined synchronization, and based on this address, gradation decoder 7.8 outputs a lighting ratio signal corresponding to each gradation. 1
In the case of 6-gradation display, the non-lighting level is O1 and the lighting level is 1
Then, if you want to generate lighting and non-lighting signals in units of 1/15, and display the third gradation by counting non-lighting as 0, pixels will light up at a rate of 3/15 as an average value. The gradation decoder outputs the signal. Further, the pseudo gradation display method has visual flicker whose degree is determined by the display frame frequency and the response speed of the liquid crystal. In order to suppress this flicker, the gradation decoder performs control based on the value of the X/Y counter so that lit and non-lit pixels are not concentrated in the same frame and in different frames.

Selector 9.10 selects the 1 generated by tone decoder 7.8.
From the lighting ratio data for 6 gradations, upper and lower screen latch 3
．． The lighting ratio data corresponding to data No. 4 is selected and sent to the shift register.

The shift register performs parallel data conversion to the number of data input bits of the LCD panel and outputs the data to the LCD.

Therefore, a pseudo gradation display corresponding to the input data DO to D3 is realized on the LCD.

Here, the input clock frequency and circuit operation will be described. As mentioned above, the pseudo gradation method inherently has visual flicker, and in order to reduce this, it is necessary to drive the LCD at a high frame frequency with a high-speed clock input. In the pseudo gradation generating circuit of the present invention shown in FIG. 1, even if a high frequency clock is input, the frequency is immediately divided by % and the circuit operates at twice the frequency. Particularly in pseudo gradation generation circuits, the path in which data is converted from the X/Y counter to the gradation decoder and selector to the shift register is performed within one clock cycle, so doubling the period is very unlikely. It is effective for Even if clocks of the same frequency are input, the circuit operation only needs to be completed within twice the period, so inexpensive circuit components can be used. Furthermore, when integrating into an integrated circuit, the chip area can be reduced because the elements constituting each circuit do not require high-speed operation. On the other hand, when circuits with the same operating frequency are used, it is possible to handle a clock input with twice the frequency, so it is possible to display gray scales on an LCD with twice the number of display pixels.

Furthermore, in this embodiment, the case of displaying 16 gradations with 4-bit input has been explained, but with 6-bit input, 64 gradations or 8 gradations.
When the number of gradations increases as in the case of bit input 256 gradations,
Since the scale of the X/Y counter, gradation decoder, and selector circuit increases, the effects of the present invention become even greater.

In this way, even if input data is clocked to the station frequency and latched to generate grayscale signals, the original structure of an LCD is divided into upper and lower sections, and data is input independently to the upper and lower screens. Therefore, the gradation-processed signal is directly transmitted to the LC
It is sufficient to transfer the signal to D, and there is no need for any processing to restore the original frequency. The present invention has been made with attention to such points.

On the other hand, FIG. 2 is a block diagram of a conventional pseudo gradation generation circuit.

The basic circuit operation is the same as that of the circuit of the present invention, but the input data is latched by the clock without being used, and the input data is latched by the clock, and is connected to the X/Y counter 151 gradation decoder 16, selector 17 . operates at the original clock frequency. Distribution to the upper screen and upper screen of the LCD was performed in a circuit that converts serial data into parallel data. In this conventional circuit, an X/Y counter 15, a gradation decoder 1
6 and the selector 17 are the upper limit of the clock input frequency, which interferes with the high frame frequency operation of the LCD to prevent visual flickering, making it impossible to obtain good gradation display. Ta. Furthermore, in conventional circuits, most circuit blocks operate with a clock at the original frequency, resulting in large current consumption. As mentioned above, the gradation is 64.256, which is more noticeable as the number of levels increases, and has been a major hindrance to future high-resolution, high-gradation display of LCDs.

[Effects of the Invention] As described above, according to the present invention, the data for each of the upper and lower screens, which are input alternately, is latched separately using the squarely divided clock, and the pseudo gradation generation circuit is generated using the squarely divided clock. The cost of the pseudo gradation generation circuit can be reduced by displaying it on an LCD with a structure divided into upper and lower halves.
Also, the quality of pseudo gradation display can be improved by high frame frequency operation of a high resolution LCD.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pseudo gradation generation circuit according to the present invention. FIG. 2 is a block diagram of a conventional pseudo gradation generation circuit. ...input latch ····latch ・・・Top screen latch ・・・Top screen latch ...Station frequency divider circuit ...X/Y counter 8... Gradation decoder 10...16→1 selector 12...Shift register ...LCD ...Input latch ...X/Y counter ・・・・・・gradation dueda ...X/Y count ・・・・・・Shift register ...LCD 1・ 2・・・ ３　・・ ４　・・ 5　・・ 6・ 7. 9. 1 l, 13・ l　4　・ l　5　・ 16・ 17・ l　8　・ l　9　・

Claims (1)

[Claims] An input latch that inputs multiple bits of data, a horizontal and vertical counter that inputs horizontal and vertical synchronization signals and counts the display device, and a signal that controls lighting or extinguishing of each pixel according to the values of the horizontal and vertical counters. and a pseudo gradation generation circuit that selects the output of the decoder with a lighting ratio according to the value of the input latch to drive a flat display device divided into upper and lower parts. A pseudo gradation generation circuit characterized by having means for controlling lighting and extinguishing by latching an input.