JPH04116950A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To check whether chips after final wafer processing are satisfactory or not under the condition that the chips are lined up by leaving the part of the chip to be connected with each other when forming chip dividing grooves on the wafer after marking. CONSTITUTION:A dividing groove 41 is formed at the periphery of each chip in a GaAs wafer 21, and the chip is connected with the adjacent chips by connecting parts 42. Thus, the chips are allowed to be lined up even after the wafer 21 is divided by the connecting parts 42 of the dividing grooves 41 formed on the wafer 21, and a fine defect mark given to the chip at the previous process as a result of wafer test is identified under the condition that the chips are lined up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for dividing a semiconductor wafer that has been processed into individual chips into individual chips.

[Conventional technology]

In conventional semiconductor device manufacturing methods, it is important to check whether a plurality of semiconductor chips (hereinafter simply referred to as chips) on a wafer (hereinafter simply referred to as wafer) that has undergone a predetermined wafer process have desired electrical characteristics. It includes a process called a normal wafer test process to measure the quality of the wafer and determine its acceptability.

In this wafer testing process, technology for measuring electrical characteristics and determining pass/fail is of course important, but the question is how to give such pass/fail marks to each of these chips containing semiconductor devices. This is also an important technique. Hitherto, marking methods based on ink deposition have been most commonly used as known techniques.

This marking method using ink adhesion is used for testing wafers that do not require a special wafer test after the series of wafer test steps of measuring electrical characteristics and attaching marks to defective chips, that is, wafers that have undergone the wafer testing process. .

However, due to constraints in the wafer process, models that require a wafer test to be performed even after the test process, ie, models that require a wafer test during the wafer process, have been put into practical use in recent years.

As an example, FET (Field-Effect Tr) formed on a wafer made of GaAs is an example.
ansistor: field effect transistor),
In particular, one type of transistor called a high-output transistor is called a via hole type.

A cross-sectional view showing the concept of this via-hole type GaAsFET is shown in FIG.

In the figure, 21 is a GaAs wafer, 22 is a source electrode, 23 is a drain electrode, 24 is a gate electrode, 25.26
27 is a gold plating part, and 27 is a source gold plating part.

Next, the manufacturing method will be explained.

In this FET, a source electrode 22 and a drain electrode 23 are formed on a GaAs wafer 21, and a gate electrode 24 is formed in an intermediate region (channel region) between the two. The GaAs wafer 21 makes ohmic contact with the source electrode 22 and the drain electrode 23, and the GaAs wafer 21 and the gate electrode 24 make Schottky contact, forming a structure commonly called a MESFET.

In order to stably flow a large amount of current and to enhance the heat dissipation effect, the gold-plated portions 25 and 26 are used as electrodes for leading the source electrode 22 and drain electrode 23 to the outside.
Similarly, a gold-plated portion (not shown) is formed on the gate electrode 24 as an electrode for leading to the outside.

In this figure, only the basic unit is shown, but in reality, a plurality of source portions, drain portions, and gate portions are usually formed on a wafer.

Further, a wafer 21 is provided in a portion corresponding to the source electrode 22.
A hole, that is, a via hole, penetrating from the back surface to the source electrode 22 on the front surface is formed, and the hole is completely filled with gold plating.

The thickness (1) of the GaAs wafer 21 is after the final processing,
That is, in the state shown in this figure, the thickness is about 30 μm, whereas the gold plated portions 25 and 26 have a thickness of about 5 μm, and the source electrode 2
2. Both the drain electrode 23 and the gate electrode 24 have a thickness of 1 μm or less.

Now, in this via-hole type GaAsFET,
Control of the thickness (1) of the GaAs wafer 2I is considered to be very important. This is because when forming the via hole corresponding to the source electrode 22 by etching from the back surface, Ga
This is because if the thickness of the As wafer 21 is not constant, the shape of the via hole to be formed will also not be constant. For example, if the via hole is too small, a sufficient current cannot be extracted from the source electrode 22, and the heat dissipation effect also deteriorates. On the other hand, if the via hole is too large, in extreme cases, the diameter of the via hole on the front side of the wafer protrudes more than the width of the source electrode 22, and the wafer (at least such a via hole (including chips) will be defective.

Due to the above constraints, the conventional method of measuring the electrical characteristics of the chip during the wafer test process during the wafer process and marking the quality using ink deposition cannot be applied to this via-hole type semiconductor element. I can't.

This is because it is practically difficult to keep the size, thickness, and shape of the deposited ink uniform, and this uneven deposition of ink causes problems in controlling the wafer thickness.

In addition to impeding uniformity, when the GaAs wafer 21 is thinned, the ink attached to it peels off, causing the inconvenience that chips that cannot be determined to be defective are mixed in with non-defective chips. be.

Therefore, as an alternative to marking by ink adhesion, a method is used in which fine scratches are formed as defect marks on the chip surface, such as the gold-plated portions 25 and 26, for example.

An outline of this method will be explained below.

In this case, a marker or other device for depositing ink onto a wafer in a conventional marking method using ink deposition is used as is, with only the ink and the ink reservoir removed.

First, when it is necessary to measure the electrical characteristics of chips on a wafer and mark them as defective, touch the tip of the marker needle to the desired area on the wafer, such as the gold-plated part on the surface, and Add.

The size of the scratches generated at this time and the desired area on the wafer where the scratches are generated can be controlled using this marker.

Furthermore, in the case of via-hole type semiconductor devices, the final wafer thickness is extremely thin, approximately 30 μm, so when dividing into individual chips, it is necessary to physically form dividing grooves using a diamond scriber, etc. It is difficult to apply general methods (at least there is a risk of significantly lowering the yield when dividing into individual chips).

For this reason, a method of forming dividing grooves from the front surface to the back surface of the wafer by etching or the like is used. However, since the wafer is thin at about 30 μm, the wafer is usually pasted onto an auxiliary substrate such as a glass plate using wax, etc., and then cut into individual chips by forming grooves and melting the wax. ing.

This chip dividing method will be explained using FIG.

In the figure, the same reference numerals as in FIG. 2 indicate the same parts, and 31
is a glass disk, 32 is wax, 41 is a dividing groove, 43
is a groove.

In the same figure (a), a GaAs wafer 21 is covered with transparent wax 3.
2 to the transparent glass disk 31, and the dividing groove 4
FIG. 1 is a conceptual diagram showing a state in which 1 is formed.

Here, the GaAs wafer 21 is either the surface or the glass disk 31.
This figure is a plan view seen through this transparent glass disk 31.

In addition, (b) to (d) of the same figure are x-x' in (a) of the same figure.
FIG. 7 is a cross-sectional view showing a conventional dividing groove forming process for a cross section of a portion.

The figure (b) shows that after measuring the electrical characteristics of chips formed on a GaAs wafer 21 and adding fine marks to defective chips (not shown), the GaAs wafer 21 is placed on a glass disk 31. , shows a state in which the glass disc is attached using wax 32 so that the surface faces the glass disc.

In this figure, grooves 43 are formed on the surface of the wafer 21 at portions corresponding to positions where dividing grooves 41 will be formed later. This groove 43 has a shape that completely surrounds the outer periphery of each chip, and has a depth of about 10 μm and a width of about 100 μm.

Furthermore, in FIG. 2(e), after aligning the GaAs wafer 21 to a desired thickness, for example 30 μm, and forming a via hole reaching the source electrode 22 from the back surface, the inside of the via hole is filled with a metal such as gold, and the source plated portion 27 is formed. This shows the state in which the step of forming has been completed.

In this case, polishing is used to make the thickness of the wafer 21 uniform.

Photolithography, etching, etc. may be used to form the via hole, and well-known techniques such as vapor deposition, plating, etc. may be used to fill the via hole with metal.

Further, FIG. 2D shows a state in which the wafer 21 is divided into individual chips after forming chip dividing grooves 41 from the back surface thereof.

In order to form this dividing groove 41, a portion of the back surface of the wafer corresponding to the groove 43 formed on the front surface of the wafer 21 is selectively etched to form a groove reaching from the back surface of the wafer 21 to the front surface. For this formation, well-known techniques such as photolithography and etching are used.

[Problem to be solved by the invention]

As mentioned above, conventionally, in the wafer test process, for wafers for which marking methods using ink adhesion cannot be applied, a method of making minute scratches on the plating area on the chip has been applied, but marks caused by these scratches are inevitable. It needs to be relatively small, so after dividing it into individual chips,
When selecting pass/fail using this mark as a landmark, there was a problem in that it could not be determined unless the mark was enlarged using a microscope.

In addition, when performing the desired chipping process on a wafer as thin as about 30 μm, it is necessary to attach the auxiliary substrate such as the glass disk 31 with wax or the like, and perform the chip separation groove in the chipboard process. 41, melting the wax and performing the desired drying process will separate the wafer into individual chips. Therefore, when inspecting and sorting such scattered chips, there is a problem in that the chips must be rearranged before the inspection and sorting.

The present invention was made in order to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing semiconductor devices in which a defective mark given by a sea urchin fly process can be easily identified at the end of the final wafer process. do.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention is a marking method in which the electrical characteristics of chips formed on a semiconductor wafer are measured to determine whether the chips are good or bad, and fine marks are added to defective chips based on the results of this determination. When carrying out a wafer process including a step of forming grooves from the front surface to the back surface for separating the semiconductor wafer into individual chips, the grooves are shaped so that a desired portion of the grooves remains. This is how it was done.

[Effect]

In this invention, a part of the wafer dividing groove for dividing the semiconductor wafer into individual chips is left, and even after the wafer is divided, the chips can be divided by the connecting part of the dividing groove formed on the wafer. are aligned,
It is possible to identify minute defective marks as a result of wafer tests that were applied to the chips in the previous process when the chips are aligned.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

1(a) to 1(e) are diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and in the figures, the same reference numerals as in FIGS. 2 and 3 indicate the same parts. show,
Reference numeral 42 denotes a connecting portion that connects the chips on the wafer 21 to each other.

In the same figure (a), GaA is deposited on an auxiliary substrate 31 such as a glass disk.
FIG. 3 is a plan view showing a conceptual diagram of a state in which an S wafer 21 is attached using wax 32 and a desired process (described later) is completed, as seen through a transparent glass disk 31.

In the figure, a dividing groove 41 is formed on the outer periphery of each chip in the wafer 21, but adjacent chips are connected to each other via a connecting portion 42.

In addition, FIG. 1(b) to (d) are Y-Y' in FIG. 1(a).
FIG. 2 is a cross-sectional view showing an example of the present invention in a cross-sectional section. Note that the detailed sectional view along line xx' in FIG. 3(a) is exactly the same as the detailed section along line xx' in FIGS. do.

FIG. 1(b) shows that after measuring the electrical characteristics of the chips formed on the GaAs wafer 21 and giving minute marks to defective chips (not shown), the GaAs wafer 21 is placed on a glass disk 31. A state in which the wax 32 is attached so that its surface faces the glass disk 21 is shown. At this time, the wafer has grooves 4 corresponding to the grooves that separate the chips into individual chips.
3 are formed at desired positions on the wafer surface. The groove 43 formed on this surface is formed on the outer periphery of the chip, and as shown in FIG. groove 4
3 was not formed at all. Note that the depth of this groove 43 is approximately 10 μm and the width thereof is approximately 100 μm.

In the same figure (C), the wafer 21 is heated to a desired thickness, for example, 30 μm.
m, a step of forming a hole (via hole) from the back surface of the wafer 21 to the source electrode 22 at a position corresponding to the source electrode 22, and then filling the inside of this via hole with a metal such as gold. A state in which the step of forming the plating portion 27 has been completed is shown. Similar to the conventional example, sea urchin ls
Polishing, etching, etc. may be used to make the thickness uniform, photolithography, etching, etc. may be used to form the via hole, and well-known techniques such as vapor deposition, plating, etc. may be used to fill the via hole with metal.

In addition, in the same figure (dl shows a state in which a groove 41 for chip division is formed by etching a portion of the back surface of the wafer that corresponds to a groove 43 previously formed on the front surface of the wafer, and the wafer is divided into individual chips. Here, adjacent chips are connected to each other via a connecting portion 42.

In the manner described above, it is possible to obtain a wafer in which the desired process has been completed and the wafers are connected only by the connecting portion 42. Thereafter, by dissolving the wax 32 used for pasting with a desired solvent, and then washing and drying, a wafer with aligned chips can be obtained.

After this, desired operations such as identifying minute defective marks formed on the wafer surface and inspecting the appearance of chips for presence or absence of defects using a metallurgical microscope, etc. are carried out, and ink is applied to the surface of the defective chip. Known techniques such as adhesion are used to accomplish the desired task of providing a more distinct mark.

At this time, if necessary, it is preferable to attach the wafer face up, that is, the back surface of the wafer, to the auxiliary substrate. For this adhesion, an adhesive such as phenyl salicylate or wax is used.

After the process is complete, the wafer is cut into individual chips. At this time, since the connecting portion 42 is as thin as about 10 μm, it can be easily divided using a sharp knife such as a scalpel.

After the wafer has been divided into chips and undergoes a desired cleaning and drying process, it is preferable to determine whether the chips are good or bad.

At this time, since a clear mark is provided on the surface of the defective chip, it is possible to easily determine whether the chip is good or bad.

In this example, as described above, when forming the chip dividing groove, a desired part of the groove was left to connect the chips to each other, so that the quality of the chips after the final wafer processing step could be checked. Identification can be performed with the chips aligned.

Furthermore, mark adhesion is stabilized by using well-known techniques such as the above-mentioned marking method using ink adhesion on the aligned chips, and by introducing well-known pattern discrimination technology to identify minute defective marks on the chips. I can do it. Furthermore, by stabilizing this mark, it will be possible to determine whether the chip is good or bad and to automate marking in the near future.

In the above embodiment, an example was shown in which the connecting portion is formed near the center of the chip, but it may also be provided at a corner of the chip as shown in FIG. 1(e). be effective.

Furthermore, although the semiconductor device made of GaAs wafer has been described in the above embodiment, other substrate materials may be used.

〔Effect of the invention〕

As described above, according to the method of manufacturing a semiconductor device according to the present invention, the chip dividing groove is formed so that a desired portion remains during the wafer process, so that even when the wafer process is finished, individual chips on the wafer are With just a few changes to the conventional method, it is possible to identify marks indicating defects and inspect the appearance of the chip surface while the chips are aligned, making it possible to identify good and defective chips. This has the effect of making it easier to separate. Moreover, inspection
After identification, the wafer can be divided into individual chips with a simple operation, resulting in a significant effect on production efficiency. Furthermore, by using well-known techniques such as marking methods using ink adhesion, and by introducing well-known pattern discrimination technology to distinguish fine defective marks on chips, it will be possible to stabilize mark adhesion, and in the near future it will be possible to make chips pass or fail. This has the effect of automating discrimination and marking.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a conceptual diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the concept of an sFET, and FIG. 3 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device. In the figure, 21 is a GaAs wafer, 22 is a source electrode, 23 is a drain electrode, 24 is a gate electrode, 25.26
27 is a gold plated portion, 27 is a source gold plated portion, 31 is a glass disk, 32 is wax, 41 is a dividing groove, 42 is a connecting portion, and 43 is a groove. In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A marking process in which the electrical characteristics of individual chips formed on a semiconductor wafer are measured and fine marks are added to defective chips, and after the marking process, areas between the individual chips on the semiconductor wafer are marked. and a wafer dividing groove forming step of forming grooves penetrating from the front surface to the back surface of the wafer except for some regions, and obtaining a divided wafer in which individual chips are connected in the some regions. A method for manufacturing a semiconductor device.