JPH04116445U - interface circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To enable the transmission signal to be taken into the interface circuit of the receiving device even when the level of the transmission signal from the transmitting device is low. [Configuration] Amplifier circuits 20-1 to 20-1 selectively operate on digital signal sources 1 to 3 connected as transmitting side devices, respectively.
20-3 and these amplifier circuits 20-1 to 20
-3 is activated according to the control signal CRS, transmission signals DS1 to D from digital signal sources 1 to 3 are transmitted.
S3 is selectively supplied to the detection circuit 11.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

When transmitting data between multiple devices, this invention allows the receiving device to transmit the transmitted signal. The present invention relates to an interface circuit for receiving data.

0002

[Conventional technology]

Digital devices such as compact disc players and digital audio tape recorders When transmitting data according to a specified format between audio devices, The receiving device that receives the signal synchronizes the operation of the device with the transmitted signal, and Configured to demodulate the received transmission signal into a format compatible with each device . This configuration allows the signal format used within each device to be Even if they are different, data can be exchanged with each other.

0003 FIG. 3 shows an interface circuit that receives a transmission signal at a receiving device. The plurality of digital signal sources 1 to 3 are selectively transmitted to the receiving device 10 as the transmitting device. Transmission according to a predetermined format from connected and selected digital signal sources 1 to 3 The signal DS is transmitted to the receiving device 10. The transmission signal DS is, for example, EIAJ (Japanese According to the format of the Japan Electronics Machinery Industries Association), a 4-bit fixed signal is used as shown in Figure 4. It consists of a signal part and a 28-bit data part, and a total of 32-bit signals are connected. It continues. The interface circuit that receives the transmission signal DS at the receiving device 10 is Consisting of a detection circuit 11, a phase-locked loop 12, and a demodulation circuit 13, the detection circuit 11 According to the clock DCK synchronized with the transmission signal DS obtained from the phase-locked loop 12 generates the basic clock BCK, and the demodulation circuit 13 generates the basic clock BCK based on the basic clock BCK. and is configured to demodulate the transmission signal DS into a predetermined format. That is, the bar The switching of bits in the data part of the transmission signal DS modulated by the e-phase code A clock detected by the detection circuit 11 and synchronized with the timing of bit switching DCK is applied from the detection circuit 11 to the phase locked loop 12 . phase lock loop The clock DCK performs frequency tracking and synchronizes with the clock DCK. generates a basic clock BCK, and supplies this basic clock BCK to the demodulation circuit 13. Ru. Then, the demodulation circuit 13 operates based on the basic clock BCK in synchronization with the transmission signal DS. Then, the parity check of each bit for the transmission signal DS and the reception side equipment 10 are performed. Processing such as demodulation to the corresponding format is performed to create audio in the desired format. The signal ADS is output to the next stage circuit.

0004 On the other hand, digital signal sources 1 to 3, which are transmitting devices, have unique Transmit the format signal after modulating it into a predetermined format common to each device. Configured to send to the line. Therefore, such an interface circuit According to , the receiving device 10 synchronizes with the transmission signal DS, Since the audio signal ADS corresponding to the Signals can be transmitted even if the signal formats are different.

[0005]

[Problem that the idea aims to solve]

However, the transmission signal DS sent out from each digital signal source 1 to 3 is The signal level may vary depending on the output characteristics of digital signal sources 1 to 3, attenuation in the transmission line, etc. is the TTL level of the interface circuit, that is, the digital The receiving device 10 may not be able to transmit the data because There is a possibility that the signal DS cannot be received or cannot be received correctly. So, receive It is conceivable to amplify the transmission signal DS from each digital signal source 1 to 3 on the side. , when the number of connected digital signal sources 1 to 3 increases further, it becomes necessary to amplify the transmission signal DS. A complicated selection circuit is required in addition to the circuit for selecting the This causes problems such as delays and decreased reliability.

[0006]

[Means to solve the problem]

This invention was devised to solve the above-mentioned problems, and its features include: roha, the receiving device receives the transmission signal in a specified format sent from the transmitting device. and an interface that demodulates the above transmission signal into a format compatible with the above receiving side equipment. In the face circuit, a certain gain is given to the above transmission signal received on the receiving side. The amplification means detects the bit switching timing of the transmission signal and detects the bit switching timing of the transmission signal. a detection means for generating a first clock synchronized with the transmission signal; and the first clock. a phase-locked loop that generates a second clock synchronized with the second clock; demodulating means for demodulating the transmission signal into a format compatible with the receiving device according to the The reason is that it has been prepared with the following.

[0007]

[Effect]

According to the present invention, a certain gain is given to the transmission signal received by the receiving device. After that, it is input to the detection circuit, and the transmission of sufficient signal level to the detection circuit is Since the transmission signal is input, the detection circuit reliably detects each timing of the transmission signal. can be done. Then, selectively operating the amplifying means for amplifying the transmission signal, It is now possible to import one output of multiple transmitting devices to the receiving device, and the connected This eliminates the need for complex selection circuits when the number of transmitting devices increases.

[0008]

【Example】

The interface circuit of the present invention is shown in FIG. In this figure, the detection circuit 11 , phase-locked loop 12, demodulation circuit 13, and each digital signal source 1 to 3 are shown in FIG. transmissions that are the same and are selectively input to the detection circuit 11 from digital signal sources 1 to 3; A basic clock that obtains the clock DCK from the signal DS and synchronizes with this clock DCK. BCK is supplied from the phase-locked loop 12 to the demodulation circuit 13. .

[0009] The feature of the present invention is that each digital signal source 1 to 3 is installed in the receiving device 10. Amplifying circuits 20-1 to 20-3 that receive output transmission signals DS1 to DS3 are connected in parallel. By providing and selectively operating these amplifier circuits 20-1 to 20-3, digital One of the transmission signals DS1 to DS3 from signal sources 1 to 3 is taken into the receiving device. There is a particular thing. That is, the amplifier circuit 20-1 is associated with each digital signal source 1 to 3. ~20-3 is activated according to the control signal CRS and the corresponding digital signal source 1 The transmission signals DS1 to DS3 from ~3 are amplified to a predetermined level and supplied to the detection circuit 11. configured to do so. Here, the control signal CRS is the amplifier circuit 20-1 to 20-3. By activating one of them and leaving the rest inactive, the receiving device 10 is selected.

0010 Each amplifier circuit 20-1 to 20-3 has a feedback path, for example, as shown in FIG. It is composed of an inverter and is inactive by closing the return path according to the control signal CRS. It is considered to be a state. The transmission signal DS is connected to a capacitor 21 for removing DC components and input protection. The output of this inverter 23 is inputted to the inverter 23 via the resistor 22 of The signal is supplied to the detection circuit 11 via the inverter 24. Also, the output of the inverter 23 is , and are fed back to the input side via the feedback resistor 25 to form an amplifier circuit. this return route is provided with an analog switch 26 that operates in response to a control signal CRS, and The input side of the inverter 23 is connected to the input side of the inverter 23 according to the control signal CRS. An N-channel type transistor 27 is provided which pulls the side to ground potential. subordinate Therefore, when the control signal CRS is "0", the analog switch 26 is turned on and the trigger is turned on. Since the transistor 27 is turned off, the output of the inverter 23 is transferred to the feedback resistor 25 for amplification. The signal is fed back to the input side via the input signal DS, and gives a predetermined gain to the transmission signal DS. On the contrary, control When the control signal CRS becomes "1", the analog switch 26 turns off and the transistor 27 is turned on, the input of inverter 23 is fixed at ground potential and becomes inactive. Therefore, the digital output DS is no longer captured.

[0011] The control signal CRS that controls these amplifier circuits 20-1 to 20-3 is 20-1 to 20-3, that is, corresponding to the number of connected digital signal sources 1 to 3. In the case of FIG. 1, it is composed of 3 bits, and each bit is an amplifier circuit 20-1 to 20-. given to 3. This control signal CRS is a 3-bit signal sent directly to the receiving device 10. Although input may be input directly, in general, input for selection control of the receiving device 10 is Considering the reduction in the number of input terminals, the binary data is decoded inside the receiving device 10. A 3-bit signal is obtained.

0012 In the above interface circuit, the detection circuit 11, the phase lock In addition to the loop 12 and the demodulation circuit 13, there are also By integrating the amplifier circuits 20-1 to 20-3 into one chip, the receiving device 10 It is possible to reduce the number of parts and simplify wiring when configuring. In addition, the amplifier circuit 20- Since the circuit configurations of 1 to 20-3 are simple, they can be used as standard circuit blocks. The standard cell method, in which circuits are designed by combining blocks, makes circuit design easy. , to minimize the increase in chip area for the interface circuit shown in Figure 3. I can do that.

[0013]

[Effect of the idea]

According to the present invention, by making the selection circuit perform an amplification operation, the transmitting side The transmission signal from the device is amplified and captured by the interface circuit of the receiving device. As a result, the receiving device can reliably judge the digital signal, and the transmission This can prevent the receiving device from becoming unable to receive the signal. Also, selectively By incorporating a working amplifier circuit into the interface circuit, the connecting transmitter Even if the number of devices increases, it can be handled without major circuit changes or additions. This makes it possible to realize an inexpensive and highly reliable interface circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an interface circuit of the present invention.

FIG. 2 is a circuit diagram of an amplifier circuit built into the interface circuit.

FIG. 3 is a block diagram showing the configuration of a conventional interface circuit.

FIG. 4 is a diagram showing the format of a transmission signal.

[Explanation of symbols]

1-3 Digital signal source 10 Receiving side equipment 11 Detection circuit 12 Phase-locked loop 13 Demodulation circuit 20 Amplifier circuit

Claims (2)

[Scope of utility model registration request] Claim 1: In an interface circuit that receives a transmission signal in a predetermined format sent from a transmission side device at a reception side device and demodulates the transmission signal into a format compatible with the reception side device, the transmission signal received at the reception side an amplification means that provides a constant gain to the signal; a detection means that detects the timing of bit switching of the transmission signal and generates a first clock synchronized with the transmission signal;
A phase-locked loop that generates a second clock synchronized with the first clock; and demodulation means that demodulates the transmission signal into a format compatible with the receiving device according to the second clock. interface circuit. 2. A plurality of said amplification means are respectively associated with transmission signals from a plurality of transmission side devices, and said plurality of said amplification means are selectively activated to transmit signals from said plurality of transmission side devices. 2. The interface circuit according to claim 1, wherein one of the interface circuits is input to a receiving device.