JP2508729B2 - Timing extraction circuit - Google Patents

Description

The present invention relates to a timing extraction circuit for extracting a clock signal from a coded signal, and more particularly to a binary coded NR.
The present invention relates to a timing extraction circuit from a Z (Non Return to Zero) signal.

[Conventional technology]

This type of timing extraction circuit is widely used for signal transmission via a coaxial cable or an optical fiber. As a reference, Takashi Kaneko, "PCM Communication Technology," pp
・ 84-88, Industry Bulletin, 1976. FIG. 2 shows a configuration example of a data link terminal station using an optical fiber.
In this figure, the optical signal transmitted through the optical fiber 30 is converted into an electric signal by the optical receiver 32 and becomes the input signal 39. Timing extraction circuit from this input signal 39
The data signal 35 and the clock signal 36 are extracted by 33. The extracted signal is converted by the encoding / decoding circuit 37 into a format suitable for the input / output signal of the signal processing circuit 38. The processed signal is encoded again by the encoding / decoding circuit 37 to become the output signal 40. The output signal 40 is converted into an optical signal by the optical transmitter 34 and sent to the next terminal station via the optical fiber 31.

An example of the timing extraction circuit 33 is shown in FIG. The signal input terminal 1 is a terminal for applying the input signal 39 shown in FIG.
The tank circuit 4 is a band pass filter using a crystal or a surface acoustic wave device. The resonance frequency of this filter is set to match the frequency of the clock signal. Since the clock signal extracted by the tank circuit 4 has a small amplitude, the amplifier 5
Amplify with to make the logic signal amplitude. The output signal of the amplifier 5 is output from the clock output terminal 15, which corresponds to the clock signal 36 in FIG. This clock signal is also connected to the clock input terminal of the D-type flip-flop 2, and the D-type flip-flop 2 synchronizes the data signal with the clock signal. The data signal synchronized with the clock signal is led to the data output terminal 3, which corresponds to the data signal 35 in FIG.

[Problems to be solved by the invention]

In the above-described conventional timing extraction circuit, the amplitude of the output signal of the tank circuit 4 changes when the mark ratio of the input signal (time occupation ratio of "0" and "1") changes. In order to amplify this signal to a sufficient amplitude, the amplification factor of the amplifier 5 needs to be sufficiently large. However, when the mark ratio of the input signal is large (close to 1/2), the amplification ratio required for the amplifier 5 is close to 1. When an amplifier with a large amplification factor is applied to such a system, both the noise signal superimposed on the power supply line and the electromagnetic induction noise signal are also amplified with a large amplification factor, so the output signal of the amplifier contains a lot of jitter. There is a problem that it will be lost.

The present invention is intended to solve such a problem of the conventional one, and provides a timing extraction circuit which prevents amplification of an unnecessary signal and increase of jitter of a clock.

[Means for solving problems]

The timing circuit of the present invention inputs a signal containing a clock component, extracts a clock component from the input signal, a D-type flip-flop for synchronizing the input signal and the clock signal, and the tank circuit. In a timing extraction circuit composed of an amplifier for amplifying an output signal, a mark ratio detection circuit for detecting a mark ratio of a signal containing the clock component, and an amplification factor of the amplifier variable according to an output of the mark ratio detection circuit. And means for doing so.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this figure, a signal including a clock component is input to the signal input terminal 1. A clock component is extracted from this input signal by a tank circuit 4 and amplified by an amplifier 5, and then data and a clock are synchronized by a D-type flip-flop 2. The synchronized data is sent out from the data output terminal 3. The mark rate detection circuit 6 detects the mark rate of the input signal and outputs a voltage proportional to the value. Amplifier 5 '
Uses a voltage control type amplifier so that the amplification factor changes according to the output voltage of the mark ratio detection circuit 6. The clock signal output from the amplifier 5'is provided to the D-type flip-flop 2 and the clock output terminal 15.

In this embodiment, the amplification factor of the amplifier 5'when the mark ratio is 1/2 is 10 dB in order to compensate for the loss of the tank circuit 4. When the mark ratio drops to 1/10, the amplifier 5'is designed so that the amplification factor rises to 24 dB.
The output amplitude of can be kept constant.

〔The invention's effect〕

As described above, the present invention has the effect of preventing unnecessary signals from being amplified and increasing clock jitter by varying the amplification factor of the amplifier in accordance with the mark ratio of the input signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a data link terminal station using an optical fiber, and FIG.
FIG. 1 is a block diagram of an example of a conventional timing extraction circuit. In the figure, 2 is a D-type flip-flop, 4 is a tank circuit,
5, 5'is an amplifier, and 6 is a mark ratio detection circuit.

Claims (1)

(57) [Claims] 1. A tank circuit for inputting a signal containing a clock component and extracting the clock component from the input signal; a D-type flip-flop for synchronizing the input signal with the extracted clock signal; In a timing extraction circuit composed of an amplifier for amplifying an output signal of a tank circuit, a mark ratio detection circuit for detecting a mark ratio of a signal containing the clock component, and amplification of the amplifier according to an output of the mark ratio detection circuit. A timing extraction circuit including means for varying the rate.