JP3048769B2 - Input amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input amplifier circuit for receiving a transmission signal on a receiving side when data is transmitted between a plurality of devices.

[0002]

2. Description of the Related Art When transmitting data according to a predetermined format between digital audio devices such as a compact disk player and a digital audio tape recorder, the transmission signal receiving side synchronizes the device with the transmission signal and transmits the received transmission signal. An interface circuit for demodulating the signal into a format corresponding to the device is configured.
According to this interface circuit, data can be exchanged with each other even when the format of a signal used in each device is different.

FIG. 3 is a block diagram of an interface circuit for receiving a transmission signal at a receiving device. The transmission signal DIN sent from the transmission-side device is, for example, EIAJ
According to the standards of the Japan Electronic Machinery Manufacturers Association, it is composed of a fixed signal portion of 4 bits and a data portion of 28 bits in a total of 32 bits, and the digital signal of 32 bits is continuous. This transmission signal DIN is first taken into the input amplifier 1, amplified to a predetermined level, and then given to the receiving circuit 2. The input amplifier 1 amplifies a transmission signal attenuated in the transmission path from the transmission side to the reception side to a level that can be handled as a digital signal, and shapes the waveform to obtain a square wave. It is composed of an added inverter. Receiving circuit 2
, The transmission signal D modulated to the biphase code
The switching of bits in the data portion of IN is detected, and the data clock D coincides with the timing of the switching.
CK is taken out. The data clock DCK serves as a reference clock for the phase locked loop 3, and the phase locked loop 3 generates a system clock BCK synchronized with the data clock DCK. On the other hand, the demodulation circuit 4 receives the transmission signal DIN from the reception circuit 2 and demodulates the transmission signal DIN into a format corresponding to the device on the receiving side, based on the reference clock BCK given from the phase locked loop 3, and also transmits the transmission signal DIN. Is subjected to processing such as parity check of each bit. Therefore, in the demodulation circuit 4, a processing operation is performed in synchronization with the transmission signal DIN (system clock BKC), and an audio signal ADS in a desired format is output to the next circuit such as an audio amplifier.

FIG. 4 is a circuit diagram showing a configuration of the input amplifier 1. A capacitor 11 for removing a DC component is connected to the input side IN.
2 inputs. The output of the inverter 12 is connected to the input of the inverter 12 via the feedback resistor 13 and is supplied to the output OUT through the inverter 14. As a result, the input potential of the inverter 12 becomes the threshold potential of the inverter 12, and the inverter 12 is inverted by a slight change in the input potential. Therefore, the level change of the signal supplied to the capacitor 11 is amplified, and a rectangular wave is output from the output OUT. Thus, a signal of the power supply potential level can be obtained.

By the way, in a normal interface circuit, a plurality of input amplifiers are provided in parallel, and these are selectively operated. In an unselected input amplifier, the input side is in a floating state. In the case of such an input amplifier, since the state of the inverter 12 is extremely unstable, the output may be inverted in response to a slight noise, or may be affected by crosstalk from another input amplifier. Yes, it causes the interface circuit to malfunction.
Therefore, by applying a power supply potential to the input of the inverter 12 via the resistor 15, the input potential of the inverter is slightly higher than the threshold potential of the inverter 12, and the inverter 12 is in a stable state.

[0006]

A normal transmission signal has a slow rise and fall due to the effects of attenuation and delay in the transmission path, and does not form a perfect rectangular wave. Therefore, when the input potential of the inverter 12 is made higher than the threshold potential to change the center point of the operation of the inverter 12, the transmission signal DIN1 given to the input side of the input amplifier 1 and the output side are obtained as shown in FIG. The duty ratio does not match with the transmission signal DIN2. That is, in the input amplifier 1, the output potential of the inverter 12 is
, The output falls when the voltage exceeds the threshold potential _Vth , and the output _rises when the voltage falls below the threshold potential _Vth. The duty ratio changes by the delay of the rise and fall of.

In the receiving circuit 2 receiving the transmission signal DIN from the input amplifier 1, the data clock DCK is obtained at the rising or falling timing of the transmission signal DIN, and if the duty ratio of the given transmission signal DIN changes, Data clock DCK for transmission signal DIN
Will also change. For this reason, the operation of the phase lock loop 3 becomes unstable, which causes an increase in jitter.

Accordingly, an object of the present invention is to provide an input amplifier for suppressing a change in a duty ratio of an output signal with respect to an input signal.

[0009]

DISCLOSURE OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the feature of the present invention is that an input signal which takes in a transmission signal transmitted from a transmitting device and gives it to a receiving circuit is provided. In the amplifier circuit, a capacitor for extracting a signal component of the transmission signal, and a first component for receiving the signal component of the transmission signal on an input side through the capacitor.
An inverter, a feedback resistor for feeding back the output of the first inverter to the input, and a switch means for applying a constant potential exceeding a determination level of the first inverter to the input side of the first inverter through a predetermined resistor. A second inverter for transmitting the output of the first inverter to the receiving circuit, and a control circuit for controlling the switch means in response to the operation of the receiving circuit.

[0010]

According to the present invention, when the receiving circuit starts normal operation, the switch means for applying a constant potential through a resistor to the input side of the inverter is turned off. Since the center point of the operation of the above becomes the threshold potential, the signal obtained from the output side of the inverter is
The duty ratio matches the signal supplied to the input side. Therefore, the receiving circuit extracts a clock that matches the timing of the transmission signal.

[0011]

FIG. 1 is a block diagram of an input amplifier according to the present invention and an interface circuit using the input amplifier. In this figure, a receiving circuit 21, a phase locked loop 22, and a demodulating circuit 23 have the same configuration as in FIG.
The transmission signal DIN given from 0 is taken into the receiving circuit 21, the receiving circuit 21 obtains a data clock DCK synchronized with the transmission signal DIN and supplies the data clock DCK to the phase lock loop 22, and the signal component of the transmission signal DIN to the demodulation circuit 2. Configured to give.

The input amplifier 20 has a capacitor 3 on the input side.
1, the input of the inverter 32 is connected to the capacitor 31, and the output of the inverter 32 is connected to the input via the feedback resistor 33.
2 is provided to the output side through an inverter 34. A power supply potential is applied to the input of the inverter 32 via a resistor 35 and a switch 36, and the switch 36 is controlled to open and close according to a lock detection signal LDS supplied from a lock detection circuit 24 described later. The lock detection circuit 24 is provided in association with the demodulation circuit 23, and determines that the phase lock loop 22 has locked when an error does not occur several times consecutively in the result of the parity check performed in the demodulation circuit 2, It is configured to output a lock detection signal LDS for turning off the switch 36 of the input amplifier 20. That is, since the system clock BCK itself is not stable until the phase lock loop 22 locks, and the duty ratio of the transmission signal DIN has no effect, the switch 36 of the input amplifier 20 is turned on. The center point of the operation of the inverter 32 is set higher than the threshold potential. When it is detected that the phase lock loop 22 is locked, the switch 36 is turned off and the inverter 3 is turned off.
By using the center point of the operation 2 as a threshold potential and matching the duty ratio between the input side and the output side of the input amplifier 20, the timing shift of the data clock DCK with respect to the transmission signal DIN is eliminated. According to the measurement, when the frequency of the system clock BCK is set to 2.8 MHz, when the switch 36 is turned on, the timing difference between the reference data clock DCK and the system clock BCK obtained by the phase lock loop 22 is obtained. Is 2.5 nsec on average, whereas 1.8 nsec on average when switch 36 is turned off. Therefore, the operation of the phase lock loop 22 becomes more stable, jitter can be reduced, and the accuracy of the interface circuit can be improved.

As a method of detecting that the phase lock loop 22 is locked, a method of judging from the operation state of the demodulation circuit 23 or a method of judging from the output of the phase comparator constituting the phase lock loop 22 is also possible. It is. in this case,
The lock detection circuit is provided to be attached to the phase lock loop 22. By the way, regarding the input amplifier 20, FIG.
As shown in FIG. 7, in addition to the one-to-one correspondence between the input amplifiers 20 and the interface circuits, it is also possible to connect a plurality of input amplifiers 20 in parallel to one interface circuit and selectively operate them. It is. For example,
As shown in FIG. 2, the receiving circuit 21 has two input amplifiers 2
0a and 20b are connected and transmission signals DINa and DINb are selectively applied to one of the input amplifiers 20a and 20b, so that two inputs can be set in the interface circuit. In this case, in the input amplifiers 20a and 20b to which the transmission signal is not applied, the input side is in the floating state, but the respective switches 36 are turned on and the power supply potential is applied to the input side of the inverter 32 via the resistor 35. , The inverter 32 enters a stable state. Then, a selection control signal CRS generated externally is applied to each of the input amplifiers 20a and 20b, and only the input amplifiers 20a and 20b to which the transmission signal is applied respond to the lock detection signal LDS. Input amplifier 20 in state
Malfunctions of a and 20b are reliably prevented.

[0014]

According to the present invention, after the operation of the interface circuit rises, the center point of the operation of the inverter constituting the input amplifier is made equal to the threshold potential, so that the duty ratio of the input transmission signal is reduced. Can be obtained. If this input amplifier is used for the input portion of the interface circuit, a stable reference clock can be given to the phase locked loop, so that jitter is suppressed and errors are less likely to occur during demodulation processing in the demodulation circuit. And reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional interface circuit.

FIG. 4 is a circuit diagram of an input amplifier incorporated in the interface circuit.

FIG. 5 is a waveform diagram of an input signal and an output signal of an input amplifier.

[Explanation of symbols]

 1, 20 Input amplifier 2, 21 Receiving circuit 3, 22 Phase locked loop 4, 23 Demodulation circuit 24 Lock detection circuit 11, 31 Capacitor 12, 14, 32, 34 Inverter 13, 15, 33, 35 Resistor 36 Switch

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 25/00 H04L 7/00

Claims (1)

(57) [Claims] An input amplifier circuit for receiving a transmission signal transmitted from a transmission-side device and supplying the transmission signal to a reception circuit, a capacitor for extracting a signal component of the transmission signal, and a signal component of the transmission signal passing through the capacitor to an input side. A first inverter receiving the first inverter, a feedback resistor for feeding back the output of the first inverter to the input, and a first resistor through which a predetermined potential exceeding the determination level of the first inverter is passed through a predetermined resistor. Switch means for providing an input to the inverter, and a second means for transmitting the output of the first inverter to the receiving circuit.
And an operation of the receiving circuit.
Turn off the above switch means when synchronizing with the transmitted signal.
And an input amplifier circuit.