JPH04114511A - Cmos inverter - Google Patents

Abstract

PURPOSE:To suppress the generation of noise without increasing the power consumption of a logic circuit by providing an output voltage level guarantee circuit in parallel to an inverse speed control circuit. CONSTITUTION:Since the current supply capacity of an N-channel MOS transistor Q3 is much larger than that of a P-channel MOS transistor Q4, a load circuit is mainly driven by a current supplied from the N-channel MOS transistor Q3 in an initial stage. The potential of the high level of an output signal rises to the potential (VDD-VTN) dropped from a power voltage by the threshold value voltage of the N-channel MOS transistor Q3 by the operation. Since the N- channel MOS transistor Q3 comes to an off state a small current flows only in a P-channel MOS transistor Q4 and the potential of an output terminal is gradually raised. Thus, the generation of noise can be prevented without increasing the power consumption of the logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an inverter, and particularly to a circuit configuration of a CMOS inverter.

[Conventional technology]

Inverter using CMOS transistor connection (hereinafter referred to as CM
The basic circuit configuration of the OS inverter (hereinafter referred to as an OS inverter) is a configuration in which a P-channel MO8 transistor and an N-channel MOS transistor are connected in series between a power supply voltage terminal and a ground terminal.

Since this CMOS inverter is one of the basic circuits constituting a logic circuit, it is used in large numbers in semiconductor integrated circuits.

By the way, as mentioned above, a large number of CMOS inverters are used in semiconductor integrated circuits, so when they operate simultaneously, the amount of charge movement when a signal is inverted is large.
Therefore, noise is likely to occur.

Conventionally, various methods have been devised to prevent the generation of noise in such CMOS inverters.

One method for preventing this noise is to limit the amplitude of the output signal of the CMOS inverter to slow down the inversion speed and control the amount of charge movement.

FIG. 3(a) shows a circuit configuration of an example of a CMOS inverter that takes such measures.

This CMOS inverter differs from the basic CMOS inverter in which a P-channel MOS transistor Q1 and an N-channel MOS transistor Q2 are connected in series and each gate is connected to the input terminal 1, as shown in Fig. 3(a). As shown, an N-channel MO8 transistor Q3 is connected between the power supply voltage terminal 2 and the source of the P-channel MO8 transistor Q, and the gate of this N-channel MOS transistor Q3 is connected to the power supply voltage terminal 2 to set the gate potential. The circuit configuration is fixed to the power supply voltage VDD.

With this circuit configuration, the source potential of the P-channel MO8 transistor Q1 is lower than the power supply voltage VDD by the threshold voltage (VT
The potential is lower by the amount (N).

Therefore, as shown in the waveform of the input/output signal in FIG. 3(b), when a low level input signal is input, the P channel MO3
When transistor Q1 is conductive and a high-level output signal is output to output terminal 3, the value of its potential is (V DD
-V TN) and cannot rise to the power supply voltage VDD.

That is, since the potential of the high-level output signal is limited, the inversion speed of the output signal becomes slow.

[Problem to be solved by the invention]

In the conventional CMOS inverter described above, the potential of the high-level output signal is a value lower than the power supply voltage by the threshold voltage of the N-channel MO8 transistor Q3 (vDo-V
lN).

Therefore, if the same type of inverter is connected to the next stage of this CMOS inverter, depending on the potential value of the high-level output signal of the driving side CMOS inverter,
A problem arises in that in the next stage inverter, the P-channel MO8 transistor and the N-channel MOS transistor may become conductive at the same time, increasing power consumption.

[Means to solve the problem]

The CMOS inverter of the present invention comprises M
A CMOS in which an inversion speed control circuit is provided between the power supply side terminal of the OS transistor and the corresponding power supply voltage terminal.
The inverter is characterized in that an output voltage level guarantee circuit is provided in parallel with the inversion speed control circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a circuit diagram showing the circuit configuration of a first embodiment of the present invention, and FIG. 1(b) is a diagram showing operating waveforms of input/output signals in this first embodiment. It is.

As shown in FIG. 1(a), the circuit configuration of this embodiment is different from the conventional CMOS inverter shown in FIG. The gate of this P-channel Mos transistor Q4 is connected to the input terminal 1.

The current supply capacity of this P-channel MO8 transistor Q4 is designed to be much smaller than the current supply capacity of the N-channel MO8 transistor Q3, as will be understood from the explanation of the operation of the circuit described later.

Next, the operation of this CMOS inverter will be explained.

First, when the input signal changes from high level to low level, P channel MO8 transistors Q1 and Q4 are turned on.

Also, regarding the N-channel MOS transistor Q3,
Since the gate potential is always the same as the drain potential, this N-channel MO8 transistor is also turned on.

Therefore, at this time, the P-channel MO8 transistor Q receives current from the P-channel MO8 transistor Q4 and the N-channel Mos transistor Q3 to drive the next stage load circuit (not shown).

However, in this case, the current supply capacity of the N-channel MOS transistor Q3 is much larger than that of the P-channel MO8 transistor Q4, so in the initial stage, the load circuit mainly uses this N-channel MOS transistor Q4.
Driven by current supplied from transistor Q3.

As a result of this operation, the high-level potential of the output signal is reduced to a potential lower than the power supply voltage by the threshold voltage of the N-channel MOS transistor Q3, as shown in FIG. MDI)-vTN)
The gusset rises.

After that, after the potential of the output signal reaches (V no V TN), the N-channel MOS transistor Q3 is turned off, so the P-channel MO8 transistor Q
4 is a small current that gradually raises the potential of the output terminal.

Then, the potential of the output signal finally becomes the power supply voltage VD
It has the same value as D.

That is, in this embodiment, when the output signal is inverted from low level to high level, the amplitude is limited in the initial stage, so the inversion speed is slow like the conventional CMOS inverter, and the final Specifically, the potential of the high-level output signal becomes the same value as the power supply voltage.

Next, a second embodiment of the present invention will be described.

FIG. 2(a) is a circuit diagram showing the circuit configuration of a second embodiment of the present invention. FIG. 2(b) is a diagram showing operating waveforms of input/output signals in this second embodiment.

In this embodiment, as shown in FIG. 2(a), FIG.
), P-channel MO8 transistors Q5 and N are also connected in parallel between the source of the N-channel MOS transistor and the ground terminal 4.
A channel MOS transistor Q6 is provided.

The gate of the P-channel MO8 transistor Q6 is connected to the ground terminal 4, and the gate of the N-channel MOS transistor Q
6 is connected to input terminal 1.

Note that the current supply capability of these two MOS transistors is designed so that the P-channel MO8 transistor Q5 is much larger.

With this circuit configuration, when the input signal changes from low level to high level and the output signal changes from low level to high level, in the first stage, the charge in the next stage load circuit is mainly transferred to the P-channel MO8. Discharged by the current flowing through the transistor Q5, the low level potential of the output signal is lower than the ground potential (zero) to the threshold voltage of the P-channel MOS transistor Q5 (VTR and ) will fall to a higher value.

After that, this P-channel MO3 transistor Q5 is turned off, so it is discharged by only a small current flowing through the N-channel MOS transistor Q8, and the potential of the low-level output signal gradually decreases, eventually reaching the same level as the ground potential. Become.

The operation when the input signal changes from high level to low level and the output signal changes from low level to high level is the same as in the first embodiment.

Therefore, in this embodiment, even when the output signal changes from low level to high level, or conversely from high level to low level, the reversal speed is slow, and the final potential value of the output signal is , the same value as the power supply voltage and ground potential.

〔Effect of the invention〕

As explained above, according to the present invention, in a CMOS inverter, the amplitude of the output signal can be made to swing fully between the power supply voltage and the ground potential, and the inversion speed can be controlled to be gentle. Therefore, the generation of noise can be suppressed without increasing the power consumption of the logic circuit.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are circuit diagrams showing the first practical circuit configuration of the present invention and diagrams showing operating waveforms of input/output signals, and FIGS. 2(a) and (b) are , a circuit diagram showing a circuit configuration of a second embodiment of the present invention and a diagram showing operating waveforms of input/output signals, FIGS. 3(a) and 3(b) are circuit diagrams showing a circuit configuration of a conventional CMOS inverter. FIG. 3 is a diagram showing operation waveforms of input and output signals. 1...Input terminal, 2...Power supply voltage terminal, 3...Output terminal, 4...Ground terminal.

Claims (1)

[Claims] In a CMOS inverter in which an inversion speed control circuit is provided between a power supply side terminal of a MOS transistor constituting an inversion circuit and a corresponding power supply voltage terminal, the inversion speed control circuit is provided in parallel with the inversion speed control circuit. A CMOS inverter characterized by being provided with an output voltage level guarantee circuit.