JPH04111463A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce power consumption and further increase the degree of integration by using a low voltage parasitic MOS transistor where its load device is locally formed in a device isolation region in terms of 6 device SRAM memory cells. CONSTITUTION:At first on a P type Si substrate 41 is formed a device isolation oxide film 42, say, 5000Angstrom based on the application of a known selection oxidation technology. Then, a resist pattern 43 having an opening section is prepared where the opening section is arranged to be in a region which forms a parasitic MOS transistor of low threshold voltage. Furthermore, the oxide film is etched so that the remaining film may be 2000Angstrom , for example. N type impurities are ion-implanted in a thin oxide film region. For example, when <31>P<+> is implanted by 2000keV, 7X10<11> ions/cm<-2>, the threshold voltage will be about 0V. The gate oxide film, gate electrode, source/drain diffusion layers will be formed based on the known technology.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure and manufacturing method of an SRAM memory cell, which is a type of semiconductor memory device, and is constituted by six transistor elements.

(Prior Art) FIG. 2 ( ) is an equivalent circuit diagram of a memory cell of a first example of a conventional SRAM in which all six elements Tr 21 to Tr 26 use enhancement l-MOS transistors.

Enhancement MO8 for both load element and active element)
Inverter output using transistors! 1L11 condition,
The "H" state is determined from the voltage-current characteristics of each transistor as shown in FIG. 2(b).

In the “L” state, the T of the transistor used as a load element
r21 + Tr2□ Since a current flows that is determined by the gate width and gate length, in order to reduce power consumption, the gate width of the load element must be made small and the gate length must be made large, which increases the area of the memory cell. .

FIG. 3 is an equivalent circuit diagram ( ) of a memory cell of a second conventional SRAM using high resistances R51 and R52 as load elements, and an explanatory diagram (b) of an inverter operation. Resistance element R31# R5□ as active element Tr 5 s~Tr
By stacking them on top of the memory cell 56, it is possible to reduce power consumption without increasing the area of the memory cell.

(Problems to be Solved by the Invention) As mentioned above, enhancement type memory cells cannot achieve low power consumption unless the transistors that serve as load elements are made large, and it is difficult to create highly integrated and large capacity SRAM memories. Have difficulty.

In addition, memory cells with high resistance loads are highly integrated and
Generally used for large capacity SRAM memory,
Since the resistance element is formed on the active element (transistor), the manufacturing process becomes complicated, which causes an increase in manufacturing TAT (process completion time) and a decrease in yield.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention, in a six-element SRAM memory cell, replaces the load element with a parasitic MO3 with a low threshold voltage locally formed in the element isolation region. ) using transistors.

Furthermore, the present invention provides the method of applying selective oxidation onto a semiconductor substrate.
a step of forming a thick element isolation oxide film; a step of forming a resist pattern with a partially open hole on the element isolation oxide film; and etching the element isolation oxide film using the resist as a mask. A depletion type parasitic MOS l-transistor is formed by a step of reducing the film thickness and a step of ion-implanting an impurity of conductivity type opposite to that of the semiconductor substrate using the lenost as a mask.

(Function) As mentioned above, in the present invention, an SRAM consisting of six elements
A parasitic MOS transistor with a low threshold voltage formed locally in an element isolation region is used as a load element of a memory cell, and its manufacturing method is also different from the conventional MOS transistor.
For OS transistor manufacturing process.

It is only necessary to add one resist patterning process, one etching process, and one ion implantation process, making it possible to realize a highly integrated SRAM memory with short TAT, low power consumption, and low power consumption.

(Example) FIG. 1 is an equivalent circuit diagram of an SRAM memory cell according to the present invention. Conventionally, enhancement type transistors,
A parasitic MOS transistor Tr 11 t Tr 12 with a low threshold voltage and whose gate electrode is connected to a power supply line is used as a load element that used a high resistance.

MOS! -Lanzosta current value engineer. is the relationship when the drain and date voltages are fixed. Here, μ is the charge mobility and ε. is the dielectric constant of the gate oxide film, tox is the gate oxide film thickness, W, L
are the gate width and gate length of the MOS transistor, respectively.

Normally, the element isolation oxide film thickness is 10 to 30 times the gate oxide film thickness of the drive transistor (for example, the gate oxide film thickness is 30 to 30 times).
In the case of 0X, the element isolation oxide film thickness is 3000 to 9000X
), compared to a load transistor that uses the same date oxide film thickness as the drive transistor, a load transistor that uses an element isolation oxide film has the same size (W and L).
When the current value is 1/10 to 1/306 or a similar current is passed, the gate length is 1/10 to 1/30, which allows for low power consumption and high integration.

Normally, a parasitic MO8) transistor has a very large threshold voltage due to its original purpose, for example, an element isolation oxide film thickness of 5000×, a P-type substrate surface concentration of 5×10
tons/crn is 16V. Therefore, in order to use it as a load element, it is necessary to
It is necessary to distinguish between load element regions.

FIG. 4 shows a method of forming a low threshold voltage parasitic MOS transistor region.

(a) An element isolation oxide film 42 having a thickness of, for example, 5000× is formed on a P-type St substrate 41 using a known selective oxidation technique.

(b) Parasitic MO with low threshold voltage 8) A resist pattern 43 having an opening in a region where a transistor is to be formed is created.

(c) Using the resist pattern 43 as an etching mask, the oxide film 42 is etched with, for example, 5% diluted hydrofluoric acid (HF), leaving a remaining film of, for example, 2000 etchings.

The surface concentration of the P-type substrate is 5×101610 n s/
Considering the example of '2'ff+-3, the oxide film thickness is 5000
By setting X to 2000X, the threshold voltage is 16,
V can be lowered to 6.5v.

Using the resist pattern 43 as a mask, N-type impurity ions are implanted into the thin oxide film region formed in (c). For example, 51P+ is 5 to 1 at 150 to 300 keV.
Enter 0 X 10” tons/2y++-2.3
1P+ to 200 keV, 7
By implanting ns/z-2, the threshold voltage can be lowered by about 6.5 cm, and in the case of the above example, the threshold voltage becomes about Ov.

(d) Hereinafter, by using a known technique, a gate oxide film,
Form a date electrode and source/drain diffusion layer.

(Effects of the Invention) As described above in detail, in the present invention, a parasitic MO3) transistor with a low threshold voltage locally formed in an element isolation region is used as a load element of an SRAM memory cell consisting of six elements. Furthermore, in the manufacturing method, a resist patterning process, an etching process, and an ion implantation process are added to the conventional MOS transistor manufacturing process.
It is possible to manufacture a highly integrated SRAM memory with a short TAT, low power consumption, and only an additional cycle.

Furthermore, since the conditions for the additional manufacturing process can be set completely independently of the manufacturing process of the drive transistor, it becomes easy to realize high-performance LSIs such as memory-mounted gate arrays and standard cell LSIs.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention, FIG. 2 is a first conventional example of an SRAM memory cell, FIG. 3 is a conventional second example of an SRAM memory cell, and FIG. 4 is a diagram of the present invention. It is a manufacturing process diagram of an example. Tr111Tr12'45'' Parasitic MO8) transistor, Tr13+Tr14. ...Resist. Patent applicant: Oki Electric Industry Co., Ltd. ■ (b) B brush explanatory diagram of the conventional second I month. SRAM memory diagram

Claims (2)

[Claims] (1) The gates and drains of the first and second transistors are both connected to the power supply, and the source of the first transistor is connected to the third transistor.
The drain of the transistor and the gate of the fourth transistor are connected to the first bit line through the fifth transistor, and the source of the second transistor is connected to the fourth bit line.
The drain of the transistor, together with the gate of the third transistor, are connected to the second bit line through the sixth transistor, the sources of the third and fourth transistors are both connected to ground potential, and the fifth and In a semiconductor memory device in which gates of a sixth transistor are connected to the same word line, the first and second transistors use a gate oxide film as an element isolation oxide film to locally reduce a threshold voltage. A semiconductor memory device characterized in that it is a MOS transistor. (2) a step of forming an oxide film for element isolation on a semiconductor substrate; a step of forming a resist pattern having openings so as to locally connect element regions on the oxide film for element isolation; The method includes the steps of: using a resist pattern as a mask, etching the element isolation oxide film to reduce the film thickness; and using the resist pattern as a mask, ion-implanting an impurity having a conductivity type opposite to that of the semiconductor substrate. A method for manufacturing a semiconductor memory device.