JPH0411135B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous modulation/demodulation device in a serial transmission system.

[Conventional technology]

Conventionally, as this type of apparatus, the Mantier system, the Biphas system, and the like are known.

FIG. 4 shows the configuration of a general serial transmission system. Note that although the full-duplex system is shown and explained here, the same explanation will suffice for the half-duplex system, so the explanation will be omitted here. In the figure, 1A and 1B are serial controllers, 2A, 2B and 3A, 3B are modulators and demodulators corresponding to the serial controllers 1A and 1B, respectively, and 4AB and 4BA are transmission lines. Transmission data from the above serial controller 1A
TXD is the transmit clock pulse from modulator 2A
The signal is sent to the modulator 2A in synchronization with TXC, modulated, and sent out to the transmission path 4AB. On the other hand, the transmission path (modulation) data inputted to the demodulation path 3B via the transmission path 4AB is demodulated and received data RXD
and receive clock pulse RXC, and sent to the serial controller 1B. Transmit data TXD from serial controller 1B using the same procedure.
is transmitted to the serial controller 1A via the modulator 2B, transmission line 4BA, and demodulator 3A.

The conventional device will be explained below based on FIGS. 5 and 6. FIG. 5 is a circuit diagram showing an example of a modulator and a demodulator of a conventional device.
7, an OR (logical sum) circuit 8, and a JK type flip-flop 9. On the other hand, the demodulator 3 includes an oscillator 10 and D-type flip-flops 11, 12, 1.
3, 14 and EOR (exclusive OR) circuits 15 and 16
Frequency division counters 16, 17 and NOT (negation) circuit 18
It is composed of.

Next, a conventional modulation/demodulation method will be explained using the time charts shown in FIGS. 6a to 6e. Modulator 2
On the side, from oscillator 5 to 1/8 frequency divider 6 and 1/2 frequency divider 7
Transmit data TXD (Figure 6b) in synchronization with the transmit clock pulse TXC (Figure 6a) generated via
is input. The above-mentioned transmission clock pulse TXC and transmission data TXD are logically summed by an OR circuit 8 and input to the J and K terminals of a JK type flip-flop 9. T of JK type flip-flop 9 above
A clock pulse with twice the frequency of the transmitting clock pulse TXC is input to the terminal, and when the JK terminal is at H level, it is inverted every time this clock pulse rises, and when it is at L level, the output state is maintained regardless of this clock pulse. The output is the transmission path (modulation) data MD (Figure 6c)
Sent as . On the other hand, on the demodulator 3 side, from the transmission path (modulation) data MD, D-type flip-flops 11 and 12 operated by the clock pulse of the oscillator 10, EOR circuits 15 and 16 frequency division counters 16, and NOT circuits 18 and 16 frequency division counters 1
Receive clock pulse RXC via 7 (Figure 6d)
Further, received data RXD (FIG. 6e) is taken out via D-type flip-flops 13 and 14.

[Problem that the invention seeks to solve]

However, in the above conventional example, as shown by the broken line in the time chart of FIG. 6, the transmission path (modulation) data MD has a waveform that corresponds one-to-one to the high level 1 and low level 0 of the transmission data TXD. Therefore, the process of demodulating the received data RXD and the transmitted clock pulse RXC from the transmission line (modulated) data MD becomes complicated.
Therefore, the circuit configuration of the device becomes complicated, resulting in a problem of high cost.

An object of the present invention is to obtain a serial transmission modulation/demodulation device that can perform demodulation with a simple circuit configuration and realize cost reduction by changing the modulation method.

[Means for solving problems]

The present invention performs pulse width modulation on the transmitting side. The present invention also provides a delay means for outputting a control clock pulse by delaying a transmission clock pulse by a predetermined phase angle, and a calculation based on the following logical conditions based on the transmission clock pulse, control clock pulse, and transmission data, and outputting the result as modulated data. a logic circuit that outputs a reception clock pulse delayed by a predetermined angle from the rising edge of the modulation data obtained via a transmission path; and a sampling circuit that samples the modulation data using the reception clock pulse and outputs a demodulated signal. It is equipped with the means.

((TXC+TXCD)・TXD)+(TXC ・・） In addition, + is logical sum ・is logical product is reversed TXC is the transmit clock pulse TXCD is the control clock pulse TXD is transmission data shows.

[Effect]

In the present invention, since pulse width modulation is performed on the transmitting side, demodulation becomes easy. Further, a control clock pulse is generated by delaying the transmission clock pulse by a predetermined phase angle by a delay means, and from this control clock pulse, transmission clock pulse, and transmission data,
Pulse width modulated data is generated by the logic circuit and transmitted to the transmission path. On the other hand, on the receiving side, a receiving clock generating means generates a receiving clock pulse delayed by a predetermined angle from the rising edge of the modulated data, and a sampling means samples the modulated data based on the receiving clock pulse to produce a demodulated signal, that is, received data corresponding to the transmitted data. is demodulated.

〔Example〕

The present invention will be explained below based on the embodiments shown in FIGS. 1 and 2. Note that the same reference numerals are used for the same or equivalent parts as in the conventional example, and the explanation thereof will be omitted.

First, the method of the present invention will be explained using time charts shown in FIGS. 1a to 1f. TXCD shown in figure b changes the phase of the transmitting clock pulse TXC by 90°.
The transmission data TXD, which is a delayed control clock pulse and is sent out from the serial controller 1A or 1B in synchronization with the transmission clock pulse TXC, has the following logical conditions.

((TXC+TXCD)・TXD)+(TXC . . .) The data pulse width modulated according to the above equation is transmitted to the transmission path as transmission path (modulation) data MXD (d in the figure).

On the other hand, on the receiving side, the above transmission path (modulation) data
Receive clock pulse RXC that rises 90 degrees later than the rise of MXD and falls after a certain period of time.
(e) is generated. Furthermore, the above transmission line (modulation) data MXD is the above received clock pulse RXC.
The demodulated signal, that is, the received data RXD (f in the same figure) is demodulated.

FIG. 2 is a circuit diagram of a device according to this embodiment that implements the above method. In the figure, reference numeral 19 denotes an oscillator that oscillates at twice the frequency of the transmission clock pulse TXC, and the oscillator 19 and the 1/2 frequency divider 7 constitute a transmission clock generation means 20. 21
is a D-type flip-flop as a delay means, and the transmitting clock pulse input to the D terminal
By triggering TXC at the rising edge of a clock pulse of twice the frequency input to the T terminal, a control clock pulse TXCD delayed in phase by 90 degrees from the transmission clock pulse TXC is output.
22 is a logic circuit that realizes the logic condition shown in the above formula, and an OR circuit 23 that takes the logical sum of the transmission clock pulse TXC and the control clock pulse TXCD.
and the output of this OR circuit 23 and the serial controller 1A or 1B as a transmission data generation means.
(Fig. 4), an AND circuit 24 that performs logical product with the transmission data TXD inputted from the input terminal, a NOT circuit 25 that inverts the transmission data TXD, and the output of the NOT circuit.
It consists of an AND circuit 26 which takes the logical product of TXD, the transmission clock pulse TXC, and the inverted output of the D-type flip-flop 21, and an OR circuit 27 which takes the logical sum of the outputs of the AND circuits 24 and 26. Therefore, from the OR circuit 27, the transmission path (modulation) data MXD having the waveform shown in FIG. 1d is pulse width modulated so as to satisfy the above logical condition.
is sent to the transmission line 4. The above transmission path (modulation) data MXD is the transmission data TXD as shown in Figure 1.
The pulse width is modulated so that the duty ratio is 3:1 and 1:3 corresponding to the high level (1) and low level (0) of , respectively. On the other hand, the receiving side includes a shift register 29 operated by a clock pulse from an oscillator 28 and a D-type flip-flop 30.
Reception clock generation means 3 consisting of AND circuit 31
2 and a D-type flip-flop 33 as sampling means. Transmission line (modulation) data MXD input via the transmission line 4 is delayed by 90° by the shift register 29, and a rising signal is taken out by the D-type flip-flop 30 and the AND circuit 31. This rising signal becomes the reception clock pulse RXC (indicated by solid line P1) shown in FIG. Furthermore, the transmission line (modulation) data MXD is input to the D terminal of the D-type flip-flop 33, and the received data is demodulated as the transmit data TXD by sampling with the above-mentioned receive clock pulse RXC.
RXD is obtained.

In this way, according to this embodiment, the transmission path (modulation)
Since the data MXD is pulse width modulated in correspondence with the transmission data TXD, the demodulation process is simplified as described above and can be performed using an inexpensive circuit configuration.

FIG. 3 is a circuit diagram showing a demodulator in another embodiment of the present invention, which is improved in that the duty ratio of the received clock pulse RXC (indicated by solid line P1 in FIG. 1) is not 1:1 in the embodiment. It is something. In the figure, the transmission path (modulation) data MXD is D
The rise change is detected by the type flip-flops 34, 35 and the NAND circuit 36, and the oscillator 2
The clock pulse from 8 is input to the reset terminal of the 16 frequency division counter 37. The output of the above-mentioned 16 frequency division counter 37 is the reception clock pulse.
RXC, and this duty ratio is 1:1 as shown by the broken line P2 in FIG. 1e. received data
RXD is a D-type flip-flop 3 as in the previous embodiment.
Obtained from 3.

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a logic circuit that performs an operation based on a predetermined logical condition based on a transmission clock pulse, a control clock pulse, and transmission data and outputs it as modulation data, and a logic circuit that outputs the result as modulation data, and The demodulator includes a receiving clock generating means for detecting the rising edge of data and outputting a receiving clock pulse delayed by a predetermined angle from the rising edge, and a sampling means for sampling the modulated data using the receiving clock pulse and outputting a demodulated signal. In addition, by providing a logic circuit that takes predetermined logic conditions and pulse width modulating the transmission data, demodulation can be performed with a simple circuit configuration and cost reduction can be achieved.

[Brief explanation of drawings]

FIG. 1 is a time chart showing an embodiment of the serial transmission modulation/demodulation method according to the present invention, FIG. 2 is a circuit diagram showing the apparatus of the above embodiment, and FIG. 3 is a circuit diagram showing another embodiment of the demodulator. FIG. 4 is a block diagram showing a general configuration of a serial transmission system, and FIGS. 5 and 6 are a circuit diagram showing a conventional device and a time chart showing a method. 1A, 1B...Transmission data generation means, 20...
Transmission clock generation means, 21...delay means, 22
... logic circuit, 32 ... reception clock generating means,
33...Sampling means, TXC...Transmission clock pulse, TXD...Transmission data, MXD...Modulation data, RXC...Reception clock pulse,
TXCD...Control clock pulse, RXD...Demodulation signal. Note that the same reference numerals are used for the same or corresponding parts in the figures.

Claims (1)

[Claims] 1. The high level and low level of transmission data consisting of a combination of high level and low level signals with a constant width are pulse width modulated on the transmitting side and received via the transmission path of the modulated data. In the serial transmission modulation/demodulation device, the serial transmission modulation/demodulation device is configured to transmit the data to the transmitting side and demodulate the transmitting data to the transmitting data at the receiving side, the transmitting data generating means;
a transmitting clock generating means for generating a transmitting clock pulse of a constant period; a delay means for outputting a control clock pulse by delaying the transmitting clock pulse outputted from the transmitting clock generating means by a predetermined phase angle; and the transmitting clock pulse, the control clock pulse and the transmitting data. A logic circuit that executes calculations based on the following logical conditions and outputs it as modulated data, and a logic circuit that detects the rising edge of the modulated data obtained through the transmission line and outputs a reception clock pulse that is delayed by a predetermined angle from this rising edge. 1. A serial transmission modulation/demodulation device comprising reception clock generation means and sampling means for sampling the modulated data using the reception clock pulse and outputting a demodulated signal. ((TXC+TXCD)・TXD)+(TXC...) Note that + is logical sum, ・is logical product, and inversion. TXC is the transmit clock pulse. TXCD is the control clock pulse. TXD indicates the transmit data.