JPH09149088A - Fsk signal demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely demodulate a base band signal even when noise is in existence for a non-signal period where a communication line is not driven by an FSK(frequency shift keying) signal. SOLUTION: The demodulator detects a waveform-shaped FSK signal and is provided with a gate control means 4 providing an output of a detection signal when the FSK signal satisfies a prescribed condition, a 1st gate means 5 providing an output of the waveform-shaped FSK signal synchronously with a clock signal when an output of the gate control means 4 is in a prescribed state, and a detection means 6 demodulating the output of the 1st gate means 5 to a base band signal based on the clock signal. The 1st gate control means 5 detects it that the communication line 18 driven by the FSK signal and the FSK signal is outputted from the 1st gate means 5 and demodulated into a base band signal while the state is detected. On the other hand, a noise signal appearing when the communication line is not driven by the FSK signal is interrupted by the 1st gate means 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for demodulating an FSK modulated signal used in asynchronous digital communication, and more particularly, to reduce malfunctions due to noise on a communication line and to more reliably demodulate a baseband signal. It is the one.

[0002]

2. Description of the Related Art In digital communication, an FSK (Frequency Shift Keying) method in which a carrier frequency is changed according to digital information is widely used. In binary FSK, different frequencies f ₁ and ₁ are used for 1 and 0 signals, respectively.
f ₀ is assigned. The FSK signal can be narrowed in band by reducing harmonic components depending on the modulation method.

The receiver that receives this FSK signal is
A demodulation circuit that demodulates the SK signal into a baseband signal is required. As shown in FIG. 11, a conventional FSK signal demodulating device includes a waveform shaping circuit 3 for shaping the received FSK signal 1 and a delay detection for demodulating the output of the waveform shaping circuit 3 into an NRZ signal using a clock signal 2. The circuit 6 and the RZ signal conversion circuit 8 for converting the output of the differential detection circuit 6 into the RZ signal 11 using the clock signal 2 are provided.

The FSK signal 1 has a unit of data for 8 periods of the clock signal 2, and for example, by continuing the modulation frequency of f / 16 (f is the frequency of the clock signal 2) for 8 periods of the clock signal 2. Display 1 of the data,
Data 0 is displayed by continuing the modulation frequency of f / 8 for 8 cycles of the clock signal 2. Waveform shaping circuit 3
Waveform-shapes the FSK signal 1 as shown in FIG.

The output of the waveform shaping circuit 3 is input to the differential detection circuit 6, and the differential detection circuit 6 outputs N based on this output.
Generate an RZ signal. A timing chart of the output of the waveform shaping circuit 1 and the output of the differential detection circuit 6 is shown in FIG. The differential detection circuit 6 generates the signal (a) by synchronizing the output of the waveform shaping circuit 3 with the clock signal 2, and then delays this signal (a) for 8 cycles of the clock signal 2 to obtain the signal (b). ) Is generated and these signals (a and b) are input to an internal EX-OR gate. The output of the differential detection circuit 6 is the output of this EX-OR gate, and N
An RZ signal can be obtained. The unnecessary signal in FIG. 13 is a signal that is always generated on the principle of differential detection.

The NRZ signal output from the waveform shaping circuit 3 is input to the RZ signal conversion circuit 8, and the RZ signal conversion circuit 8 is input.
Generates an internal clock signal (c) for sampling this NRZ signal. The internal clock signal detects the first rising edge of the output of the differential detection circuit 6 to start clocking, and repeats the HIGH level at a frequency of f / 8 so that the center point of the NRZ signal can be sampled. Then, the NRZ signal when the sample clock signal (c) is at the HIGH level is sampled, and if the data is 1, it outputs LOW for four cycles of the clock signal 2, and then outputs HIGH. If the sampled data is 0, the HIGH output is maintained. In this way, the RZ signal conversion circuit 8 outputs the RZ signal 11.

Thus, the sample clock signal (c)
The reason why the NRZ signal is sampled by using is to enable correct demodulation of the RZ signal 11 even when the NRZ signal output from the differential detection circuit 6 contains jitter. To do so, it must always be possible to sample the data center of the NRZ signal with the sample clock signal (c). Therefore, the RZ signal conversion circuit 8
Adjusts the sample clock signal (c) so as to synchronize with the NRZ signal each time the changing point of the NRZ signal is detected.

In this way, the RZ signal 11 is demodulated from the FSK signal 1.

[0009]

[Problems to be Solved by the Invention] However, the conventional FSK
In the signal demodulation device, the communication line is not driven by the FSK signal, and noise occurs during a non-signal period, which causes a malfunction. FIG. 14 shows the case. When such noise is present, the waveform shaping circuit 3 outputs a signal whose waveform has been shaped including the noise. The differential detection circuit 6 is
All signals appearing at the output of the waveform shaping circuit are synchronized with the clock signal 2 to generate the signal (a), and the signal (a) is delayed by 8 cycles of the clock signal 2 to generate the signal (b), An EX-OR of these signals (a) and (b) is output. Therefore, in the output of the differential detection circuit 6, change points other than the NRZ signal appear everywhere. Therefore, R
The Z signal conversion circuit 8 will generate the sample clock signal (c) synchronized with an erroneous change point other than the NRZ signal, and as a result, the NRZ signal cannot be properly sampled.

Further, if such a state continues, the influence of noise propagates to the devices following the FSK signal demodulating device, and as a result, communication cannot be performed at all.

For this reason, this demodulator has a problem in that it often fails in reception in communication in a place where it is susceptible to external noise and in communication in a severe vehicle environment, and it becomes impossible to receive.

The present invention solves these conventional problems, and can reliably demodulate a baseband signal even when noise is present in a signalless period in which the communication line is not driven by the FSK signal. It is an object of the present invention to provide an FSK signal demodulating device that can perform stable operation without increasing the circuit scale.

[0013]

Therefore, in the present invention, F
The SK signal demodulating device monitors the waveform-shaped FSK signal and outputs a detection signal when the FSK signal satisfies a predetermined condition, and while the output of the gate control device is in a predetermined state, First gate means for outputting the waveform-shaped FSK signal to the detection means is provided.

Therefore, the gate control means detects the state where the communication line is driven by the FSK signal, and only the FSK signal during that period is demodulated. The signal appearing in the non-signal period when the communication line is not driven by the FSK signal is blocked by the first gate means, so that the influence of noise during this period can be eliminated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is an FSK demodulating device for detecting a waveform-shaped FSK signal, which monitors the waveform-shaped FSK signal.
Gate control means for outputting a detection signal when the SK signal satisfies a predetermined condition, and a first gate for outputting the waveform-shaped FSK signal in synchronization with the clock signal while the output of the gate control means is in a predetermined state. Means and demodulation means for demodulating the output of the first gate means into a baseband signal by a clock signal, wherein the communication line is FSK.
The gate control means detects the state of being driven by a signal, and the FSK signal while this state is detected is output from the first gate means and demodulated to a baseband signal. On the other hand, the signal appearing when the communication line is not driven by the FSK signal is blocked by the first gate means.

According to a second aspect of the present invention, the FSK signal demodulating device further comprises an RZ signal converting means for converting the output of the detecting means into an RZ signal with a clock signal, and an output of the RZ signal converting means with a clock signal. The delay means for delaying the output and the second gate means for controlling and outputting the output of the delay means by the output of the gate control means are provided, and an erroneous signal generated at the end stage of the conversion into the RZ signal. Can be removed by the second gate means.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FSK of the first embodiment
As shown in FIG. 1, the signal demodulating device includes a waveform shaping circuit 3 for shaping the received FSK signal 1 and a waveform shaping circuit 3.
The gate control circuit 4 that determines the drive start of the FSK signal on the communication line based on the arrangement of the data output from the and outputs the detection signal, and the waveform shaping after the detection signal is output from the gate control circuit 4 The first gate circuit 5 that outputs the output of the circuit 3 in synchronization with the clock signal 2 and the output of the first gate circuit 5 with the clock signal 2 as the NRZ signal 7
And a differential detection circuit 6 for demodulating

The FSK signal 1 has one cycle of data for eight cycles of the clock signal 2, the modulation frequency for data 1 is f / 16 (f is the frequency of clock signal 2), and the modulation frequency for data 0 is f. / 8. Data 1 is assigned to the demodulated NRZ signal 7 when the output signal is HIGH, and data 0 is assigned when the output signal is LOW.

Next, the operation of this FSK signal demodulating device will be described. 2 and 3 show the timing of each unit of this demodulation device.

First, when the FSK signal 1 is input to the waveform shaping circuit 3, the waveform shaping circuit 3 shapes the signal including noise, as shown in FIGS. 2 and 3, and outputs the waveform shaping circuit 3. Is output.

The output of the waveform shaping circuit 3 is input to the gate control circuit 4. The gate control circuit 4 samples the output of the waveform shaping circuit 3 with the clock signal 2, and the sampled series of data satisfies the condition (d) or (e) shown in FIG.
, That is, when the cycle of the clock signal 2 is a unit, LOW continues for 4 cycles or more, and then HIGH changes to 4
When it continues for four cycles, or after HIGH continues for four cycles or more and LOW continues for four cycles, a HIGH level detection signal is output to the first gate circuit 5. At this time,
As will be described later, the gate control circuit 4 allows the first gate circuit 5 to output the FSK signal pulse in a complete form.
Adjust the output timing of the detection signal.

The first gate circuit 5 is, for example, a 2-input AN.
It is composed of a D gate and a D flip-flop operated by the clock signal 2. As shown in FIG. 5, the two-input AND gate inputs the output of the waveform shaping circuit 3 to one side and the output of the gate control circuit 4 to the other side. And
The output of the 2-input AND gate is input to the D flip-flop operated by the clock signal 2, and the output of the D flip-flop is used as the output of the first gate circuit 5.

Therefore, the first gate circuit 5 has the same structure as that shown in FIGS.
As shown in, the output of the waveform shaping circuit 3 when the output of the gate control circuit 4 is in the HIGH state is output in synchronization with the clock signal 2. If the output of the gate control circuit 4 is LOW, the output of the first gate circuit 5 is LOW regardless of the output of the waveform shaping circuit 3. Therefore, the waveform shaping circuit 3
The effect of noise contained in the output is cut off here. 2 is a timing chart when the condition (d) is detected, and FIG. 3 is a timing chart when the condition (e) is detected.

The output of the first gate circuit 5 is the delay detection circuit 6
The differential detection circuit 6 generates the NRZ signal by the procedure described in the conventional example.

In the case of FIG. 2, the condition (d) in FIG. 4 is detected and the output of the gate control circuit 4 is immediately set to HI.
When it is set to GH, as shown in FIG. 5, the AND gate output of the first gate circuit 5 becomes HIG from the middle of the FSK signal pulse.
The output signal of the first gate circuit 5 becomes H, and a part of the HIGH pulse of the waveform-shaped FSK signal is deleted. In order to avoid such a situation, the gate control circuit 4
When the condition (d) is detected, operates so that the detection signal becomes HIGH after the output of the waveform shaping circuit 3 falls next.

On the other hand, when the condition (e) in FIG. 4 is detected, as shown in FIG. 6, even if the output signal of the gate control circuit 4 is immediately set to HIGH, a part of the pulse of the waveform-shaped FSK signal is detected. There is no shaving. Therefore, in this case, the gate control circuit 4 sets the detection signal output to HIGH before the output of the waveform shaping circuit 3 next rises to HIGH.

However, in this FSK signal demodulating device, as is clear from FIGS. 2 and 3, at the time of demodulating the NRZ signal 7, at least the first 2-bit data 1 of the transmitted FSK signal 1 is removed. Therefore, this FSK
When the signal demodulating device is used, the transmitting side adds 2 or more bits of data 1 as a start bit string to the beginning of the data to be transmitted and transmits the data.

The NRZ signal 7 demodulated in this way is
Even if there is noise on the communication line before operating with the FSK signal, the noise does not affect the NRZ signal 7. Further, since the NRZ signal 7 does not include a change point other than the NRZ signal, even if the NRZ signal 7 is subjected to signal processing, there is no propagation of the influence of noise to the demodulators and thereafter.

In the first embodiment, the basic cycle of the received data is 8 cycles of the clock signal and the modulation frequency of the FSK signal is 1/16 and 1/8 of the frequency of the clock signal. The fundamental period can be between m periods of the clock signal, where m is an arbitrary integer, and the FSK modulation frequency is x, y where x is an arbitrary integer.
It can be set to f / 2m, yf / 2m (x ≠ y, f: clock signal frequency).

The conditions for determining that the communication line is driven by the FSK signal in the gate control circuit 4 are not limited to those shown in FIG. Further, the first gate circuit 5 may be configured by other than the 2-input AND gate and the D flip-flop. The relationship that the first gate circuit 5 blocks the waveform-shaped FSK signal when the output of the gate control circuit 4 is LOW is not fixed, and the gate control circuit 4 may be adjusted according to the configuration of the first gate circuit 5. You can change the output of.

The differential detection circuit 6 may use a method other than the differential detection, and may demodulate a baseband signal other than the NRZ signal. Also, the waveform shaping circuit 3
The output of the first gate circuit 5 when the output of 1 is cut off does not have to be LOW as long as no hazard is output and some of the pulses to be output from the first gate circuit 5 are not cut.

Further, in this embodiment, the low frequency of the FSK modulation frequency is assigned to data 1, but it may be assigned to either data 1 or data 0.

(Second Embodiment) FSK of the Second Embodiment
The signal demodulating device is configured to demodulate the RZ signal and eliminate an erroneous signal generated at the end of the RZ signal demodulation.

As shown in FIG. 7, this device uses the gate control circuit 4 for detecting the end of drive and the output of the delay detection circuit 6 for detecting the drive end of the FSK signal on the communication line by using the clock signal 2. The RZ signal conversion circuit 8 for converting into a signal, the delay circuit 9 for delaying the output of the RZ signal conversion circuit 8, and the detection signal of the gate control circuit 4 are HIG.
The second gate circuit 10 outputs the output of the delay circuit 9 during H as the RZ signal 11. Other configurations are first
Of the apparatus (FIG. 1) of the embodiment of FIG.

Next, the operation of this FSK signal demodulating device will be described. FIG. 8 shows the timing of each part when the demodulator detects the condition (e) in FIG. The FSK signal 1 has the same conditions as in the first embodiment. As for the demodulated RZ signal 11, a signal for switching the output signal to HIGH after the output signal once becomes LOW is allocated to the data 1, and a signal for maintaining the HIGH signal without switching the output signal is allocated to the data 0. To do.
Further, the no-signal period of the FSK signal 1 corresponds to the data 0 of the RZ signal 11.

NRZ signal 7 demodulated by the delay detection circuit 6
Is input to the RZ signal conversion circuit 8, the RZ signal conversion circuit 8 generates a sample clock signal (c) at a frequency of f / 8, as in the conventional circuit, and the sample clock signal (c) is HIGH. , The NRZ signal is sampled. Then, if the sampled result is data 1, it returns to HIGH after outputting LOW for four cycles of the clock signal 2, and if the sampled result is data 0, H
By maintaining the IGH output, and by doing so, the RZ signal
Output 11 prototypes.

The output of the RZ signal conversion circuit 8 is the delay circuit 9
It is input to the second gate circuit 10 after being delayed by 4 bits.

The second gate circuit 10 is, for example, a 2-input OR.
The output of the delay circuit 9 is input to one of the two-input OR gates, and the output of the gate control circuit 4 is inverted and input to the other. Therefore, when the detection signal of the gate control circuit 4 is HIGH, the second gate circuit 10
Therefore, the output of the delay circuit 9 is directly output as the RZ signal 11.

Next, the operation of the FSK signal demodulating device when communication is completed will be described. As shown in FIG. 9, when communication is completed, a waveform shaping circuit 3 that shapes the waveform of the FSK signal 1
The output of is in the steady state during the no signal period. As shown in FIG. 10, the gate control circuit 4 outputs HIGH or LO for the output of the waveform shaping circuit 3 for 13 cycles of the clock signal 2.
When W is maintained, this steady state is detected and the detection signal is changed to LOW.

In response to this, the output of the first gate circuit 5 becomes LOW. Further, since the detection signal is inverted and input to the second gate circuit 10 composed of a 2-input OR gate,
It becomes IGH.

When the output of the waveform shaping circuit 3 reaches the steady state satisfying the steady state detection condition shown in FIG. 10, an unnecessary signal is always generated at the end of the NRZ signal output from the differential detection circuit 6. The RZ signal conversion circuit 8 causes a malfunction due to this unnecessary signal. In order to prevent the influence of the malfunction output of the RZ signal conversion circuit 8, first, the transmitting side transmits the data 0, for example, 4 bits after the data to be transmitted, and delays the error signal generation time to be output to the RZ signal conversion circuit 8. Further, the delay circuit 9 delays the output of the RZ signal conversion circuit 8 by the communication time of 4 bits. In this way, the gate control circuit 4 is activated at the time when the error signal output by the RZ signal conversion circuit 8 causing the malfunction is input to the second gate circuit 10.
Since the inverted output of is already HIGH, the erroneous signal is masked, and the influence of the erroneous operation does not appear on the RZ signal 11.

The first gate circuit 5 and the second gate circuit
Since both 10 block each input signal, FS
The influence of noise on the communication line when not driven by the K signal does not propagate to the demodulated RZ signal 11.

Therefore, the demodulated RZ signal 11 does not include the influence of noise before and after driving the communication line with the FSK signal (including the unnecessary signal output from the differential detection circuit 6).

The condition under which the gate control circuit 4 judges that the communication has been completed and the communication line is in the steady state during the no-signal period is not affected by the unnecessary signal output from the differential detection circuit 6 as shown in FIG. It may not be as shown in 10. Further, the delay time of the delay circuit 9 is set to a time other than the communication time of 4 bits unless the output of the second gate circuit 10 is affected by an unnecessary signal of the output of the delay detection circuit 6 or noise on the communication line. It is also possible. In this case, it is set to an appropriate delay time that is 1 / f times the shaping of the clock signal 2.

Further, the second gate circuit 10 performs RZ for demodulation.
If the hazard is not output by the signal and the output of the second gate circuit 10 is not affected by the unnecessary signal of the output of the differential detection circuit 6, a configuration other than the 2-input OR gate can be adopted.

When the output of the RZ signal conversion circuit 8 is cut off, the output of the second gate circuit 10 does not output a hazard, and if the pulse to be output from the second gate circuit 10 is not cut, the output is HIGH. It doesn't have to be. Further, the frequency of the sample clock signal (c) for sampling the NRZ signal inside the RZ signal conversion circuit 8 may not be f / 8 as long as the NRZ signal can be converted into the prototype of the RZ signal.

[0048]

As is apparent from the above description, the FSK signal demodulating device of the present invention can convert the clock signal from the FSK signal to the clock signal even if the communication line in the non-signal state not driven by the FSK signal is affected by noise. It is possible to correctly demodulate the baseband signal synchronized with. At the time of this demodulation, the operation of the device other than the waveform shaping device is performed in synchronization with the clock signal, so that the demodulation operation is stable and the occurrence of delay can be avoided. Furthermore, because the circuit configuration is simple,
There is no need to increase the circuit scale.

Further, the logic circuit portion of the circuit of the present invention is
Even when the FSK signal demodulation circuit of the present invention operates in synchronization with a clock signal even when it is programmed and used in a logic circuit such as a GA that can be freely written by a user, it depends on the delay peculiar to each device. Rarely. Therefore, it is not necessary to change the circuit configuration, any device can be used, and the performance of the written device can be maximized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an FSK signal demodulation device showing a first embodiment of the present invention,

FIG. 2 shows the condition (d) in FIG. 4 for the FSK signal demodulating device.
Timing chart showing the operation when the

FIG. 3 shows the condition (e) in FIG.
Timing chart showing the operation when the

FIG. 4 is a diagram showing detection conditions of a gate control circuit of the FSK signal demodulation device,

FIG. 5 is a diagram for explaining the timing when the gate control circuit of the FSK signal demodulating device detects the condition (d) and outputs a detection signal;

FIG. 6 is a diagram for explaining the timing when the gate control circuit of the FSK signal demodulating device detects the condition (e) and outputs a detection signal;

FIG. 7 is a block diagram of an FSK signal demodulation device showing a second embodiment of the present invention,

FIG. 8 is a timing chart showing the operation of the FSK signal demodulation device at the start of demodulation;

FIG. 9 is a timing chart showing an operation at the end of demodulation of the FSK signal demodulating device;

FIG. 10 is a diagram showing conditions under which a gate control circuit of the FSK signal demodulation device detects a steady state of a communication line;

FIG. 11 is a block diagram showing a configuration of a conventional FSK signal demodulation device,

FIG. 12 is a waveform diagram showing an input signal and an output signal to a waveform shaping circuit of the FSK signal demodulating device,

FIG. 13 is a timing chart showing the operation of the conventional FSK signal demodulation device when the communication line is not affected by noise during a no-signal period,

FIG. 14 is a timing chart showing an operation of the conventional FSK signal demodulation device when a communication line is affected by noise during a no-signal period.

[Explanation of symbols]

 1 FSK signal 2 clock signal 3 waveform shaping circuit 4 gate control circuit 5 first gate circuit 6 delay detection circuit 7 NRZ signal 8 RZ signal conversion circuit 9 delay circuit 10 second gate circuit 11 RZ signal

Claims (2)

[Claims] 1. A gate control for monitoring a waveform-shaped FSK signal in an FSK demodulator for detecting a waveform-shaped frequency shift keying (FSK) signal and outputting a detection signal when the FSK signal satisfies a predetermined condition. Means, first gate means for outputting the waveform-shaped FSK signal in synchronization with a clock signal while the output of the gate control means is in a predetermined state, and the output of the first gate means for the clock signal An FSK signal demodulating device, comprising: 2. An RZ signal conversion means for converting the output of the detection means into an RZ signal with the clock signal, a delay means for delaying and outputting the output of the RZ signal conversion means with the clock signal, and the delay means. 2. The FSK signal demodulation device according to claim 1, further comprising: second gate means for controlling and outputting the output of the gate control means by the output of the gate control means.