SU1559417A1 - Device for reception of messages - Google Patents

Abstract

This invention relates to radio. The purpose of the invention is to increase the reliability of receiving discrete messages. The device contains a receiver 1, a doubler 2 frequencies, demodulators 3 and 15, elements AND 4, 9, 11 and 12, element OR 5, a driver of 6 message symbols, a sync block 7, a driver of 8 clock pulses, an inverter 10 and a demodulation unit 13, which consists of a phase shifter 14 and a demodulator 15. To increase the reliability of receiving discrete messages, shift registers 16 and 19, switch 17 and demodulator 18 are entered into demodulation unit 13, with which the symbols of the second information signal are correctly decoded. 2 Il.

Description

one

(21) 4378732 / 24-09

(22) 02/10/88

(46) 04.23.90. Bul Number 15

(71) Voronezh Polytechnic Institute

(72) V.I. Ledovskikh

(53) 621.396.6 (088.8)

(56) USSR Author's Certificate No. 1378075, cl. H 04 L 5/02, 1986.

A.M. and others. Phase difference modulation. - M .: Svy, 1967, p. 15, ris.1.1.

(54) DEVICE FOR RECEIVING DISCRETE MESSAGES

(57) The invention relates to radio. The purpose of the invention is to increase

reliability of receiving discrete messages. The device contains receiver 1, frequency doubler 2, demodulators 3 and 15, E-4,9,11 and 12, e-OR OR 5, driver 6 message symbols, sync block 7, driver 8 sync pulses, inverter 10 and a demodulation unit 13, which consists of a phase shifter 14 and a demodulator 15. To increase the reliability of receiving discrete messages, shift registers 16 and 19, a switch 17 and a demodulator 18 are entered into demodulation unit 13, with which the correct information decoding symbols signal. 2 Il.

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The invention relates to radio and radio communications and can be used in the transmission of discrete messages over wired, radio, radio relay and space communication lines.

The purpose of the invention is to increase the reliability of receiving discrete messages.

Fig. 1 shows a block diagram of a device for receiving discrete messages; Figure 2 shows signal plots explaining the operation of the device.

A device for receiving discrete messages contains a frequency doubler receiver 2, a first demodulator 3, the first element AND 4, an element OR 5 and a generator of 6 message symbols, a sync block 7, a generator of 8 clock pulses, a second element I. 9, an inverter 50, a third element II, and the fourth element is AND 12, the demodulation unit 13, which contains the phase shifter 14, the second demodulator 15, the first shift register 16, the switch 17, the third demodulator 18 and the second shift register 19.

The device works as follows.

The output signal of the receiver with phase difference manipulation of the first (Fig. 2a) and second (Fig. 26) signals, respectively, with the clock frequencies FT / K and (K-1) is FT / K (received in Fig. 2) after doubling in frequency and filtering in the frequency doubler 2 with the FT / K band is input to the first demodulator 3 clocked by the output pulses of the sync block 7 with the frequency FT / K (FIG. 2c) and to the inputs of the phase shifter 14 and the third demodulator 18, B first demodulator 3, which is a demodulator of PRM signals for twice the carrier frequency, is allocated the first information FT / K clock signal (FIG. 2d) "In phase shifter 14 each time a pulse FT contact frequency is applied, the initial phase of the input signal changes by JT / 2 relative to the signal phase at the previous clock interval. As a result, one of the demodulators (15 or 18) on any clock period, the time interval equal to K-T, a signal acts without an additional PDM with respect to the signal on the previous clock interval of the same duration and according to it i the characters of the second information si are correctly decoded Nala. Moreover, if this transmission interval corresponds to the symbol 1 of the first information signal, then the decoding will be correct in the second demodulator 15,

Q, otherwise, in the third demodulator 18. The output signals of demodulators 15 and 18 (with the temporal position of the signal in Fig. 2e) are delayed by two clock intervals of frequency

5 (K-1) -FT / K in the first 16 and second 19 shift registers, and the received signals (as shown in FIG. 2g) arrive at the inputs of the switch 17. The characters of the first information signal from the output of the first demodulator arrive at the control input of the switch. 3 (fig, 2d).

With the action of symbol 1, the output of the first register 16 is transmitted to the switch output with a delay

5 for one clock frequency (K - 1) -FT / K, and under the action of the symbol O - the output signal of the second register 19 with the same delay. Thus, at the output of the first demodulator 3, the first information signal acts, and at the output of the switch 17 - the second information signal (FIG. 2h). The first element And 4, the element OR 5 and the driver 6 messages, as well as the second element And 9, the inverter 10, the third element

$ And 11 and the fourth element And 12 serve to combine the two information signals into a single signal with a clock frequency FT,

40

Claims (1)

Invention Formula A device for receiving discrete messages containing a serially connected linear receiving path, a frequency doubler, a first demodulator, a first AND element, an OR element, and a message character generator connected in series sync block, sync pulse shaper, second AND element, inverter, third AND element, and fourth AND element, the output of which is connected to the second input of the OR element, the sync block input is connected to the synchro output of the linear receiving path, which are connected in series with the synchro sync input of the sync terminal block, and the second demodulator, - tact515 the first input of which is connected to the first output of the sync pulse generator, the sync block output is connected to the clock input of the first demodulator, the second output of the sync pulse generator is connected to the second input of the third element And the clock input of the message character generator, the output of the second element And is connected to the second input of the first element And, characterized in that, in order to increase the reliability of reception, serially connected first shift register and switch, and serially connected thirds are entered th demodulator and second shift register, with the phase inputs a jl in 1 .2131 I B 1 G D1 8 jl PJ e i 2J3 iҐ Iffl7 I g I UN 41 - 0 76 the rotator and the third demodulator are connected to the information output of the linear receiving path, the input of the first shift register is connected to the output of the second demodulator, the output of the second shift register is connected to the second input of the switch, the control input of the switch is connected to the output of the first demodulator, and its output is connected to the second input of the fourth And element, the clock inputs of the third demodulator, the switch of the first and second shift registers are connected to the tactile input of the second demodulator, the second output of the driver, sync pulses connected to the second input of the second element And .. five Jl P p p p p p p p J2 f 2 I 3 I 9 I b I 7L g z i i 6 i FIG. 2