JPH04111291A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To speedily invert a cell digit by providing a means to make a cell digit and a sense amplifier digit inactive when a sense amplifier is activated and to make them active in writing. CONSTITUTION:A write control signal 18 from a write control circuit 20 and a cell digit/sense amplifier digit separating signal 4 from a sense operation control circuit 13 are impressed through an OR gate 21 to a transfer gate 22. In this case, the cell digit/sense amplifier digit separating signal is turned to a high level when the write control signal 18 is turned to the high level. Namely, in writing, the cell digit/sense amplifier digit separating signal is turned to the high level, and a write driver 17 directly inverts not only a sense amplifier digit 7 but also a cell digit 6. Thus, time for writing can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to the operation of a cell information difference potential amplification circuit.

[Conventional technology]

As shown in FIG. 2, an amplification circuit for the cell information difference potential generated in the digits of a conventional semiconductor memory device (hereinafter referred to as a sense circuit) includes a Pch flip-flop 8, a sense amplifier digit signal feedback Nch flip-flop, and a sense amplifier. It consists of 10.

The sense operation control circuit 13 has a P channel (ch
) Flip-flop activation signal 1. Word line (decoder) activation signal 12. Sense amplifier digit signal feedback Nc
h flip-flop activation signal 3. Cell digital/sensor digital/separate signal 4. A sense amplifier activation signal 53 is generated. Write control circuit 20 generates write control signal 18 . Data amplifier 16. Write driver 17 is I,10 bus 14
It is connected to the. Row decoder 11 is connected to a word line. Column decoder 15 is connected to the gates of transistors in column switch 19 .

Next, the operation will be explained.

First, cell digit 6, sense amplifier digit 7, Pc
h flip-flop activation signal 1. Sense amplifier digit signal feedback Nch flip 20 knob activation signal 3 is 1/
2■ CC level.

First, word line 2 is selected, cell information is output to cell digit 6 and sense amplifier digit 7, and when a sufficient difference in signal amount occurs between the pair of digits, sense amplifier activation signal 5 is activated. Make it. At this time, the cell digital ramy sense amplifier digit limit signal 4 is changed from high level to low level. This is to increase the amplification speed of the sense amplifier digit 7.

(7) In order to transmit the low level to the cell digital signals 1 and 6, the sense amplifier digital signal 4m (return NCI) flip-flop activation signal 3 is also activated.

After that, in order to tell the cell that it is a hide bell, a Pch flip-flop activation signal 1f! : Activate.

This completes the sensing operation. When writing data to a cell, one column switch is opened by the column decode 15, the write control signal 18 becomes high level, the write driver 17 is activated, the sense amplifier digit 73 is inverted, and the sense amplifier digit signal is returned. A flip roller 79 inverts the cell digit 6.

The above is the operation of the conventional sense circuit.

[Problem to be solved by the invention]

However, when writing data, the conventional sense circuit uses the sense amplifier 1 to signal 4ffii4Nch frisopflotz 79 to write Pch frisobflom 8t! There was a problem in that it took a long time to flip the Cell Digit 1-63, and the cell digital 1-63 had to be inverted.

The purpose of the present invention is to provide a semiconductor memory device which solves the above-mentioned problems and can be quickly inverted with cell digits.

[Means to solve the problem]

Another aspect of the present invention is a semiconductor memory device in which a first flip-flop, a pair of cell digits, a second flip-flop, a transfer gate, and a pair of sense amplifier digits are connected in cascade. - The present invention is characterized in that means is provided for deactivating the sense amplifier digit and the sense amplifier digit when the sense amplifier is activated, and activating it during writing.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

In FIG. 1, in this embodiment, the write control signal 18 from the write control circuit ii' 820 and the sense operation control circuit F! cell digi 1 from 813
~・OR gate 2 with sense amplifier digital signal 4
1 to the transfer gate 22.

The other circuit blocks are the same as those shown in FIG. Pch
The flip-flop 8 consists of a pair of P-channel MOS transistors, each with its drain connected to the cell digit 6.
, their sources are commonly connected, and their gates are connected to the drains of each other. Nch flip-flop 9 also includes a pair of N-channel MOS transistors.

The cell digit sense amplifier digit separation signal 4 becomes high level when the write control signal 18 becomes high level.

Until the sensing operation is completed, it is the same as the conventional sense circuit, but during writing, the sense digit/sense amplifier separation signal 4 becomes high level, and the write driver 17 directly inverts not only the sense amplifier digits yl~7 but also the cell digit 6. let

In this way, in this embodiment, one cell digit 6 of the paired digits (hereinafter referred to as cell digits 11-) to which the dynamic/cell is connected is connected to the other cell digit 1-1.
Connect the train of Pch transistors with G connected to Gate 1, make the same configuration for the other cell digit 6, connect their sources to each other, and connect the other sense amplifier to those paired cell digits. (hereinafter referred to as sense amplifier digit 7) is connected to the gate of the Nch transistor train, and the other sense amplifier digit 7 and cell digit have the same configuration. A transfer gate 22 is provided which connects the sources to each other, deactivates the cell digit 6 and sense amplifier digit 7 when the sense amplifier is activated, and activates them during writing.

〔Effect of the invention〕

As explained above, in the present invention, the cell digit, sense amplifier digital, and 11-minute signals are set to high level when a write error occurs, so the write driver can directly invert the cell digit to h, and the writing time is This has the effect that it only needs to be short.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor memory device. 1...Pch flip-flop activation signal, 2...Word line, 3...Sense amplifier digit signal feedback Nch
Flip-flop activation signal, 4...Cell digit
Sense amplifier digit l~separation signal, 5... sense amplifier activation signal, 6... cell digit, 7... sense amplifier digit, 8... Pch flip-flop, 9
...Sense amplifier digit signal feedback Nch flip-flop, 10...Sense amplifier, 11...Row decoder, 12...Word line (decoder) activation signal, 1
3...Sense operation control circuit, 14...l,
-'Q)<S, 15... Column decoder, 1G.
...Data amplifier, 17...Harmful driver 1S
...Write control signal, one ...Column switch, 20...-Write control circuit, 21.
...OR gate.

Claims (1)

[Claims] a first flip-flop; a pair of cell digits;
In a semiconductor memory device in which a second flip-flop, a transfer gate, and a pair of sense amplifier digits are connected in series, the cell digit and the sense amplifier digit are inactivated when the sense amplifier is activated, and activated during writing. 1. A semiconductor memory device, characterized in that the semiconductor memory device is provided with means for converting the data into digitized data.