JPH03105787A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH03105787A JPH03105787A JP1244245A JP24424589A JPH03105787A JP H03105787 A JPH03105787 A JP H03105787A JP 1244245 A JP1244245 A JP 1244245A JP 24424589 A JP24424589 A JP 24424589A JP H03105787 A JPH03105787 A JP H03105787A
- Authority
- JP
- Japan
- Prior art keywords
- potential difference
- circuit
- data
- information
- transmission lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 230000003321 amplification Effects 0.000 claims abstract description 21
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 21
- 230000005540 biological transmission Effects 0.000 claims abstract description 20
- 238000001514 detection method Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 1
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特に半導体記憶装置の
センス増幅器のように、２節点間の微小電位差を増幅す
る回路を有する半導体集積回路に淘する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a circuit for amplifying a minute potential difference between two nodes, such as a sense amplifier of a semiconductor memory device. do.
従来のこの種の半導体集積回路について、ダイナミック
メモリを例にとシ説明する．
第３図は従来のこの種の半導体集積回路の一例の回路図
、第４図はその各部信号のタイムチャートである。This type of conventional semiconductor integrated circuit will be explained using dynamic memory as an example. FIG. 3 is a circuit diagram of an example of a conventional semiconductor integrated circuit of this type, and FIG. 4 is a time chart of signals of various parts thereof.
この回路は、対をなすディジット線ＤＬＩ，ＤＬ２、ワ
ード線ＷＬＩ，ＷＬ２、トランジスタ１個と容量１個か
らなるメモリセルｌＡｅｌＢ％センス増幅器４、Ｉ／Ｏ
スイッチ回路５、制御回路２Ａ１遅延回路７Ａ＋７Ｂ及
びセンス増幅器駆動回路３とで構成され、メモリセルＩ
ＡＩＩＢの情報によってディジット線ＤＬＩ，ＤＬ２間
に生じた微小電位差をセンス増幅器４で増幅し、この情
報をＩ／Ｏスイクチ回路５ｔ介してＩ／ＯバスＩＯＢｔ
，ＩＯＢ２Ｋ出力する．
この一連の動作を制御する場合、ディジット線ＤＬＩ，
ＤＬ２の倣小電位差の増幅の完了を示す指標は無く、工
／０スイッチ回路５の開閉には、予め推測した増幅時間
分の遅延量をもつ遅延回路’ＩＡ，’ＩＢ’？：用いて
、増幅の間、Ｉ／Ｏスイッチ制御信号を遅延させるのが
通例てあった．ｔた、遅延回路７Ａｔ７Ｂは、製造ばら
つきや温度変化等で遅延時間が変化するので、最悪条件
で算出した値を用い、更に余裕を持たせるのが普通であ
る。This circuit consists of a pair of digit lines DLI and DL2, word lines WLI and WL2, a memory cell lAelB% sense amplifier 4 consisting of one transistor and one capacitor, and an I/O
It is composed of a switch circuit 5, a control circuit 2A, a delay circuit 7A+7B, and a sense amplifier drive circuit 3.
The minute potential difference generated between the digit lines DLI and DL2 based on the information on AIIB is amplified by the sense amplifier 4, and this information is sent to the I/O bus IOBt via the I/O switch circuit 5t.
, output IOB2K. When controlling this series of operations, the digit lines DLI,
There is no indicator indicating the completion of amplification of the small potential difference of DL2, and the opening/closing of the work/0 switch circuit 5 requires delay circuits 'IA, 'IB' with a delay amount corresponding to the amplification time estimated in advance. : was commonly used to delay I/O switch control signals during amplification. Furthermore, since the delay time of the delay circuit 7At7B changes due to manufacturing variations, temperature changes, etc., it is common to use a value calculated under the worst conditions and provide additional margin.
〔発明が解決しようとする１１１！）
上述した従来の半導体集積回路は、センス増幅器４の増
幅に要する時間を推測して遅延回路７Ａ，７．によシ所
定の時間遅延させてＩ／Ｏスイッチ回路５の開閉を制御
する構成となっているので、増幅Ｋｌ！する時間の厳密
な算出が峻しく、また遅延回路７Ａ，７，の遅延時間が
設定出来た場合でも、素子自体の製造ばらつきや、温度
の影響によ多、電位差増幅の途中に次の制御動作信号が
発生して増幅途中のレベルを伝達したシして正確な情報
を伝達することができないという欠点がある。[111 that the invention attempts to solve! ) The conventional semiconductor integrated circuit described above estimates the time required for amplification by the sense amplifier 4 and then uses the delay circuits 7A, 7 . Since the configuration is such that the opening and closing of the I/O switch circuit 5 is controlled with a predetermined delay, the amplification Kl! Even if the delay time of the delay circuits 7A, 7 can be set, the next control operation may not be performed during the potential difference amplification due to manufacturing variations in the elements themselves or the influence of temperature. This method has the disadvantage that accurate information cannot be transmitted because the signal is generated and the level is transmitted while it is being amplified.
また、制御動作信号の発生を遅らせる為に遅延回路７Ａ
ｔ７Ｂに充分な余裕を持たせると動作時間が冗長となシ
、迅速かつ確実な動作を行なう回路の設計が難しいとい
う欠点がある。In addition, a delay circuit 7A is provided to delay the generation of the control operation signal.
If a sufficient margin is provided for t7B, the operating time becomes redundant, and it is difficult to design a circuit that operates quickly and reliably.
本発明の目的は、迅速かつ正確に情報の伝達を行うこと
ができる半導体集積回路を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit that can transmit information quickly and accurately.
本発明の半導体集積回路は、対をなす第１及び＃！２の
情報源回路と、これら第１及び第２の情報源回路からの
情報をそれぞれ伝達する対をなす第１及び第２の情報伝
達線と、前記第１及び第２の情報伝達線に伝達された情
報の微小電位差を所定のレベルに増幅するセンス増幅器
と、前記ｗＩ１及び第２の情報伝達線の情報の微小電位
差が所定のレベル１で増幅されたか否かを検知する電位
差増幅検知回路と、この電位差増幅検知回路の出力信号
に従ってスイッチ制御信号を出力する制御回路と、前記
スイッナ制御信号に従って前記第１及び＃！２の情報伝
達線の情報を出力端へ伝達制御するスイッチ回路とを有
している．
｛実施例〕
次に、本発明の実施例について図面を参照して説明する
。The semiconductor integrated circuit of the present invention comprises a pair of first and #! two information source circuits, a pair of first and second information transmission lines that transmit information from these first and second information source circuits, respectively, and transmission to the first and second information transmission lines; a sense amplifier that amplifies the minute potential difference of the information transmitted to a predetermined level; and a potential difference amplification detection circuit that detects whether the minute potential difference of the information between the wI1 and the second information transmission line has been amplified to a predetermined level 1. , a control circuit that outputs a switch control signal according to the output signal of the potential difference amplification detection circuit, and the first and #! It has a switch circuit that controls the transmission of information from the second information transmission line to the output terminal. {Example} Next, an example of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す回路図である．この実
施例は、本発明を半導体記憶装置に適用したものであシ
、対をなす第１及び第２の情＠源回路であるメモリセル
ＩＡ，ＩＢと、これらメモリセルＩＡ，１，ｆ：選択す
るワード線ＷＬＩ，ＷＬ２と、選択されたこれらメモリ
セルＩＡ，１Ｂからの情報をそれぞれ伝達する対をなす
第１及び第２の情報伝達線であるディジット線ＤＬＩ，
ＤＬ２と、ディジット線ＤＬＩ，ＤＬ２に伝達された情
報の微小電位差を制御信号ＳＥＩ，ＳＥ２に従って所定
のレベル筐で増幅するセンス増幅器４と、トランジスタ
Ｑ５，Ｑ６ｔ−備えディジット線ＤＬＩ，ＤＬＺ間の電
位差を検出する電位差検出部６１，及びレベル判定回路
６２を含み、ディジタル線ＤＬ１，ＤＬＺ間の微小電位
差が所定のレベルまで増幅されたか否かを検知する電位
差増幅検知回路６と、センス増幅器駆動回路３を介して
制御信号８Ｅｔ，８Ｅ２ｆ：出力しセンス増幅器４ｔ−
制御すると共に、電位差増幅回路６の出力信号に従って
スイッチ制御信号を出力する制御回路２と、この制御回
路２からのスイッチ制御信号に従ってディジット線ＤＬ
ｌ，ＤＬ２の情報ｔ−Ｉ／ＯバスＩＯＢＩ，ＩＯＢ２へ
伝達制御するＩ／Ｏスイッチ回路５とを有する構或とな
っている．
次に、この実施例の動作について、トランジスタＱ５
１ ＱｓをＮｆｉＭＯＳＦＥＴとして説明する。FIG. 1 is a circuit diagram showing one embodiment of the present invention. This embodiment applies the present invention to a semiconductor memory device, and includes memory cells IA, IB, which are a pair of first and second information source circuits, and these memory cells IA, 1, f: Selected word lines WLI, WL2, and digit lines DLI, which are a pair of first and second information transmission lines that transmit information from the selected memory cells IA, 1B, respectively.
DL2 and the sense amplifier 4 which amplifies the minute potential difference of the information transmitted to the digit lines DLI, DL2 to a predetermined level according to the control signals SEI, SE2, and the digit lines DLI, DLZ equipped with transistors Q5, Q6t. A potential difference amplification detection circuit 6 includes a potential difference detection section 61 for detecting and a level determination circuit 62 and detects whether a minute potential difference between the digital lines DL1 and DLZ has been amplified to a predetermined level, and a sense amplifier drive circuit 3. Control signals 8Et, 8E2f are output through the sense amplifier 4t-
A control circuit 2 which controls the switch control signal and outputs a switch control signal according to the output signal of the potential difference amplifier circuit 6, and a digit line DL according to the switch control signal from the control circuit 2.
1, DL2 information t-I/O switch circuit 5 for controlling transmission to I/O buses IOBI and IOB2. Next, regarding the operation of this embodiment, transistor Q5
1 Qs will be explained as an NfiMOSFET.
第２図はこの実施例の動作を説明するための各部信号の
タイミング図である。FIG. 2 is a timing chart of signals of various parts for explaining the operation of this embodiment.
ディジ，ト線ＤＩ，１，ＤＬ２がプリチャージ電圧■Ｐ
Ｒｉｌ：にプリチャージされると（ここではｖＰＲＩＣ
＝Ｖｃｃ／２とするが、ＶＰＲＥ ＝ ■ＣＣの場合も
動作は同様である）、トランジスタＱｓ ， Ｑ６は双
方共オンして節点Ｎ１は（ＶＰＲＥ ＶＴ）のレベル
になる（■１はトランジスタＱ５，Ｑ６のしきい値電圧
）．メモリセルＩＡ，ＩＢから情報を読出す場合、ワー
ド線ＷＬＩ，ＷＬ２が選択されてトランジスタＱ１，Ｑ
２がオンすると、容量素子ＣＩ，Ｃ２の電荷によって、
ディジット線ＤＬｕ，ＤＬｚ間に微小な電位差が生じる
。The digital and digital lines DI, 1, and DL2 are at precharge voltage ■P
When Ril: is precharged (here vPRIC
= Vcc/2, but the operation is the same in the case of VPRE = ■CC), transistors Qs and Q6 are both turned on, and the node N1 becomes the level of (VPRE VT) (■1 is the transistor Q5, Q6 threshold voltage). When reading information from memory cells IA and IB, word lines WLI and WL2 are selected and transistors Q1 and Q
2 turns on, the charges of the capacitive elements CI and C2 cause
A minute potential difference occurs between digit lines DLu and DLz.
制御回路２からセンス増幅器駆動回路３ヘセンス信号が
送られ、センス増幅器駆動回路３から制御信号８Ｅ１，
ＳＥ２が出力され増幅が始まると、一定時間後、ディジ
ット線１）Ｌｌ，ＤＬＺは一方が電源電圧ＶＣＣ１他方
が接地電位レベルとなる。A sense signal is sent from the control circuit 2 to the sense amplifier drive circuit 3, and the sense amplifier drive circuit 3 sends control signals 8E1,
When SE2 is output and amplification begins, after a certain period of time, one of the digit lines 1)Ll and DLZ becomes the power supply voltage VCC1 and the other becomes the ground potential level.
この時、トランジスタＱ５，Ｑ６ぱ、ゲートに接続され
ているディジット線が電源電圧Ｖｃｃならばオンし、ド
レインに接続されているディジット線が当然接地電位レ
ベルであるから節点Ｎ１の電荷が抜かれ、一方、ゲート
に接続されているディジット線が低レベルならばオフし
、ドレインに接続されているディジット線が電源電圧Ｖ
ＣＣでも節点Ｎ１に電荷は移動しない。At this time, transistors Q5 and Q6 turn on if the digit line connected to their gates is at the power supply voltage Vcc, and since the digit line connected to their drains is naturally at the ground potential level, the charge at node N1 is removed. , it turns off if the digit line connected to the gate is at a low level, and the digit line connected to the drain is at the power supply voltage V.
Even in CC, the charge does not move to the node N1.
故にトランジスタＱｓ ， Ｑ６の動作によシ、節点Ｎ
１はセンス増幅器４の電位差増輻完了時に、必ず接地電
位レベルとなる。Therefore, due to the operation of transistors Qs and Q6, node N
1 always becomes the ground potential level when the sense amplifier 4 completes increasing the potential difference.
また、トランジスタＱ５，Ｑ６がＰ型Ｍ０８ＦＥＴの場
合も、前記同様電位差増幅検知回路を構威し得る．但し
、電位差増幅完了時に節点Ｎｌｔｉ電源電圧ＶＣＣにな
る．トランジスタＱ５，Ｑ６がＮｆｉＭＯ８ＦＥＴ ，
Ｐ型Ｍ０８ＦＥＴのいずれの場合も、節点Ｎ１がプリチ
ャージ電圧ｖｐｉｖから接地電位レベルあるいは電源電
圧■ｃｃになったことをレベル判定回路６２によって判
定し、電位差増幅完了の情報が制御回路２に伝達され、
Ｉ／Ｏスイッチ回路５の開閉制御動作が行なわれる．レ
ベル判定回路６２は、ＣＭＯＳインバータ回路を用いれ
ばレシオ調整によって容易に構成することができる。Also, when the transistors Q5 and Q6 are P-type M08FETs, a potential difference amplification detection circuit can be used as described above. However, when the potential difference amplification is completed, the node Nlti becomes the power supply voltage VCC. Transistors Q5 and Q6 are NfiMO8FET,
In either case of the P-type M08FET, the level determination circuit 62 determines that the node N1 has changed from the precharge voltage vpiv to the ground potential level or the power supply voltage ■cc, and information indicating the completion of potential difference amplification is transmitted to the control circuit 2. ,
The opening/closing control operation of the I/O switch circuit 5 is performed. The level determination circuit 62 can be easily configured by ratio adjustment using a CMOS inverter circuit.
ここで注意を要するのは、センス増幅器４の能力と電位
差検出部６１の能力の関係である。What requires attention here is the relationship between the capability of the sense amplifier 4 and the capability of the potential difference detection section 61.
電位差検出部６１はセンス増幅器４の電位差増幅に追従
して動作し、決して電位差増幅の妨害をしてはならない
．しかし、回路構成上、電位差検出部６１はディジット
線Ｌ）Ｌｌ，ＤＬ２の電位差を解消する方向に働く。よ
って電位差検出部６１の能力は、センス増幅器４の能力
に対し無視出来る程度に充分小さくする必要がある。The potential difference detection section 61 operates in accordance with the potential difference amplification of the sense amplifier 4, and must never interfere with the potential difference amplification. However, due to the circuit configuration, the potential difference detection section 61 works in the direction of eliminating the potential difference between the digit lines Ll and DL2. Therefore, the capability of the potential difference detection section 61 needs to be sufficiently small to be negligible with respect to the capability of the sense amplifier 4.
以上説明したように本発明は、２つの節点間の微小電位
差の増幅が所定のレベルに達したことを検出して情報伝
達線の情報を出力する構或とすることによシ、最短時間
で正確な情報を伝達することができる効果がある。As explained above, the present invention is configured to detect that the amplification of the minute potential difference between two nodes has reached a predetermined level and output information on the information transmission line, thereby achieving the desired result in the shortest possible time. This has the effect of conveying accurate information.
７Ａ，７Ｂ・・・遅延回路、６１・・・電位差検出部、
６２・・・レベル判定回路，
ＤＬＩ ，ＤＬ２・・・ディジット線、ＩＯＢＩ ，Ｉ
ＯＢ２・・・Ｉ／Ｏバス、Ｑ１〜Ｑ６・・・トランジス
タ、ＷＬＩ，ＷＬ２・・・ワード線。7A, 7B...delay circuit, 61...potential difference detection section,
62... Level judgment circuit, DLI, DL2... Digit line, IOBI, I
OB2...I/O bus, Q1-Q6...transistor, WLI, WL2...word line.
Claims (1)
第２の情報源回路からの情報をそれぞれ伝達する対をな
す第１及び第２の情報伝達線と、前記第１及び第２の情
報伝達線に伝達された情報の微小電位差を所定のレベル
に増幅するセンス増幅器と、前記第１及び第２の情報伝
達線の情報の微小電位差が所定のレベルまで増幅された
か否かを検知する電位差増幅検知回路と、この電位差増
幅検知回路の出力信号に従ってスイッチ制御信号を出力
する制御回路と、前記スイッチ制御信号に従って前記第
１及び第２の情報伝達線の情報を出力端へ伝達制御する
スイッチ回路とを有することを特徴とする半導体集積回
路。a pair of first and second information source circuits; a pair of first and second information transmission lines that respectively transmit information from the first and second information source circuits; a sense amplifier that amplifies the minute potential difference of information transmitted to the second information transmission line to a predetermined level; and a sense amplifier that amplifies the minute potential difference of information transmitted to the second information transmission line to a predetermined level. a potential difference amplification detection circuit for detecting a potential difference, a control circuit for outputting a switch control signal according to an output signal of the potential difference amplification detection circuit, and a control circuit for transmitting information of the first and second information transmission lines to an output end in accordance with the switch control signal. 1. A semiconductor integrated circuit comprising a switch circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1244245A JPH03105787A (en) | 1989-09-19 | 1989-09-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1244245A JPH03105787A (en) | 1989-09-19 | 1989-09-19 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03105787A true JPH03105787A (en) | 1991-05-02 |
Family
ID=17115891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1244245A Pending JPH03105787A (en) | 1989-09-19 | 1989-09-19 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03105787A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5558127A (en) * | 1992-10-09 | 1996-09-24 | Kabushiki Kaisha Komatsu Seisakusho | Hydraulic pilot valve |
| US5845680A (en) * | 1993-09-28 | 1998-12-08 | Komatsu Ltd. | Damper of hydraulic pilot valve |
| JP2003303493A (en) * | 2002-04-09 | 2003-10-24 | Fujitsu Ltd | Control method for semiconductor memory device, and semiconductor memory device |
| JP2004503049A (en) * | 2000-07-07 | 2004-01-29 | モサイド・テクノロジーズ・インコーポレイテッド | Method and apparatus for synchronizing row and column access operations |
-
1989
- 1989-09-19 JP JP1244245A patent/JPH03105787A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5558127A (en) * | 1992-10-09 | 1996-09-24 | Kabushiki Kaisha Komatsu Seisakusho | Hydraulic pilot valve |
| US5845680A (en) * | 1993-09-28 | 1998-12-08 | Komatsu Ltd. | Damper of hydraulic pilot valve |
| US5983942A (en) * | 1993-09-28 | 1999-11-16 | Komatsu Ltd. | Damper of hydraulic pilot valve |
| JP2004503049A (en) * | 2000-07-07 | 2004-01-29 | モサイド・テクノロジーズ・インコーポレイテッド | Method and apparatus for synchronizing row and column access operations |
| JP2003303493A (en) * | 2002-04-09 | 2003-10-24 | Fujitsu Ltd | Control method for semiconductor memory device, and semiconductor memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5007024A (en) | Semiconductor memory device with sense amplifier controller | |
| US5555526A (en) | Synchronous semiconductor memory device having an auto-precharge function | |
| JPH0253879B2 (en) | ||
| EP0639000B1 (en) | Flip-flop type amplifier circuit | |
| US7583110B2 (en) | High-speed, low-power input buffer for integrated circuit devices | |
| JP3030624B2 (en) | Sense amplifier for semiconductor memory device | |
| US5506522A (en) | Data input/output line sensing circuit of a semiconductor integrated circuit | |
| US6829189B2 (en) | Semiconductor memory device and bit line sensing method thereof | |
| CN101071634A (en) | Static semiconductor memory | |
| US6486713B2 (en) | Differential input buffer with auxiliary bias pulser circuit | |
| JPS63288497A (en) | I/o circuit of cmos semiconductor memory device | |
| US5754487A (en) | Bit line precharge circuit | |
| JPH03105787A (en) | Semiconductor integrated circuit | |
| US5550777A (en) | High speed, low power clocking sense amplifier | |
| US5781041A (en) | Sense amplifier with low power in a semiconductor device | |
| JP3297949B2 (en) | CMOS current sense amplifier | |
| US6114881A (en) | Current mirror type sense amplifier | |
| US6456545B1 (en) | Method and apparatus for data transmission and reception | |
| EP0961282B1 (en) | Semiconductor memory device exhibiting improved high speed and stable write operations | |
| JPH01192078A (en) | Semiconductor memory device and level shift circuit | |
| US7031200B2 (en) | Data output apparatus for memory device | |
| KR200204911Y1 (en) | Sense amplifier in semiconductor memory device | |
| JP2723714B2 (en) | Semiconductor memory | |
| KR100341156B1 (en) | semiconductor memory | |
| KR100244433B1 (en) | Latched type sense amplifier |