JPH04110998A - Display controller - Google Patents

Abstract

PURPOSE:To eliminate the need of executing a large quality of processings and to execute the multi-window display processing at a high speed by fetching data from different areas in a storage device, and displaying them on a display screen, in accordance with to which divided display area the present display position belongs. CONSTITUTION:An address signal generating device 30 outputs a signal for showing an address of a storage device 12 in which data to be displayed at every divided display area is stored. To which divided display area the present scanning position belongs is detected, and in accordance therewith, an address signal for showing a data position in the corresponding display area is selected and applied to the storage device 12. From the storage device 12, data in different store areas of the storage device are switched and outputted at every divided display area, therefore, on the display screen, images shown by the store contents of each divided display area are divided each other and displayed. In such a way, a display speed of a multi-window display can be improved without using a video processing circuit having a function for displaying plural screens.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] This invention applies to CRT (Cathode-Ray Tube).
The present invention relates to a display control device for controlling the display of information on be), etc., and particularly relates to a display control device for a computer application product having a so-called multi-window function.

[Prior Art] FIG. 14 is a block diagram of a general circuit for displaying information in a so-called workstation, personal computer, or the like. Referring to FIG. 15, this circuit includes a CPU 10 for preparing or processing data to be displayed, a display memory 12a for storing display data prepared by CPU 10, and a display memory 12a for storing display data prepared by CPU 10. Parallel/serial conversion (
P/S) circuit 14, a video processing circuit 16 for converting display data converted into a serial signal by the P/S circuit 14 into a video signal and outputting the video signal, and video processing circuits 16 to 6.
A CRT 18 for displaying the video signal to be scanned, and a CP
Based on the video control information given from Ul0, the CRT controller (hereinafter referred to as rCRTCJ) outputs the reading address signal of the display memory 12a, horizontal and vertical synchronization signals to be added to the video signal, blanking signals, etc. (omitted) 20a.

Referring to FIG. 15, the CRTC 20a includes a control information storage unit 31 for receiving and storing information for controlling the screen from the CPU 10, such as information such as the maximum number of characters to be displayed in the horizontal direction and the maximum number of lines to be displayed in the vertical direction. , a screen position detection circuit for receiving a clock having a period corresponding to the scanning time of one character from an oscillation circuit (not shown) in response to scanning on the display screen of the CRT 18, and detecting the current display position on the CRT 18. 22, information regarding the current screen position given from the screen position detection circuit 22, and information for controlling the screen stored in the control information storage unit 31, a horizontal synchronization signal, a vertical synchronization signal, and a blanking signal are generated. It receives a signal indicating the current screen position from the synchronization signal output circuit 32 for output and the screen position detection circuit 22, receives a horizontal synchronization signal and a vertical synchronization signal from the synchronization signal output circuit 32, and displays it at the current scanning position. The address signal generation circuit 30a generates an address signal indicating a corresponding address of the display memory in which data to be displayed is stored and provides the generated address signal to the display memory 12a.

The synchronization signal output circuit 32 compares the signal indicating the screen position given from the screen position detection circuit 22 with the information indicating the end position of the horizontal scanning line stored in the control information storage unit 31, and determines whether the scanning is horizontal scanning. a horizontal synchronization signal output circuit 100 for outputting a horizontal synchronization signal when the end point of the line is reached;
Similarly, a vertical synchronization signal output circuit 102 for outputting a vertical synchronization signal by comparing the output of the screen position detection circuit 22 with information indicating the end position of vertical scanning stored in the control information storage unit 31; Blanking for outputting a blanking signal by comparing the 8 outputs of the screen position detection circuit 22 with information indicating the maximum number of displayed characters and lines in the horizontal and vertical directions stored in the control information storage unit 31 Signal output circuit 10
4.

Referring to FIG. 16, address signal generation circuit 30a:
In synchronization with the screen position signal and vertical synchronization signal given from the screen position detection circuit 22, the display memory 12a is reset to a predetermined initial value when the vertical blanking period exits.
a display address counter 110 for counting up the display address of the display address counter 110;
a register 106 in which an initial value at the time of reset is stored;
A display raster counter 112 for counting the raster number of the display raster by counting the horizontal synchronization signal and providing it to the display memory 12a;
Scroll number register 1 where the number of rasters per row is stored
16, and a coincidence detection circuit 114 for detecting a coincidence between the raster number output from the display raster counter 112 and the contents stored in the scan number register 116 and clearing the display raster counter 112 to "0". and a register 108 for storing an initial value when the display raster counter 112 is reset. The “row” in the above explanation is
For example, displaying characters in 40 characters x 20 lines on one screen,
It represents the "line" in the case of. When displaying one character with 8×8 dots, the number of rasters per line, that is, the number of scans to be performed, is eight.

Referring to FIGS. 14 to 16, a conventional display circuit using a CRTC operates as follows.

CPU10 stores data to be displayed in display memory 12a. The CPU10 also has a control information storage unit 31.
(Figure 15) shows how many characters to display horizontally, how many characters is the length of the horizontal scanning line, and similarly,
Information for controlling the screen is stored, such as the number of display lines in the vertical direction, the maximum number of lines, and the width of the synchronization signal and blanking signal.

The screen position detection circuit 22 is supplied with a clock having a period corresponding to the time required to display one character from an oscillation circuit (not shown). The screen position detection circuit 22 detects the position of the currently displayed character on the screen by counting this clock. A horizontal synchronization signal 100, a vertical synchronization signal 102, and a blanking signal output circuit 104 are used to detect the currently displayed character position detected by the screen position detection circuit 22 and to control the screen stored in the control information storage unit 31. The information is compared and a horizontal synchronization signal, a vertical synchronization signal, and a blanking signal are respectively provided to the video processing circuit. The horizontal synchronization signal and the vertical synchronization signal are also provided to the address signal generation circuit 30a.

Referring to FIG. 16, display address counter 110 calculates the address of display memory 12a in which characters to be displayed are stored by counting the screen position signal given from screen position detection circuit 22, and displays the address. The data is given to the memory 12a.

The display address counter 110 is reset at the end of the vertical blanking period in response to the vertical synchronization signal, and starts counting up again from the initial value stored in the register 106.

At the start of vertical scanning, the display raster counter 112
By taking in the initial value stored in the register 108 and counting up the horizontal synchronizing signal given thereafter, a signal indicating the raster number of the currently displayed row is given to the display memory 12a.

A signal indicating this raster number is also given to the coincidence detection circuit 114.

The coincidence detection circuit 114 compares the number of rasters per line stored in the number of scan registers 116 and the current raster number given from the display raster counter 112,
Raster counter 1 for detecting and displaying a match between the two
Reset 12.

The display raster counter 112 is cleared by being reset and starts counting the number of rasters again from "0".

As described above, when one line includes eight rasters, the display address counter 110 repeats the address output for one line until the display for one line is completed, that is, until eight rasters are displayed. . That is, the display address counter 110 repeats counting up one line of addresses eight times.

Referring again to FIG. 14, the display memory 12a is a CRT.
The data stored in the location specified by the address signal including the raster number given from C20a is output to the P/S circuit 14. The P/S circuit 14 is the display memory 12
The digital video signal given from a is converted into a serial signal and given to the video processing circuit 16. Video processing circuit 1
6 generates a video signal by processing the video data based on the synchronization signal given from the CRTC 20a.
Give to RT18. Therefore, the data stored in the display memory 12a is displayed on the CRT 18.

Recently, so-called multi-window processing, in which multiple screens are displayed on one screen, has become mainstream in so-called workstations, personal computers, and the like. This multi-window processing cannot be performed using the above-mentioned display circuit as is.

Therefore, in order to perform multi-window processing, it is necessary to have the following circuit configuration.

Multi-window processing can be realized, for example, by employing a display circuit having a configuration as shown in FIG. Referring to FIG. 17, this circuit differs from the circuit shown in FIG. 14 in that it has a save memory 118 connected to the CPU10 and for saving some data in the display memory 12a. be. Identical parts have been given the same reference numerals and names in FIGS. 17 and 14. Their functions are also the same.

Therefore, a detailed explanation thereof will not be repeated here.

Referring to FIG. 17, multi-window processing using this circuit is performed as follows. When performing multi-window processing, CPU10 saves data corresponding to a portion where other data should be displayed by multi-window processing, out of the video data stored in display memory 12a, to save memory 118. After the data has been saved, the CPU 10 writes the data to be displayed in the window in the display memory 12a at a position corresponding to the window.

The CRTC 20a is similar to the circuit shown in FIG.
The data written in the display memory 12a is regarded as one screen and is operated to be displayed on the CRT 18. Since the data stored in the display memo IJ 12a is such that one screen contains other screens,
The data displayed on the CRT 18 realizes a so-called window display.

When terminating the window processing, the CPU 10 transfers the data saved in the save memory 118 to the display memory 1.
2a, where it was originally stored. This results in
Multi-window processing will end.

When using the first method described above, the display memory 12a
Window display can be performed by saving an arbitrary location in the saving memory 118.

The CRTC 20a does not need to perform any special operations corresponding to multi-window processing. Also, by the operation of the CPU 10, a plurality of locations in the display memory 12a are saved in the evacuation memory 1.
18, and any number of multi-window processes can be performed.

This method is explained by referring to FIG. 14 again.
This is a method that provides multi-window processing in part 2a, and is applied to devices with low display capabilities that can only display one screen.

A second method for realizing multi-window processing is to use a device with high display capability that has a function of superimposing the stored contents of a plurality of display memories.

An example of such a display circuit is shown in FIG.

Referring to FIG. 18, this display circuit differs from the circuit shown in FIG. 14 in that, in addition to display memory 12a and P/S circuit 14a, other display memory 12b and
S circuit 14b. This circuit further includes a multiplexer 120 for switching the output of the P/S circuit 14a and the P/S circuit 14b and providing it to the video processing circuit.
is connected to CPU10 and P/S circuit 14b, and
and a prioritization circuit 122 for switching the output of multiplexer 120 between P/S circuits 14a114b according to priorities specified by U10.

In the case of the circuit shown in FIG.
22 monitors the output of the P/S circuit 14b, and when data to be displayed is output from the display memory 12b, the P/S circuit 14b monitors the output of the P/S circuit 14b.
The multiplexer 120 is operated to provide the output of the S circuit 14b, and in other cases, the output of the P/S circuit 14a to the video processing circuit.

Identical parts have been given the same reference numerals and names in FIGS. 18 and 14.

Their functions are also the same. Therefore, a detailed explanation thereof will not be repeated here.

The apparatus shown in FIG. 18 operates as follows. C
PUl0 writes, for example, data to be displayed on a background screen into the display memory 12a.

The CPU 10 also writes data to be displayed in the window to a location corresponding to the window in the display memory 12b. The CRTC 20a outputs the display memory 12a in synchronization with a clock signal given from an oscillation circuit (not shown).
, 12b, and generates addresses for the display memories 12a, 12b.
give to b. The addresses given to memories 12a and 12b are the same.

The display memories 12a and 12b are CRTC20a
The information stored in the positions corresponding to the address signals from the P/S circuits 14a and 14b is provided, respectively. The P/S circuits 14a, 14b are display memories 12a, 12
The parallel digital signal given from b is converted into a serial signal and given to the multiplexer 120. P/
The output of S circuit 14b is also provided to prioritization circuit 122.

For example, when the data output from the P/S circuit 14b is logic "1", the priority ranking circuit 122
The data of circuit 14b, otherwise P/S 1
4 multiplexer 120 so that the data of a is
Switch. As a result, the signal output from the multiplexer 120 becomes the data written in the window-corresponding position of the display memory 12b in the table tree memory 12a.

The CRT 18 (FIG. 14) has display memory 12a on which information stored in display memory 12a is displayed.
A so-called multi-window display in which the data stored in 2b is displayed in a window is performed.

In the case of the circuit shown in FIG.
Only one is available. When displaying a larger number of windows, it is necessary to prepare display memories corresponding to the number of display windows. By doing this, when performing window display, there is no need to save the contents stored in the display memory. Also, CR'T C
The operation of 20a is also quite similar to that of the first method.

In the block diagram shown in FIG.
The display memory 12a to the video processing circuit 16 provide a multi-window function.

[Problems to be Solved by the Invention] When performing multi-window processing using the conventional circuit as described above, there are the following problems.

When using save memory as in the first method,
When opening a window, it is necessary to save the data to be overwritten to a save memory. Even when closing a window, it is necessary to restore the evacuated data to its original storage location. As a result, the display speed during window display was reduced.

When performing multi-window processing using the second method, it is necessary to use a video processing circuit that has a function of superimposing data stored in a plurality of memories as described above. Furthermore, when scrolling only the display contents in the opened window, there is a problem that a load is placed on the CPU and the display speed is reduced due to the following reasons. This problem also occurs in the circuit according to the first method described above.

Referring to FIG. 19, for example, an image for one character is formed by raster 124. In this example, as shown in Figure 19 (a), the raster 12 for one character is
4 is formed of 8×8 dots. The number of each rask line is 000 to 1, as shown in FIG. 19(b).
11 (0 to 7 in decimal notation).

In the circuit using the first method and the second method described above, the following processing is required to scroll this data. That is, the stored contents of each raster are scrolled to the raster part one line higher on the display memory, such as the data of the first raster to the O-th raster, the data of the second raster to the first raster, and so on. This scrolling is performed by the CPU transferring data using software.

When scrolling the contents of the display memory in this manner, the CPU is burdened because the amount of data is large. Furthermore, data transfer by CPU10 is performed continuously, resulting in a decrease in display speed.

Therefore, an object of the present invention is to provide a display control device that can improve the display speed of multi-window display without using a video processing circuit that has the function of displaying multiple screens.

Means for Solving the Problem] A display control device according to the present invention is configured to output a plurality of address signals each for associating a scanning position of a display screen with a storage address of a storage device. an address signal output means; a public display area detection means for detecting which of the divided display areas the scanning position of the display screen belongs to in order to divide the display screen into a plurality of divided display areas; and a divided display area. and address signal selection means for selecting one of the plurality of address signals and applying it to the storage device in response to the output of the detection means.

[The active core address signal generator outputs a signal indicating the address of the storage device in which data to be displayed is stored for each divided display area. It is detected which divided display area the current scanning position belongs to, and an address signal indicating the data position of the corresponding divided display area is selected and applied to the storage device. Since data from different storage areas of the storage device is switched and output from the storage device for each split display area, the images represented by the storage contents of each split display area are separated from each other on the display screen. will be displayed.

[Embodiment FIG. 1 shows a CR which is an example of a display control device according to the present invention.
FIG. 2 is a block diagram of a display circuit portion of a computer or the like, including a TC 20. FIG. CRTC20 accepted in this example
can display three windows on the screen as shown in FIG. However, this CRTC is just one example, and a CRTC capable of displaying more multi-windows can also be realized using the concept as clarified by the following embodiments.

Referring to FIG. 10, this CRTC 20 can realize multi-window display using three windows, window 0, window 1, and window 2.

On the display screen 92, the horizontal start position of window 0 (94) is set to XOI, the end position to X02, the vertical start position to Yol, and the end position to YO2. Window 0 (94) height is HO2 width is W
It is O.

The horizontal starting position of window 1 (96) is Xll,
It is assumed that the end position is set to X12, the vertical start position is set to Yll, and the end position is set to Y12. Window 1 (
96) has a height of Hl and a width of Wl. Window 1 (
96) is included within the area of window 0 (94).

The horizontal starting position of window 2 (98) is X21,
It is assumed that the end position is set to X22, the vertical start position is set to Yll, and the end position is set to Y22. Window 2 (
98) has a height of H2 and a width of W2. Window (9
8) is included within the area of window 0 (94) and overlaps a part of window 1 (96).

Referring again to FIG. 1, the difference between this display circuit and the display circuit shown in FIG.
In place of the TC 20a, in place of the display memory 12a, a display memory 12 capable of dividing and storing display data for a plurality of both sides is included. 1st
Identical parts have been given the same reference numerals and names in the figures and FIG. 14. Their functions are also the same. Therefore, a detailed explanation thereof will not be repeated here.

Referring to FIG. 9, the storage areas of the display memory 12 include an area 86 for window 0, an area 88 for window 1,
It is divided into an area 90 for window 2. Area 86 for window 0 starts at (000). Area 88 for window 1 starts at (400)H. Area 90 for window 2 starts at (800)H.

Referring again to FIG. 1, the CRTC 20, which is an example of the display control device of the present invention, is connected to the CPU10 and controls the horizontal start position, end position, vertical start position, and end position of each window 0.1.2. a window position storage circuit 24 for storing the position; a screen position detection circuit 22 for detecting the display position of characters on the screen by counting clock signals from an oscillation circuit (not shown);
A control information storage circuit 31 that is connected to the CPU 10 and stores information for controlling the screen such as the display size of the entire display screen, the number of displayed characters, and the number of displayed lines, a screen position detection circuit 22, and a control information storage circuit. 31, and outputs a horizontal synchronization signal, a vertical synchronization signal, and a blanking signal based on information for controlling the screen stored in the control information storage circuit 31 in response to the output of the screen position detection circuit 22. It is connected to the synchronization signal output circuit 32 for displaying, the screen position detection circuit 22, and the CPUl01 synchronization signal output circuit 32, and in response to the output of the screen position detection circuit 22, each address where data to be displayed is stored is connected to the window 0.1
．． 2, the window position storage circuit 24, and the screen position detection circuit 22. A switching instruction circuit 26 for determining whether each window stored in the storage circuit 24 belongs to 0.1.2 and instructing whether data should be transferred to the video processing circuit for each window; It is connected to the instruction circuit 26, the address signal generation circuit 30, and the CPUI O, and selects one of the three address signals output by the address signal generation circuit 30 based on the priority specified by the CPUI0 and the output of the switching instruction circuit 26. and an address signal switching circuit 28 for selecting one of them and applying it to the display memory 12.

FIG. 2 is a more detailed block diagram of the window position storage circuit 24 and the switching instruction circuit 26.

Referring to FIG. 2, the window position storage circuit 24 stores the horizontal start position, end position, vertical start position, and
A window 0 position storage circuit 34 for storing the end position, a window 1 position storage circuit 36 for storing the start and end positions of window 1, and a window 1 position storage circuit 36 for storing the start and end positions of window 2. window 2 position storage circuit 38.

Circuits 34, 36, 38 all include the same elements. For example, circuit 34 is connected to CPUl0, is given the horizontal start position of window 0 from CPUl0, and has window 0*, horizontal start register 60 for storing this, and C
A window 0 horizontal end register 62 is connected to PU10 and is given the horizontal end position of window 0 from CPU10 and is used to store this.A window 0 horizontal end register 62 is connected to CPU10 and is given the vertical start position of window 0 and is used to store this. window O vertical start register 64 of
given the vertical ending position of window 0 from 0,
and a window 0 vertical register 66 for storing this.

The switching instruction circuit 26 is connected to the screen position detection circuit 22, and determines whether the currently displayed character position is within window 0. If it is determined that the character position is within window 0, the switching instruction circuit 26 switches the data of window 0. A window 0 switching instruction circuit 40 outputs a signal for instructing what should be transferred to the video processing circuit, and a window 1 switching instruction circuit 42 performs similar processing for windows 1 and 2.
, and a window 2 switching instruction circuit 44.

Each window 0 switching instruction circuit 40 has a register 6.
0.62.64.66 storage contents and screen position detection circuit 2
2. Detects a match with the currently displayed character position output,
- Coincidence detection circuit 46.48 for outputting a number output signal
．． 50.52, a flip-flop (FF) 54 set by the output of the -number calculation circuit 46 and reset by the output of the -number calculation circuit 48, and a -number calculation circuit 50.
a flip-flop 56 which is set by the output of
4 and the output of the FF 56, and an AND section 58 for providing the result to the address signal switching circuit 28 as a signal A.

Circuits 42 and 44 also include exactly the same components as circuit 40.

Circuits 42 and 44 determine whether or not the currently displayed character position is included in the window for windows 1 and 2, respectively, and provides signals B and C to the address signal switching circuit 28.

Referring to FIG. 3, the address signal generation circuit 30 has registers 78 whose inputs are connected to the CPU10 and are used to store initial values of addresses of data to be displayed in windows 0.1.2 given from the CPU10. .80, 82, and the output of the screen position detection circuit 22 is connected to the input of the address signal switching circuit 28. Address counter 72.7 for outputting an address signal of data stored in 0.1.2
4.76.

Address counters 72, 74, 76 are connected to the outputs of registers 78, 80, 82, respectively. Each address counter is reset at the exit of the vertical blanking period and starts counting addresses from the initial value stored in registers 78, 80, 82.

The address signal switching circuit 28 is an input switch instruction circuit 26.
It is connected to the output of the CPUIO and determines which window among windows 0.1.2 should be displayed based on the priority information given from the CPUI O, and the priority order for outputting it as a 2-bit signal. an attached circuit 68, whose input is connected to the output of the address counter 72, 74, 76,
A multiplexer 70 selects one of the eight three address signals of the address counters 72, 74, 76 based on a 2-bit signal given from the priority circuit 68 and supplies it to the display memory 12. including.

The reason why the signal output from the priority ranking circuit 68 is 2 bits is because there are three display windows in this example, and specifying with 2 bits is sufficient to select one of them. If there are five or more display windows, three bits are required, and if there are nine or more, four bits are required.

Referring to FIG. 4, the priority ranking circuit 68 includes CPU10
8 registers A to H, each of which can store 2-bit information, and a signal indicating whether the currently displayed character position is within each window, which is given from the switching instruction circuit 26. In response to A-C, registers A~
multiplexer 84 for selecting one of the stored contents of H and providing it to multiplexer 70.

Now, assume that the priority order of windows is set to 2>1>O. i.e. window 1 on top of window 0
is set so that window 2 is displayed above windows 0 and 1. At this time, register A
The contents stored in -H are shown in the oldest column in FIG. This value is set in registers A-H by CPU10.

The multiplexer 84 is set to output the contents stored in the corresponding registers A-H according to the values of the three signals A, B, and C (the leftmost column in FIG. 5) given from the switching instruction circuit 26. The fact that this setting prioritizes windows 2.1.0 will be explained in detail later.

The multiplexer 70 switches the address signal and applies it to the display memory 12 as shown in FIG. 8 in response to a 2-bit signal applied from the priority ranking circuit 68. That is, when the value of the signal applied from the circuit 68 is "00", the multiplexer 70 determines that there is no window output and does not apply the address to the display memory 12. When the input signal is "01", the multiplexer 70 gives the address of window 0, that is, the output of the address counter 72, to the display memory 12. When the input signal is "10", the multiplexer 70 gives the address of window 0, that is, the output of the address counter 72, to the display memory 12. The address of the window 2, that is, the output of the address counter 74, is applied to the display memory 12.If the value of the input signal is "11'', the multiplexer 70 gives the address of the window 2,
In other words, the output of the address counter 76 is displayed in the display memory 1.
Give to 2.

With reference to FIGS. 1 to 4, the CRTC 2 according to the present invention
The display circuit using 0 operates as follows. Since the data set in the CRTC 20 changes depending on the number of windows to be displayed, several types of multi-window processing will be explained below as examples.

Displaying only window 0 When displaying only window 0, the CRTC 20 operates as follows. CPU10 writes display data to window 0 area 86 of display memory 12 shown in FIG. CPU10 sets X01 to window 0 horizontal start register 60 (FIG. 2), XO2 to window 2 horizontal end register 62, Yol to window 0 vertical start register 64, and window 0 vertical end register 6.
Write YO2 in 6 respectively. Moreover, "0" or a value outside the display area is written in all the registers in the window 1 storage circuit 36 and the window 2 position storage circuit 38.

The screen position detection circuit 22 is supplied with a clock signal having the same period as the time required to display one character on the screen. The screen position detection circuit 22 detects the display position on the screen by detecting this clock signal, and sends a signal representing the screen position to the switching instruction circuit 26, address signal generation circuit 30, and synchronization signal output circuit 32. give.

The synchronization signal output circuit 32 receives the currently displayed character position given from the screen position detection circuit 22 and the control information storage circuit 3.
The video processing circuit 16 and the address signal generation circuit 3
Give to 0.

The register 78 (FIG. 3) of the address signal generation circuit 30 contains window 0 of the display memory 12 shown in FIG.
The start address of area 86, ie (000), (is C
Written by PUl0.

The address counter 72 responds to the vertical synchronization signal applied from the synchronization signal output circuit 32, is reset at the end of the vertical blanking period, and takes in the contents stored in the register 78 as an initial value. The address counter 72 counts the clock signal given from the screen position detection circuit 22 from an initial value.

As a result, the address counter 72 is stored in the display memory 12.
An address signal indicating the address of data to be displayed in window O, which is stored in window 0 area 86 (FIG. 9), is applied to multiplexer 70 of address signal switching circuit 28.

Similarly, the address counters 74.76 for the window 1 area and the window 2 area count clock signals from the initial value stored in the register 80.82. As a result, an address signal indicating the address of the memory 12 in which data to be displayed in windows 1 and 2 is stored is applied to the multiplexer 70.

Referring to FIG. 2, minus number output circuit 46 detects a match between the signal indicating the horizontal position provided from screen position detection circuit 22 and the contents stored in register 60, and sets FF 54. - The number output circuit 48 is the screen position detection circuit 22
The FF 54 is reset by detecting a match between the signal indicating the horizontal position given from the register 62 and the contents stored in the register 62.

Therefore, the output of the FF 54 is set when the current display position is in the horizontal direction between XOI and XO2, and is reset otherwise.

- The number output circuit 50 detects a match between the vertical position of the display position given from the screen position detection circuit 22 and the contents stored in the register 64, and sets the FF 56. - The number output circuit 62 detects a match between the vertical display position given from the screen position detection circuit 22 and the register 66, and
Reset F56. Therefore, the output of the FF 56 is set when the vertical coordinate of the display position is between Yol and YO2, and reset otherwise.

The AND unit 58 applies the content of the signal A to the address signal switching circuit 28 as "1" when the outputs of the FFs 54 and 56 are both set, and as "0" in other cases.

The window 0 position storage circuit 34 and the window 0 switching instruction circuit 40 operate as described above. The signal A given to the address signal switching circuit 28 is "1" when the display position is within window 0 (94) shown in FIG.
In other cases, it becomes "0". The window 1 switching instruction circuit 42 and the window 2 switching instruction circuit 44 operate similarly to the window 0 switching instruction circuit 40. In this case, the contents stored in the window 1 position storage circuit 36 and the window 2 position storage circuit 38 are set so that no coincidence is detected at least within the display range. Therefore, the outputs of circuits 42 and 44 are both "0".

Referring to FIG. 4, multiplexer 84 performs processing as shown in FIG. 5 in response to the value of signal ASBSC applied from switching instruction circuit 26. Referring to FIG. In this example, the values of the signals C and BSA are each 0.0.1, which corresponds to the second line in FIG.

That is, multiplexer 84 selects the content "01" stored in register B and supplies it to multiplexer 70 (FIG. 3).

As already explained with reference to FIG. 8, when the 2-bit signal given from the priority circuit 68 is "01", the multiplexer 70 transfers the address signal output from the address counter 72 to the display memory. 12.

The data stored in the window 0 area 86 (FIG. 9) is supplied from the display memory 12 to the P/S circuit 14. P/S
The signal converted into a serial signal by the circuit 14 is converted into a video signal by the video processing circuit 16, and the signal is converted into a video signal by the video processing circuit 16.
8.

By setting the circuits 34, 36, and 38 (FIG. 2) as described above, only window 0 is displayed on the screen.

Display of only windows 0 and 1 When displaying only window 0.1 and not displaying window 2, CPU10 stores horizontal start position X11, horizontal start position X11, A horizontal end position X12, a vertical start position Yll, and a vertical end position Y12 are each set. As a result, the output B of the window 1 switching instruction circuit 42 becomes 1'' when the display position is within the window 1 shown in FIG. 10, and becomes 0 otherwise.

On the other hand, the signal C output from the window 2 switching instruction circuit 44
is always “0” because no data is set in the window 2 position storage circuit 38.

The start address (400) of the window 1 area 88 (FIG. 9) is stored in the register 80 in advance by the CPU10.
is set. Once, address counter 74
The address signal outputted by the window 1 area 88 is
Indicates the location where the data to be displayed is currently stored.

With reference to FIGS. 5 and 10, consider the case where the display position is outside window 0. At this time, the signal given from the switching instruction circuit 26 to the priority ordering circuit 68 is "00".
0'' (assuming that it is in the order of the signal “CBA”).

This corresponds to the first line in FIG.
(Figure 4) shows the contents of register A, that is, “00”
is applied to multiplexer 70 (FIG. 3). Referring to FIG. 8, multiplexer 70 determines that there is no window output and does not send an address signal to display memory 12. Therefore, no data is displayed on the screen in this area.

Assume that the display position is within window 0 and in an area other than window 1. At this time, the signal A given from the switching instruction circuit 26 is "1", and the signal BSC is both "0".
It is. As in the case of displaying only window 0, multiplexer 70 supplies only the address signal output from address counter 72 to display memory 12. Therefore, in this area, only window 0 data is displayed on the CRT 18.
displayed above.

Referring to FIG. 10, consider the case where the display position is within window 1. At this time, the value of the signal given from the switching instruction circuit 26 to the priority ranking circuit 68 becomes "011". This value corresponds to the case shown in the east 4 row of FIG. 5, so multiplexer 84 (FIG. 4) provides "10" to multiplexer 70.

In this case, multiplexer 70 provides display memory 12 with the address signal of window 1 corresponding to input "10'', ie, the address signal output from address counter 74, as shown in FIG. Therefore, in window 1, data stored in window 1 area 88 (FIG. 9) of memory 12 is displayed.

Since no data is set in the window 2 position storage circuit 38, the value of the signal C output from the window 2 switching instruction circuit 44 is always "O" in this case. The data stored in window 2 area 90 (FIG. 9) is never displayed within window 2 (98).

All window display When all windows are displayed, the window 2 position storage circuit 38 further stores the horizontal direction start position
, end position X22, vertical start position Y21, and end position Y22 are set. Therefore, in this region, the value of the signal C output by the window 2 switching instruction circuit 44 is “
1”, and “0” in other areas.

In this case, in addition to the case where only window 0.1 is displayed, the following operation is performed when the display position is within window 2. When the display position is within the overlapping range of windows 1 and 2, the value of the signal output from the switching instruction circuit 26 is "111". Fifth
As shown in the figure, the value of the signal output from the multiplexer 84 of the priority ranking circuit 68 in this case is "11".

As shown in FIG. 8, the address signal output by the multiplexer 70 of the address signal switching circuit 28 is the address signal of window 2, that is, the address counter 76.
This is the signal output by Therefore, in this case, the data to be displayed in window 2 stored below address (800)□ in memory 12 is displayed on CRT 18.

If the display position is within the overlapping range of window 0 and window 2 and outside the area of window 1, the following will occur. The value of the signal output from the switching instruction circuit 26 is "101".

Referring to FIG. 5, the value of the signal output from multiplexer 84 (FIG. 4) is the value stored in register F, that is, "
11''. Also in this case, the address signal given from the multiplexer 70 to the display memory 12 is an address signal for displaying window 2.CRT 18
The data of window 2 is displayed at the top.

A display circuit using the CRTC 20 according to the present invention operates as described above. Therefore, the following effects occur. When performing multi-window processing, CPU1
Window display can be performed simply by writing data for display in the area corresponding to each window in the memory 12 and resetting the contents of each register in the window 1 storage circuit 24. Unlike the circuit according to the first method of the prior art, there is no need to save the contents stored in the memory to the save memory before displaying the window.

Therefore, the load on the program executed by CPU10 is significantly reduced, and display speed can be improved.

Even when the window ends, the window 1 storage circuit 24
All you need to do is change the settings of each register in the . There is no need to write the data saved again to the original area when the window is closed, and the display speed can be improved.

Also, register A- in the priority circuit 68 (FIG. 4)
By changing the contents stored in H, the priority order of windows can be easily and dynamically changed. For example, when prioritizing windows in the order of 0>1>2, the contents of registers A to H may be changed as shown in FIG. The difference between the contents of FIG. 6 and the contents shown in FIG. 5 is that the contents stored in registers D and FSH are "0".
1", and the contents stored in register G are changed to "10". As a result, if window 0 overlaps with another window, window 0 will be changed, and if window 1.2 or Window 1 will be displayed respectively.

When prioritizing each window in the order of 1>2>0, the contents stored in registers A to H may be changed as shown in FIG. The difference between the contents shown in FIG. 7 and the contents shown in FIG. 5 is that the contents stored in registers G and H have been changed to 01 and 10, respectively. Window 1 will be displayed in the area where windows 0.1.2 overlap, and window 1 will be displayed in the area where windows 0.1.2 overlap.

By configuring the CRTC 20 as described above, the following effects are also produced. The start and end positions of window 0.1.2 are window 0 shown in FIG.
This can be easily changed by changing the storage contents of the registers of the position storage circuit 34, window 1 position storage circuit 36, and window 2 position storage circuit 38. Therefore, each window can be easily moved to any position on the display screen or its size can be changed.

Furthermore, according to the above-described CRTC 20, scroll processing within a window can be easily performed. It is assumed that the address signals output from the address counters 72, 74, 76 include the rask number as described in the prior art. For example, CPUIO sets the contents of register 80 to 1.
It is assumed that the count increases by 1 for each vertical period. 1st
9, for example, raster 12 within a certain vertical period.
4 is displayed in the window from raster A. In the next vertical period, the initial value of the raster number is 1.
After being counted up, the raster number of the address signal output from the address counter 74 starts from "001". Therefore, raster 124 is displayed starting from raster line B in this vertical period. Similarly, in the next vertical period, raster 124 is displayed starting from raster line C. This means that the image is moved up by one line in each vertical period, and the data in window 1 is scrolled.

In the above-described scrolling process, the CPU 10 only needs to increment the contents stored in the register 80 by one every vertical period. Unlike the device according to the second conventional method, there is no need for the CPU 10 to scroll the contents stored in the display memory 12 through transfer processing. The processing amount of CPU10 is significantly reduced, and its burden is much lighter than before.

Therefore, the display speed when scrolling is performed is also much improved compared to the conventional method.

Further, there is no need to provide special hardware for multi-window processing in the video processing circuit or the like. CR
The multi-window processing and scrolling processing described above can be performed only by the TC 20.

FIG. 11 is a flowchart of the window opening portion of the program executed by CPU10 when a display circuit is configured using the CRTC 20 according to the present invention.

FIG. 12 is a flowchart of a program when opening a window using the first conventional method, and FIG. 13 is a flowchart of a program when opening a window using the second conventional method. In FIG. 11, the case where window 1 is opened is shown as an example.

Referring to FIG. 11, in step S1, the register 8
0 (FIG. 3) is the start address (4) of the area 88 of the memory 12 in which the data to be displayed in the window
00)H is set.

Subsequently, in steps 82 to S5, the contents of the horizontal start register, horizontal end register, vertical start register, and vertical end register (none of which are shown) of the window 1 position storage circuit 36 shown in FIG. 2 are stored as shown in FIG. It is set according to the display area of window 1 as shown in FIG.

In step S6, the contents of registers A-H (FIG. 4) of the priority ranking circuit 68 are set.

Furthermore, in step S7, the data displayed in window 1 is transferred to window 1 area 88 (
(Fig. 9). As a result, the data stored in the window 1 area 88 of the memory 12 is displayed in the window 1.

According to the first conventional method compared with this, step S
At 11, the data stored in the window area in the memory is first saved to the save memory. Subsequently, in step S12, data to be displayed within the window is transferred.

That is, according to this first conventional method, step S
ll requires processing to temporarily save data in memory. Therefore, as mentioned above, the operation speed when opening a window becomes slower. This reverse transfer is also required when closing the window, which slows down the display speed. According to the method according to the present invention, there is no need to save or write back data, so it is possible to improve display speed.

According to the second conventional method as shown in FIG.
As in the case of using the CRTC according to the present invention, various registers are first set in step S21. Then, in S22, the display data within the window is transferred to the display memory for the window. In this case, there is no need to save or write back data as in the first method.

Therefore, there is no slowdown in processing speed when opening and closing windows.

However, in order to scroll the display data in the window, the data in the display memory must be transferred again and the stored contents themselves must be scrolled. Therefore, in scroll processing, the amount of processing is larger and the processing speed is slower than when using the CRTC according to the present invention.

On the other hand, when the CRTC according to the present invention is used, there is no reduction in processing speed when opening or closing a window. Furthermore, when scrolling data in a window that has just been opened, it is sufficient to simply rewrite the contents of the register. The amount of processing is extremely small compared to the case of transferring display data, and the display speed does not decrease even in the case of scroll processing.

As described above, according to the present invention, the video processing circuit does not require a special circuit for multi-window processing, and can operate at high speed not only when opening and closing a window but also when scrolling data within the window. It is possible to realize a possible CRTC.

The present invention has been described above based on one embodiment. However, the above is merely an example, and the present invention is not limited to this embodiment. It is also possible to implement various other modifications.

[Effects of the Invention] As described above, according to the present invention, data is retrieved from different areas in the storage device and displayed on the display screen depending on which divided display area the current display position belongs to. .

Therefore, a different screen is displayed for each divided display area, and a so-called multi-window display is realized. The only operation required to perform such multi-window processing is to rewrite a small amount of data, such as a register indicating the position of a divided display area and a register indicating priority. Since there is no need to perform a large amount of processing such as transferring the video data itself as in the past, the processing speed is increased. Furthermore, scroll processing can be performed by simply rewriting a very small amount of data, so there is no need to perform a large amount of processing to scroll the contents stored in the storage device. CPU processing is also simplified, and display speed can be significantly improved.

That is, it is possible to provide a display control device that can simultaneously display multiple screens and improve the display speed without using a video processing circuit or the like that has the function of displaying multiple screens. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display circuit using a CRTC according to the present invention, FIG. 2 is a block diagram of a CRTC window position storage circuit and switching instruction circuit according to the present invention, and FIG. 3 is a block diagram of a display circuit using a CRTC according to the present invention. FIG. 4 is a block diagram of the CRTC address signal generation circuit and address signal switching circuit according to the invention, FIG. 4 is a block diagram of the priority circuit, and FIG. 5 is a diagram illustrating the case classification of the operation of the priority circuit. 6 and 7 are diagrams showing the stored contents of the priority ordering circuit when different priorities are assigned, and FIG. 8 is a diagram showing the case classification of the operation of the multiplexer 70, FIG. 9 is a diagram showing the division of the storage area of the memory 12, FIG. 10 is a schematic diagram of a display screen for explaining multi-window processing, and FIG. This is a flowchart of a program executed on CPU10 when opening a window, FIGS. 12 and 13 are flowcharts when performing multi-window processing using the conventional method, and FIG. 14 is a flowchart when performing multi-window processing using the conventional method. FIG. 15 is a block diagram of a conventional CRTC, and FIG. 16 is a block diagram of a conventional CRTC.
17 is a block diagram of an address signal generation circuit, FIG. 17 is a schematic diagram of a display circuit according to the first method for performing multi-window processing, and FIG. 18 is a block diagram of a conventional display circuit. 19 is a block diagram of a display circuit for performing multi-window processing according to method 2, and FIG. 19 is a schematic diagram showing the relationship between raster and raster line numbers. In the figure, 10 is a CPU, 12 is a display memory, 14 is a parallel/serial conversion circuit, and 18 is a CRT. 20 is a CRTC, 22 is a screen position detection circuit, 24 is a window position storage circuit, 26 is a switching instruction circuit, 28 is an address signal switching circuit, 30 is an address signal generation circuit, 68
indicates a prioritized circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A display control device for displaying an image on a display screen that is scanned at predetermined time intervals by transferring a video signal stored in a storage device onto the display screen, each of which includes: address signal output means for outputting a plurality of address signals for associating a scanning position of the display screen with one of the storage addresses of the storage device; and dividing the display screen into a plurality of divided display areas. split display area detection means for detecting which of the split display areas the scanning position of the display screen belongs to; and address signal selection means for selecting one of the signals and applying it to the storage device.