JPH04109713A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the degree of circuit integration and to attain the operation of the circuit with a single power supply by adopting a CMOS inverter including a P-(or N) channel transistor(TR) whose absolute threshold voltage is larger than that of a TR being a component of an internal circuit for a level shift circuit. CONSTITUTION:An insulation film 4a is laminated on an insulation film 3 for a P-channel TR P1 of a level shift circuit and an absolute value of a threshold voltage is increased more than an absolute value of the difference between an H level of an input signal of the level shift circuit and a power supply level VDD. Thus, the level shift circuit whose output changes from 0 to 12V with respect to an input signal whose level changes from 0 to 5V is realized, and since the P-channel TR P1 is turned on and an N-channel TR N1 is turned off with respect to the input signal whose level is OV and the P-channel TR P1 is turned off and the N-channel TR N1 is turned on with respect to the input signal whose level is 5V, no steady-state current flows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having a level shift circuit having a CMOS configuration.

[Conventional technology]

FIG. 2(a) is a circuit diagram of a conventional example, and FIG. 2(b) is a sectional view of a semiconductor chip shown in a MOS transistor used in the conventional example.

The level shift circuit 101 controls the logical amplitude (0 to V) of the input signal.
cc (5V) ) amplify (G ~ Vt1D (12V)
) and transmit it to the internal circuit, but the N-channel transistor N2. N3. P-channel transistor P2.
P3 each has the same threshold voltage as the transistors forming the internal circuit.

[Problem to be solved by the invention]

The above-mentioned conventional level shift circuit not only requires two power supplies but also has the drawback of poor integration because the circuit is configured with six transistors.

Furthermore, even if you try to use a CMOS inverter composed of transistors with the same threshold voltage as the transistors in the internal circuit as a level shift circuit, the logic amplitude of the input signal is smaller than that of the internal circuit, so the input signal will be "H".
Since the P-channel transistor does not necessarily turn off even when the level shifts, the level shift function becomes incomplete.
Another drawback is that a steady current flows.

[Means to solve the problem]

The present invention provides a semiconductor integrated circuit device having a level shift circuit for amplifying logic amplitude, in which the level shift circuit has an absolute value of the potential difference between the °"H'" level and the power supply potential in the positive (or negative) logic of the input signal. It is a CMOS inverter having a P (or N) channel transistor whose absolute value of the threshold voltage is larger than the absolute value of the threshold voltage.

〔Example〕

Figure 1 (a> is a circuit diagram of an embodiment of the present invention, Figure 1 (b)
) is a cross-sectional view of a semiconductor chip showing a level shift circuit of one embodiment.

1 is a gate polysilicon film of a P-channel transistor,
2 is the gate polysilicon film of the N-channel transistor, and the insulating film directly under the gate polysilicon film is normally formed simultaneously for the P-channel transistor and the N-channel transistor, as shown in Fig. 2, but in this example, the level shift For the P-channel transistor array 1 of the circuit, an insulating film 4a is laminated on the insulating film 11W3 as shown in FIG. 1(a),
The absolute value of the threshold voltage is set to the H level of the input signal of the level shift circuit.
“Make it larger than the absolute value of the potential difference between the level and the power supply potential VDD.

The amplitude of the input signal IN is from Vss''Ov to VCC5v, the power supply voltage VDD of the semiconductor integrated circuit device 100a is 12v, the absolute value of the threshold voltage of P channel transistor 1 is 8v, and the absolute value of the threshold voltage of N channel transistor N1 is 5v. When the absolute value is normal IV, if IN is "L" level Ov, the voltage between the gate and back gate of Pl is V.2
Since 12V is greater than 8V, Pl is on, and the voltage between the gate and back gate of Nl is V. Since N is Ov, which is smaller than lv, N1 is turned off, and the output signal ○a outputs the power supply voltage VDD. Next, if IN is 5v at the level of ゛H, then ■G
P is turned off because the potential difference between VDD and VCC is 7V, which is smaller than 8V, and IVGN is turned on because it is 5V, which is larger than 1V, and Oa outputs Ov.

As mentioned above, a level shift circuit is realized in which the output signal changes between 0 and 12V in response to an input signal that changes between 0 and 5V, and when the input signal is OV, P channel transistor 1 is turned on, and N channel transistor If N1 is off and the input signal is 5.times., the P-channel transistor 1 is off and the N-channel transistor is on, so that no steady current flows.

Since the configuration is simple with a single power supply system, the degree of integration of the semiconductor integrated circuit device can be improved.

The above has explained the case of positive power supply and positive logic, but in the case of negative power supply and negative logic, the absolute value of the threshold voltage of N-channel transistor N4 can be increased as shown in Fig. 3 (a) and (b). do it.

Furthermore, it goes without saying that channel doping may be used to increase the absolute value of the threshold voltage of a MOS transistor.

〔Effect of the invention〕

As explained above, the semiconductor integrated circuit device of the present invention includes
By making the level shift circuit a CMOS inverter including a P (or N> channel transistor whose absolute value of the threshold voltage is larger than that of the transistors constituting the internal circuit), the number of elements can be reduced and the degree of integration can be increased. This has the effect of enabling operation with a single power supply.

Furthermore, by realizing a circuit configuration with a single power supply, there is no need to perform N-well isolation or latch-up measures between N-wells unlike in a circuit configuration with two power supplies, which also increases the degree of integration and simplifies the design. It also has the effect of becoming.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a circuit diagram and a cross-sectional view showing an embodiment of the present invention, and FIGS. 2(a) and (b) are
are a circuit diagram and a sectional view showing a conventional example, respectively, and Fig. 3 (
a) and (b) are a circuit diagram and a sectional view, respectively, showing other embodiments of the present invention. 1.2...Gate polysilicon film, 3.4a. 4b...Insulating film, 5...P4 type diffusion layer, 6...N
Well, 7...N+ type resistive diffusion layer 8...P type Si substrate, 91. . Field oxide film, 10... Interlayer insulating film, 11...
Aluminum electrode, 100, 100a, 100b=-semiconductor integrated circuit device, 101.101a 101b-・
・Level shift circuit, 102, 102a, 102b...
・Internal circuit, IN・Input signal (or its terminal), P1~
P4...P channel transistor, VDD...positive power supply terminal, VDD...negative power supply terminal.

Claims (1)

[Claims] In a semiconductor integrated circuit device having a level shift circuit for amplifying logic amplitude, the level shift circuit has a threshold voltage that is greater than the absolute value of the potential difference between the "H" level in the positive (or negative) logic of the input signal and the power supply potential. P with large absolute value
A semiconductor integrated circuit device characterized in that it is a CMOS inverter having (or N) channel transistors.