JPH06283672A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to apply a bias across a well area formed in a semiconductor substrate without increasing the power consumption nor causing peripheral circuits to malfunction even when a voltage higher than the power supply voltage is applied across a pad connected to an impurity diffusion layer area formed in the well area. CONSTITUTION:The circuit is provided with a first conductivity semiconductor substrate 11, well area 12 which is formed in the substrate 11 and has a second conductivity type which is opposite to the first conductivity type, and an impurity diffusion layer area 14 which is formed in the well area 12 and has the first conductivity. In addition, the circuit is also provided with a pad for applying an external voltage across the area 14, detection circuit 17 which detects whether or not the voltage applied across the pad 15 is higher than the power supply voltage of this circuit, and switching circuit 18 which switches the voltage applied across the well area 12 between the voltage applied across the pad 15 and the power supply voltage of this circuit in accordance with the detecting output of the circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a well region having an impurity diffusion layer region connected to a terminal to which an external voltage higher than a power supply voltage may be applied. The present invention relates to a substrate bias circuit that applies a bias.

[0002]

2. Description of the Related Art In non-volatile semiconductor memories such as EPROM and EEPROM, ground potential Vss is applied to an external terminal.
Alternatively, a signal of the power supply potential Vcc or a voltage (program voltage) Vpp higher than the power supply voltage may be applied.

As described above, an external terminal to which an external voltage higher than the power supply voltage may be applied is used as an impurity diffusion layer region (for example, a pull-up diffusion resistor or a MOS transistor) formed in a well region in a semiconductor substrate. Source / drain regions, etc.), there are the following problems.

FIG. 3 shows a part of a semiconductor substrate of an EPROM, for example, 31 is a P-type substrate, 32 is an N-type well region formed in the P-type substrate, and 33 is an electrode region of the N-type well region ( N + type regions) and 34 are P type diffusion resistance regions formed in the N type well region. Reference numeral 35 denotes a pad connected to the P-type diffusion resistance region, which is connected to an external terminal.

Since the P-type substrate 31 is connected to the ground potential Vss and the N-type well region 32 is connected to the power supply potential Vcc, the PN junction between the substrate 31 and the well 32 is biased in the reverse direction.

Since the N-type well region 32 is connected to the power supply potential as described above, it is prohibited to apply a voltage higher than the power supply voltage to the pad 35 connected to the P-type diffusion resistance region 34. There is. Because pad 3 above
When a voltage higher than the power supply voltage is applied to 5, the diffusion resistance 34
The PN junction between the wells 32 is biased in the forward direction and a current flows in the well region, which increases the current consumption and also makes the substrate bias of the peripheral circuit unstable and causes a circuit malfunction. is there.

In recent years, external terminals (pins) of integrated circuits
The number of P-type diffused resistance regions as described above is added to any one of the existing plurality of pins when the existing multiple pins are to be shared by one pin. When this is connected, it is impossible to apply a voltage higher than the power supply voltage to this pin, so that this pin cannot be used also as another pin.

In order to prevent the above problems from occurring, the circuit is configured to use the N-type diffused resistance region instead of the P-type diffused resistance region, or the polysilicon is replaced with the P-type diffused resistance region. Although a resistor or the like is used, it is not preferable to be restricted by such a device configuration.

[0009]

As described above, in the conventional integrated circuit, the external terminal to which an external voltage higher than the power supply voltage may be applied has the impurity diffusion layer region formed in the well region in the semiconductor substrate. However, if an external voltage higher than the power supply voltage is applied, the current consumption increases and the peripheral circuits malfunction.

The present invention has been made to solve the above problems, and a voltage higher than the power supply voltage is applied to a pad connected to an impurity diffusion layer region formed in a well region in a semiconductor substrate. Even in such a case, it is an object of the present invention to provide a semiconductor integrated circuit capable of applying a bias to the well region without increasing the current consumption and causing malfunction of peripheral circuits.

[0011]

A semiconductor integrated circuit according to the present invention comprises a semiconductor substrate of a first conductivity type and a well region of a conductivity type opposite to the first conductivity type formed in the semiconductor substrate.
A first conductivity type impurity diffusion layer region formed in the well region, a pad for applying an external voltage to the impurity diffusion layer region, and a voltage applied to the pad are equal to or higher than the power supply voltage of the integrated circuit. A detection circuit that detects whether or not there is,
A switching circuit for switching and supplying the voltage applied to the pad or the power supply voltage of the integrated circuit to the well region according to the detection output of the detection circuit.

[0012]

When a voltage higher than the power supply voltage is applied to the pad, the applied voltage of the pad is supplied to the well region, so that the PN junction between the impurity diffusion layer and the well is forward biased. In this case, no current flows through the well, and the consumption current does not increase and the peripheral circuits do not malfunction.

Therefore, since it becomes possible to connect an external pin to which the external voltage higher than the power supply voltage may be applied to the pad, a plurality of existing pins can be commonly used by one pin to reduce the number of integrated circuits. It becomes possible to promote pinning.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an EPRO according to an embodiment of the present invention.
A part of M is shown.

Here, 11 is a P-type substrate, which is connected to the ground potential Vss. Reference numeral 12 is an N-type well region formed in the P-type substrate, and 13 is an electrode region (N
+ Type regions) and 14 are P type diffusion resistance regions formed in the N type well region. Reference numeral 15 is a pad for applying an external voltage to the P-type diffusion resistance region, which is connected to an external terminal.

Reference numeral 16 is a substrate bias circuit, which is a power supply voltage level detection circuit 17 for detecting whether or not the voltage applied to the pad 15 is higher than the power supply voltage Vcc of the EPROM.
And a voltage switching circuit 18 for switching and supplying the voltage applied to the pad 15 or the power supply voltage of the EPROM to the well region 12 according to the detection output of the power supply voltage level detection circuit 17.

In the EPROM, when the ground potential Vss is applied to the pad 15, the power supply voltage Vcc is supplied to the well region 12, and the PN junction between the substrate 11 and the well 12 and the diffusion resistor 14 The PN junctions between the wells 12 are reverse biased.

On the other hand, the power supply voltage Vcc is applied to the pad 15.
When a higher voltage (for example, the program voltage Vpp) is applied, the applied voltage V of the pad 15 is applied to the well region 12.
Since the pp is supplied, the PN junction between the substrate and the well is also reversely biased. Further, the PN junction between the diffused resistor 14 and the well 12 is not biased in the forward direction, no current flows through the well 12, and no increase in current consumption or malfunction of peripheral circuits occurs.

Therefore, since it becomes possible to connect an external pin to which the external voltage higher than the power supply voltage is applied to the pad, a plurality of existing pins can be commonly used by one pin to reduce the number of integrated circuits. It becomes possible to promote pinning. FIG. 2 is a circuit diagram showing a specific example of the substrate bias circuit of FIG.

Here, 15 is a pad, 19 is a P-type diffusion resistor for pull-up, P8 is a PMOS transistor for switching, 17 is a power supply voltage level detection circuit, 181 is a power supply voltage supply circuit, and 182 is an external voltage supply circuit. And the power supply voltage supply circuit 181 and the external voltage supply circuit 182.
Have their output nodes connected in common to form the voltage switching circuit 18 in FIG.

The P-type diffusion resistor 19 for pulling up is
One end is connected to the Vcc node and the other end is connected to the drain of the PMOS transistor P8.
The pad 15 is connected to the source of the OS transistor P8.

The source / drain diffusion regions of the P-type diffusion resistor 19 and the PMOS transistor P8 are formed in the N-type well region, and this N-type well region (the substrate region of the P-type diffusion resistor 19 and the PMOS transistor P8). Is supplied with the voltage of the output node 18a of the voltage switching circuit as a bias.

In the power supply voltage level detection circuit 17, the source / substrate region is connected to the pad 15 and the gate is V
A PMOS transistor P1 connected to the cc node, an NMOS transistor N having a drain connected to the drain of the PMOS transistor P1, a source / substrate region connected to the Vss node, and a gate connected to the Vcc node.
1 and a first inverter circuit 21 whose input end is connected to the drain interconnection nodes of the transistors P1 and N1.

The power supply voltage supply circuit 181 includes the first
Of the inverter circuit 21, the gate of which is connected to the output terminal 18a of the voltage switching circuit, and the drain of which is connected to the drain of the PMOS transistor P2 whose source / substrate region is connected to the output node 18a of the voltage switching circuit. Is connected to the Vss node and the gate is connected to the output node of the first inverter circuit 21.
The OS transistor N2 and the source are connected to the Vcc node, and the drain / substrate region is the output node 1 of the voltage switching circuit.
8a, and a PMOS transistor P7 whose gate is connected to the drain interconnection node of the transistors P2 and N2.

The external voltage supply circuit 182 is a PMO in which each source / substrate region is connected to the pad 15 and each drain is cross-connected to the other gate.
The drains of the S-transistors P3 and P4 are connected to the drains of the PMOS transistor P3.
An NMOS whose substrate region is connected to the Vss node and whose gate is connected to the output node of the first inverter circuit 21.
The drain is connected to the drains of the transistor N3 and the PMOS transistor P4, and the source / substrate region is V.
An NMOS transistor N4 connected to the ss node, a PMOS transistor P5 having a source / substrate region connected to the pad 15 and a gate connected to the drain interconnection node of the transistors P4 and N4;
The source is connected to the drain of the MOS transistor P5, and the drain / substrate region is the output node 1 of the voltage switching circuit.
8a, the gate of which is connected to the first inverter circuit 2
PMOS transistor P6 connected to the output node of 1
And an input terminal connected to the output node of the first inverter circuit 21 and an output terminal connected to the NMOS transistor N4.
And a second inverter circuit 22 connected to the gate of the. The drain interconnection node of the transistors P3 and N3 is connected to the gate of the PMOS transistor P8. Next, the operation of the circuit of FIG. 2 will be described.

Now, when the ground potential Vss is applied to the pad 15, the transistor P1 is turned off, the transistor N1 is turned on, the output of the first inverter circuit 21 is at "H" level, and the transistor N2 is turned on. , The transistor P2 is turned off, and the transistor P7 is turned on.

At this time, since the output of the first inverter circuit 21 is at "H" level and the output of the second inverter circuit 22 is at "L" level, the transistor N3 is turned on, the transistor N4 is turned off, and the transistor N4 is turned off. P3 is off, transistor P4 is on, and transistor P5 is off. Then, the transistor P6 is turned off by the output “H” of the first inverter circuit 21.

As a result, the output node 1 of the voltage switching circuit
8a, the power supply voltage Vcc appears via the transistor P7, and this power supply voltage Vcc is applied to the P-type diffusion resistors 19 and P.
It is supplied to the substrate region of the MOS transistor P8.

At this time, the switching transistor P8 is turned on by the "L" level of the drain node of the transistor N3, and the pull-up resistor 19 pulls up the potential of the pad 15.

Even when the power supply voltage Vcc is applied to the pad 15, the power supply voltage Vcc appears at the output node 18a of the voltage switching circuit and the power supply voltage Vcc is applied, as in the above-described operation.
cc is supplied to the substrate region of the P-type diffused resistor 19 and the PMOS transistor P8.

On the other hand, the power supply voltage Vcc is applied to the pad 15.
When a higher voltage (eg program voltage Vpp) is applied, the transistor P1 is turned on, the output of the first inverter circuit 21 is at "L" level, the transistor P2 is on, the transistor N2 is off, and the transistor P2 is off.
7 is off. Here, the channel length L of the transistor N1 is set larger than usual in order to suppress a shoot-through current.

At this time, since the output of the first inverter circuit 21 is at the "L" level and the output of the second inverter circuit 22 is at the "H" level, the transistor N3 is turned off, the transistor N4 is turned on, and the transistor N4 is turned on. P3 is on, transistor P4 is off, and transistor P5 is on. The transistor P6 is turned on by the output "L" of the first inverter circuit 21.

As a result, the output node 1 of the voltage switching circuit 1
The applied voltage Vpp of the pad 15 is applied to the transistor P at 8a.
5 and P6, the applied voltage Vpp is supplied to the substrate region of the P-type diffused resistor 19 and the PMOS transistor P8.

At this time, the switching transistor P8 is turned off by the "H" level of the drain node of the transistor P3, so that the voltage Vpp applied to the pad 15 is increased.
Are prohibited from being transmitted to the pull-up resistor 19. The PMOS transistor P8 is connected to the pad 1
It may be omitted if there is no problem in transmitting the applied voltage of 5 to the pull-up resistor 19.

In the above embodiment, the case where the positive power supply voltage is used has been described, but the case where the negative power supply voltage is used can also be realized according to the above embodiment. That is, pad 1
It is detected whether or not the absolute value of the voltage applied to 5 is greater than or equal to the absolute value of the power supply voltage of the EPROM, and the pad application voltage or the EPROM power supply voltage is switched and supplied to the well region according to the detection output. Can be carried out.

[0036]

As described above, according to the semiconductor integrated circuit of the present invention, a voltage higher than the power supply voltage is applied to the pad connected to the impurity diffusion layer region formed in the well region in the semiconductor substrate. Even in such a case, a bias can be applied to the well region so as not to increase the current consumption and malfunction of the peripheral circuits.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing a part of an EPROM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a substrate bias circuit in FIG.

FIG. 3 is a sectional view showing a part of a substrate of a conventional EPROM.

[Explanation of symbols]

11 ... P type substrate, 12 ... N type well region, 13 ... Electrode region (N + type region), 14 ... P type diffusion resistance region, 15 ... Pad, 16 ... Substrate bias circuit, 17 ... Power supply voltage level detection circuit, 18 ... Voltage switching circuit, 181 ... Power supply voltage supply circuit, 182 ... External voltage supply circuit, 18a ... Output node of voltage switching circuit, 19 ... P-type diffusion resistor for pull-up,
P8 ... PMOS transistor for switch.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/115

Claims (2)

[Claims] 1. A semiconductor substrate of a first conductivity type, a well region of a conductivity type opposite to that of the first conductivity type formed in the semiconductor substrate, and a first conductivity type of a well region formed in the well region. An impurity diffusion layer region, a pad for applying an external voltage to this impurity diffusion layer region, a detection circuit for detecting whether or not the voltage applied to this pad is equal to or higher than the power supply voltage of the integrated circuit, and this detection A semiconductor integrated circuit comprising: a switching circuit that switches and supplies the voltage applied to the pad or the power supply voltage of the integrated circuit to the well region according to a detection output of the circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the impurity diffusion layer region is a diffusion resistor, and the switch M is connected in series between the diffusion resistor and the pad.
A semiconductor integrated circuit having an OS transistor inserted therein.