JPH04109678A - Thin film semiconductor device - Google Patents

Thin film semiconductor device

Info

Publication number
JPH04109678A
JPH04109678A JP22884890A JP22884890A JPH04109678A JP H04109678 A JPH04109678 A JP H04109678A JP 22884890 A JP22884890 A JP 22884890A JP 22884890 A JP22884890 A JP 22884890A JP H04109678 A JPH04109678 A JP H04109678A
Authority
JP
Japan
Prior art keywords
thin film
active layer
semiconductor device
film semiconductor
contact hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22884890A
Other languages
Japanese (ja)
Inventor
Zenichi Akiyama
善一 秋山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP22884890A priority Critical patent/JPH04109678A/en
Publication of JPH04109678A publication Critical patent/JPH04109678A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To prevent disconnection of metal electrodes generated during microminiaturization of elements and improve reliability of metal electrodes by covering a region corresponding to the lower part of a contact hole on a glass substrate and the lower part of an active layer with an insulating film having resistance to hydrogen fluoride. CONSTITUTION:A thin film semiconductor device forming thin film semiconductor elements on a glass substrate 1, where a contact hole 7, used to lead the source-drain electrodes from an isolated active layer 2, is formed in such a shape as reaching not only the active layer 2 but also external side thereof and a region at least corresponding to the lower part of the contact hole 7 on the glass substrate 1 and the lower part of the active layer 2 are covered with an insulating film 10 having resistance to hydrogen fluoride. Thereby, disconnection of contact area is not generated and reliability of the stepped portion can be improved in the micro-miniaturized thin film semiconductor device.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、薄膜半導体素子やイメージセンサの製作に有
用な薄膜半導体装置用の絶縁基板、特に該基板上にシリ
コン窒化膜の薄膜による部分被覆を形成した絶縁基板上
に薄膜半導体素子を形成した薄膜半導体装置に関する。
[Detailed Description of the Invention] [Technical Field] The present invention relates to an insulating substrate for a thin film semiconductor device useful for manufacturing thin film semiconductor elements and image sensors, and particularly to an insulating substrate for forming a partial coating with a thin film of silicon nitride on the substrate. The present invention relates to a thin film semiconductor device in which a thin film semiconductor element is formed on an insulating substrate.

〔従来技術〕[Prior art]

通常薄膜トランジスタを形成するには、絶縁基板上に多
結晶シリコンを基板全面に形成し、フォトリソグラフ技
術等を用いて製造するのが一般的である。この場合、基
板からの不純物(Na、に、Ca、Fe、AQ、W等)
の拡散により製造装置やその雰囲気および薄膜トランジ
スタが汚染されてしまい、その特性変動を引き起こし、
信頼性に問題があった。
Normally, to form a thin film transistor, polycrystalline silicon is formed on the entire surface of an insulating substrate and manufactured using photolithography technology or the like. In this case, impurities from the substrate (Na, Ca, Fe, AQ, W, etc.)
The diffusion of the
There were reliability issues.

ガラス基板上にSin、、SiN、PSG等の薄膜で被
覆した後、素子を形成する技術としては特開昭59−8
9436号公報がある。これは、ガラス基板に含まれる
可動イオンのブロッキング層としての被覆を全面(表面
、表面+裏面)に施すものである。
A technique for forming an element after coating a glass substrate with a thin film of Sin, SiN, PSG, etc. is disclosed in Japanese Patent Application Laid-Open No. 59-8.
There is a publication No. 9436. This is a method in which the entire surface (front surface, front surface + back surface) is coated as a blocking layer for mobile ions contained in the glass substrate.

しかし、絶縁基板から薄膜半導体素子へのW。However, W from the insulating substrate to the thin film semiconductor element.

Fe等の重金属、Na、に等のアルカリ金属等の不純物
拡散による汚染防止のために、該基板の被覆膜として酸
化珪素膜、リンガラス膜、シリコン窒化膜等の絶縁膜を
使用する場合、全面被覆では、成膜による欠陥、および
後の熱処理によるクラックの発生、膜生成時の膜の内部
応力あるいは、111!縁膜と絶縁基板の熱膨張率の差
に起因する熱応力等によってM#膜のハガレやクラック
が発生し易い欠点がある。このため折角絶縁膜を基板全
面に被覆しても、所期の効果が得られないことが判明し
た。
In order to prevent contamination due to diffusion of impurities such as heavy metals such as Fe, alkali metals such as Na, etc., when using an insulating film such as a silicon oxide film, a phosphorous glass film, or a silicon nitride film as a coating film for the substrate, In case of full-surface coating, defects may occur due to film formation, cracks may occur due to subsequent heat treatment, internal stress of the film during film formation, or 111! There is a drawback that peeling and cracking of the M# film is likely to occur due to thermal stress caused by the difference in coefficient of thermal expansion between the edge film and the insulating substrate. For this reason, it has been found that even if the entire surface of the substrate is coated with an insulating film, the desired effect cannot be obtained.

ところで、ガラス基板上に薄膜半導体素子を形成する薄
膜半導体装置において、分離された活性層からソース、
ドレイン電極を引き出すためのコンタクトホールが、活
性層のみならず活性層の外部まで達する形状のコンタク
トホールを有する薄膜半導体装置の基本例を第2図に示
す。コンタクトホール7は共に活性層領域に。
By the way, in a thin film semiconductor device in which a thin film semiconductor element is formed on a glass substrate, source, source, and
FIG. 2 shows a basic example of a thin film semiconductor device in which a contact hole for drawing out a drain electrode is shaped to reach not only the active layer but also the outside of the active layer. Both contact holes 7 are in the active layer region.

活性層領域より小さな寸法で形成する。そのため、コン
タクトホール7の寸法及び活性層領域の寸法(L工)が
プロセスマージンも含め制限をうけ、素子の微細化を制
限してしまうという欠点があった。
It is formed to have a smaller size than the active layer region. As a result, the dimensions of the contact hole 7 and the dimensions of the active layer region (L process), including the process margin, are limited, which has the drawback of limiting miniaturization of the device.

活性層領域が薄膜で分離されている薄膜半導体装置にお
いて、その特徴を生かし素子の微細化を次のように図る
ことも考えられる。
In a thin film semiconductor device in which the active layer region is separated by a thin film, it is conceivable to utilize this feature to miniaturize the element in the following manner.

すなわち、コンタクトホール寸法を活性層領域上のみに
限定しないことにより活性層の寸法の制限を減少し素子
の微細化を図ることができる。
That is, by not limiting the size of the contact hole only above the active layer region, restrictions on the size of the active layer can be reduced and the device can be miniaturized.

このときの薄膜半導体装置図を第3図に示す。A diagram of the thin film semiconductor device at this time is shown in FIG.

しかし、第3図に示す構造では次の問題点が生しる。す
なわちコンタクトホール開孔にHFを含むエッチャント
でのウェット加工プロセスを行うと、第4図に示すよう
に活性層端にくぼみ6を生じ、次工程のメタル電極に断
IIIA9を生じてしまうことである。ドライプロセス
、CDE(Chemical Dry Etching
)でも同様な形状のくぼみ6を生じる6一方、RI E
 (Reactive IonEtching)では材
料の選択性が低く薄膜半導体プロセスには不向きである
However, the structure shown in FIG. 3 has the following problem. In other words, if a wet processing process is performed using an etchant containing HF to open a contact hole, a depression 6 will be created at the edge of the active layer as shown in FIG. 4, and a break IIIA9 will be created in the metal electrode in the next step. . Dry process, CDE (Chemical Dry Etching)
) also produces a depression 6 of a similar shape 6 On the other hand, RIE
(Reactive Ion Etching) has low material selectivity and is unsuitable for thin film semiconductor processes.

〔目  的〕〔the purpose〕

本発明は、薄膜半導体装置において、上述の微細化を行
った時に生じるメタル電極の断線を防ぎ、メタル電極の
信頼性を向上させることを目的とするものである。
An object of the present invention is to prevent disconnection of metal electrodes that occurs when the above-mentioned miniaturization is performed in a thin film semiconductor device, and to improve reliability of the metal electrodes.

〔構  成〕〔composition〕

上記目的を達成するため、本発明者は鋭意研究を重ねた
結果、薄膜半導体装置の素子分離した活性層近傍に、部
分的被覆を施すことにより、かつ、部分的に被覆する場
合には、ダストによる欠陥、クラック等の問題は生じる
ことなく、メタル電極の断線防止が可能となることを確
認し、本発明を完成するに至った。
In order to achieve the above object, the present inventor has conducted intensive research and found that by applying partial coating to the vicinity of the isolated active layer of a thin film semiconductor device, and in the case of partial coating, dust The present invention was completed by confirming that it is possible to prevent disconnection of metal electrodes without causing problems such as defects and cracks caused by the above.

すなわち、本発明は、ガラス基板上に薄膜半導体素子を
形成した薄膜半導体装置であって。
That is, the present invention is a thin film semiconductor device in which a thin film semiconductor element is formed on a glass substrate.

分離された活性層からソース、゛ドレイン電極を引き出
すためのコンタクトホールが、活性層上のみならず、活
性層の外部まで達する形状のコンタクトホールを有する
薄膜半導体装置においてガラス基板上の少くともコンタ
クトホールの下部に相当する個所と活性層の下部とが耐
フッ化水素性絶縁膜で被覆されていることを特徴とする
薄膜半導体装置に関する。
In a thin film semiconductor device in which a contact hole for drawing out source and drain electrodes from a separated active layer has a shape that reaches not only above the active layer but also to the outside of the active layer, at least a contact hole on a glass substrate is used. The present invention relates to a thin film semiconductor device characterized in that a portion corresponding to the lower part of the active layer and a lower part of the active layer are covered with a hydrogen fluoride-resistant insulating film.

航記耐フッ化水素性絶縁膜は、耐熱性(好ましくは10
00℃において安定)であり、半導体材料にドーパント
となる不純物を与えないものであって、具体的には窒化
けい素膜を挙げることができる。この膜厚は通常0.0
5〜1μm、とくに好ましくは0.2〜0.4μmであ
る。
The hydrogen fluoride-resistant insulating film has heat resistance (preferably 10
It is stable at 00° C.) and does not add impurities that become dopants to the semiconductor material, and a specific example is a silicon nitride film. This film thickness is usually 0.0
It is 5 to 1 μm, particularly preferably 0.2 to 0.4 μm.

図面により1本発明の構成を具体的に説明する。The configuration of the present invention will be specifically explained with reference to the drawings.

本発明においては、第1図に示すようにシリコン窒化膜
のような耐HF性のある絶縁膜10を、部分的にガラス
基板上に被覆して、薄膜半導体装置が形成されるもので
ある。
In the present invention, as shown in FIG. 1, a thin film semiconductor device is formed by partially covering a glass substrate with an HF-resistant insulating film 10 such as a silicon nitride film.

すなわち、石英基板1の上にシリコン窒化膜10、ポリ
シリコンよりなる活性層2、活性M2を熱酸化して形成
したゲート酸化膜3、ポリシリコンからなるゲート電極
4が形成された薄膜半導体装置であり、ソース、ドレイ
ン電極を引き出すためのコンタクトホール7は活性層上
のみならず、活性層の外部まで達し、がっシリコン窒化
膜領域外にならないような形状のコンタクトホールを形
成するものである。
That is, it is a thin film semiconductor device in which a silicon nitride film 10, an active layer 2 made of polysilicon, a gate oxide film 3 formed by thermally oxidizing active M2, and a gate electrode 4 made of polysilicon are formed on a quartz substrate 1. The contact hole 7 for drawing out the source and drain electrodes is formed in such a shape that it reaches not only above the active layer but also to the outside of the active layer and does not extend outside the silicon nitride film region.

〔実施例〕〔Example〕

本発明の詳細な説明するが、本発明はこれによって限定
されるものではない。
Although the present invention will be described in detail, the present invention is not limited thereto.

第1図に示すように、本発明の薄膜半導体装置は、先ず
石英基板上上にシリコン窒化膜(窒化けい素膜)をLP
−CVD法を用いて1000人堆積しフォトリソグラフ
ィエツチング技術で被覆層10を形成する。
As shown in FIG. 1, the thin film semiconductor device of the present invention is manufactured by first depositing a silicon nitride film (silicon nitride film) on a quartz substrate.
- 1000 layers are deposited using the CVD method, and the covering layer 10 is formed using the photolithography etching technique.

次にポリシリコンをLP−CVD法を用いて1200人
厚さに堆積し、フォトリングラフィエツチング技術でト
ランジスタの活性層2を形成する。乾燥酸素雰囲気中で
1020℃で熱酸化を行い、ポリシリコンの表面に80
0人の熱酸化膜3を生長させる。引き続いてポリシリコ
ンをLP−CVD法を用いて3000人堆積し、フォト
リングラフィエツチング技術で、ゲート電極4を形成す
る。次にイオン注入法により、りん(またはボロン)を
注入エネルギー90Kev (ボロンの場合30Key
)、トープ量4 X 10”atomic/adの条件
で注入する。この時、ゲート電極4とソーストレイン領
域は同時に不純物注入が行われ、ソースドレイン領域は
ゲート電極でセルフアライメントされる。活性化は、N
2雰囲気中で900℃30分間行う。次に眉間絶縁膜5
としてLP−CVD法で5in2を3000人堆積し、
コンタクトホール7をフォトリソグラフィエツチング技
術で形成する。この時、コンタクトホール7は活性層2
上のみならず活性層2の外部まで達する形状のコンタク
トホールのフォトマスクを使用して露光を行う。最後に
メタル電極8はスパッタリング法でAQを堆積し、フォ
トリソグラフィエツチング技術でパターニングして本発
明の薄膜M○Sトランジスタ装置が完成する。
Next, polysilicon is deposited to a thickness of 1200 nm using the LP-CVD method, and the active layer 2 of the transistor is formed using the photophosphorographic etching technique. Thermal oxidation was performed at 1020°C in a dry oxygen atmosphere to give an 80%
A thermal oxide film 3 of 0 is grown. Subsequently, 3,000 layers of polysilicon are deposited using the LP-CVD method, and the gate electrode 4 is formed using photophosphorographic etching technology. Next, using the ion implantation method, phosphorus (or boron) is implanted with an energy of 90Kev (30Kev for boron).
), and the doping amount is 4 x 10" atomic/ad. At this time, the gate electrode 4 and the source train region are implanted with impurities at the same time, and the source and drain regions are self-aligned with the gate electrode. Activation , N
2 atmosphere for 30 minutes at 900°C. Next, the eyebrow insulating film 5
3000 people deposited 5in2 using the LP-CVD method,
Contact hole 7 is formed using photolithography etching technology. At this time, the contact hole 7 is connected to the active layer 2.
Exposure is performed using a photomask with contact holes shaped to reach not only the top but also the outside of the active layer 2. Finally, for the metal electrode 8, AQ is deposited by sputtering and patterned by photolithography to complete the thin film M○S transistor device of the present invention.

〔効  果〕〔effect〕

本発明は、以上説明したように構成されているから、微
細化した薄膜半導体装置においてコンタクト部での断線
がなく、かつそのステップ部での信頼性が向上するとい
う効果が奏され、産業上極めて有用である。
Since the present invention is configured as described above, it is possible to achieve the effect that there is no disconnection at the contact portion in a miniaturized thin film semiconductor device and the reliability at the step portion is improved, which is extremely important in industry. Useful.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明薄膜半導体装置の構造を示す断面図、
第2図は基本例の半導体装置の構造を示す断面図、第3
図は、従来例装置における欠陥の生じ易い部分を示す説
明図であり、第4図は、第3図の欠陥部分の拡大説明図
である。 1・・石英基板    2・・活 性 層3・・ゲート
酸化膜  4・・・ゲート電極5・・層間絶縁膜   
6・・く ぼ み7・・・コンタクトホール 8・・・メタル電極   9・・・断線部分10・・・
S i N、被覆層 第1図 第2図
FIG. 1 is a cross-sectional view showing the structure of the thin film semiconductor device of the present invention;
Figure 2 is a cross-sectional view showing the structure of a basic example semiconductor device;
The figure is an explanatory diagram showing a portion where defects are likely to occur in a conventional device, and FIG. 4 is an enlarged explanatory diagram of the defective portion in FIG. 3. 1...Quartz substrate 2...Active layer 3...Gate oxide film 4...Gate electrode 5...Interlayer insulating film
6... Depression 7... Contact hole 8... Metal electrode 9... Disconnection part 10...
S i N, coating layer Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims] 1、ガラス基板上に薄膜半導体素子を形成した薄膜半導
体装置であって、分離された活性層からソース、ドレイ
ン電極を引き出すためのコンタクトホールが活性層上の
みならず活性層外部まで達する形状のコンタクトホール
を有する薄膜半導体装置において、ガラス基板上の少く
ともコンタクトホールの下部に相当する個所と活性層の
下部とが耐フッ化水素性絶縁膜で被覆されていることを
特徴とする薄膜半導体装置。
1. A thin film semiconductor device in which a thin film semiconductor element is formed on a glass substrate, and the contact hole for drawing out the source and drain electrodes from the separated active layer reaches not only above the active layer but also outside the active layer. 1. A thin film semiconductor device having a hole, characterized in that at least a portion of a glass substrate corresponding to a lower portion of a contact hole and a lower portion of an active layer are covered with a hydrogen fluoride-resistant insulating film.
JP22884890A 1990-08-30 1990-08-30 Thin film semiconductor device Pending JPH04109678A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22884890A JPH04109678A (en) 1990-08-30 1990-08-30 Thin film semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22884890A JPH04109678A (en) 1990-08-30 1990-08-30 Thin film semiconductor device

Publications (1)

Publication Number Publication Date
JPH04109678A true JPH04109678A (en) 1992-04-10

Family

ID=16882823

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22884890A Pending JPH04109678A (en) 1990-08-30 1990-08-30 Thin film semiconductor device

Country Status (1)

Country Link
JP (1) JPH04109678A (en)

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